Lines Matching +full:mipi +full:- +full:dsi2
1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
269 /* dual-channel */
277 /* being a phy for other mipi hosts */
360 return -EINVAL; in max_mbps_to_parameter()
365 writel(val, dsi->base + reg); in dsi_write()
391 * ns2bc - Nanoseconds to byte clock cycles
395 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); in ns2bc()
399 * ns2ui - Nanoseconds to UI time periods
403 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); in ns2ui()
411 if (dsi->phy) in dw_mipi_dsi_phy_init()
417 * 000 - between 80 and 200 MHz in dw_mipi_dsi_phy_init()
418 * 001 - between 200 and 300 MHz in dw_mipi_dsi_phy_init()
419 * 010 - between 300 and 500 MHz in dw_mipi_dsi_phy_init()
420 * 011 - between 500 and 700 MHz in dw_mipi_dsi_phy_init()
421 * 100 - between 700 and 900 MHz in dw_mipi_dsi_phy_init()
422 * 101 - between 900 and 1100 MHz in dw_mipi_dsi_phy_init()
423 * 110 - between 1100 and 1300 MHz in dw_mipi_dsi_phy_init()
424 * 111 - between 1300 and 1500 MHz in dw_mipi_dsi_phy_init()
426 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; in dw_mipi_dsi_phy_init()
428 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_phy_init()
430 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_phy_init()
432 dsi->lane_mbps); in dw_mipi_dsi_phy_init()
436 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
438 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); in dw_mipi_dsi_phy_init()
458 INPUT_DIVIDER(dsi->input_div)); in dw_mipi_dsi_phy_init()
460 LOOP_DIV_LOW_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
466 * Only in this way can we get correct mipi phy pll frequency. in dw_mipi_dsi_phy_init()
471 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
517 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
527 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); in dw_mipi_dsi_phy_power_on()
529 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); in dw_mipi_dsi_phy_power_on()
533 phy_configure(dsi->phy, &dsi->phy_opts); in dw_mipi_dsi_phy_power_on()
534 phy_power_on(dsi->phy); in dw_mipi_dsi_phy_power_on()
541 phy_power_off(dsi->phy); in dw_mipi_dsi_phy_power_off()
553 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; in dw_mipi_dsi_get_lane_mbps()
561 dsi->format = format; in dw_mipi_dsi_get_lane_mbps()
562 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in dw_mipi_dsi_get_lane_mbps()
564 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
566 dsi->format); in dw_mipi_dsi_get_lane_mbps()
570 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); in dw_mipi_dsi_get_lane_mbps()
577 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
582 if (dsi->phy) { in dw_mipi_dsi_get_lane_mbps()
583 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, in dw_mipi_dsi_get_lane_mbps()
585 &dsi->phy_opts.mipi_dphy); in dw_mipi_dsi_get_lane_mbps()
586 dsi->lane_mbps = target_mbps; in dw_mipi_dsi_get_lane_mbps()
587 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
592 fin = clk_get_rate(dsi->pllref_clk); in dw_mipi_dsi_get_lane_mbps()
611 * Due to the use of a "by 2 pre-scaler," the range of the in dw_mipi_dsi_get_lane_mbps()
625 delta = abs(fout - tmp); in dw_mipi_dsi_get_lane_mbps()
635 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); in dw_mipi_dsi_get_lane_mbps()
636 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
637 dsi->input_div = best_prediv; in dw_mipi_dsi_get_lane_mbps()
638 dsi->feedback_div = best_fbdiv; in dw_mipi_dsi_get_lane_mbps()
640 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); in dw_mipi_dsi_get_lane_mbps()
641 return -EINVAL; in dw_mipi_dsi_get_lane_mbps()
663 /* Table A-3 High-Speed Transition Times */
717 i--; in dw_mipi_dsi_phy_get_timing()
734 if (dsi->cdata->lanecfg1_grf_reg) in dw_mipi_dsi_rockchip_config()
735 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, in dw_mipi_dsi_rockchip_config()
736 dsi->cdata->lanecfg1); in dw_mipi_dsi_rockchip_config()
738 if (dsi->cdata->lanecfg2_grf_reg) in dw_mipi_dsi_rockchip_config()
739 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, in dw_mipi_dsi_rockchip_config()
740 dsi->cdata->lanecfg2); in dw_mipi_dsi_rockchip_config()
742 if (dsi->cdata->enable_grf_reg) in dw_mipi_dsi_rockchip_config()
743 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, in dw_mipi_dsi_rockchip_config()
744 dsi->cdata->enable); in dw_mipi_dsi_rockchip_config()
750 if (dsi->cdata->lcdsel_grf_reg) in dw_mipi_dsi_rockchip_set_lcdsel()
751 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, in dw_mipi_dsi_rockchip_set_lcdsel()
752 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); in dw_mipi_dsi_rockchip_set_lcdsel()
763 switch (dsi->format) { in dw_mipi_dsi_encoder_atomic_check()
765 s->output_mode = ROCKCHIP_OUT_MODE_P888; in dw_mipi_dsi_encoder_atomic_check()
768 s->output_mode = ROCKCHIP_OUT_MODE_P666; in dw_mipi_dsi_encoder_atomic_check()
771 s->output_mode = ROCKCHIP_OUT_MODE_P565; in dw_mipi_dsi_encoder_atomic_check()
775 return -EINVAL; in dw_mipi_dsi_encoder_atomic_check()
778 s->output_type = DRM_MODE_CONNECTOR_DSI; in dw_mipi_dsi_encoder_atomic_check()
779 if (dsi->slave) in dw_mipi_dsi_encoder_atomic_check()
780 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL; in dw_mipi_dsi_encoder_atomic_check()
790 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, in dw_mipi_dsi_encoder_enable()
791 &dsi->encoder.encoder); in dw_mipi_dsi_encoder_enable()
800 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
802 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_encoder_enable()
807 if (dsi->slave) in dw_mipi_dsi_encoder_enable()
808 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); in dw_mipi_dsi_encoder_enable()
810 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
822 struct drm_encoder *encoder = &dsi->encoder.encoder; in rockchip_dsi_drm_create_encoder()
825 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, in rockchip_dsi_drm_create_encoder()
826 dsi->dev->of_node); in rockchip_dsi_drm_create_encoder()
845 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); in dw_mipi_dsi_rockchip_find_second()
847 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); in dw_mipi_dsi_rockchip_find_second()
852 match->compatible))) { in dw_mipi_dsi_rockchip_find_second()
856 if (node == dsi->dev->of_node) in dw_mipi_dsi_rockchip_find_second()
863 /* same display device in port1-ep0 for both */ in dw_mipi_dsi_rockchip_find_second()
865 struct dw_mipi_dsi_rockchip *dsi2; in dw_mipi_dsi_rockchip_find_second() local
880 return ERR_PTR(-EPROBE_DEFER); in dw_mipi_dsi_rockchip_find_second()
882 dsi2 = platform_get_drvdata(pdev); in dw_mipi_dsi_rockchip_find_second()
883 if (!dsi2) { in dw_mipi_dsi_rockchip_find_second()
885 return ERR_PTR(-EPROBE_DEFER); in dw_mipi_dsi_rockchip_find_second()
888 return &pdev->dev; in dw_mipi_dsi_rockchip_find_second()
914 master1 = of_property_read_bool(dsi->dev->of_node, in dw_mipi_dsi_rockchip_bind()
915 "clock-master"); in dw_mipi_dsi_rockchip_bind()
916 master2 = of_property_read_bool(second->of_node, in dw_mipi_dsi_rockchip_bind()
917 "clock-master"); in dw_mipi_dsi_rockchip_bind()
920 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); in dw_mipi_dsi_rockchip_bind()
921 return -EINVAL; in dw_mipi_dsi_rockchip_bind()
925 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); in dw_mipi_dsi_rockchip_bind()
926 return -EINVAL; in dw_mipi_dsi_rockchip_bind()
929 /* we are the slave in dual-DSI */ in dw_mipi_dsi_rockchip_bind()
931 dsi->is_slave = true; in dw_mipi_dsi_rockchip_bind()
935 dsi->slave = dev_get_drvdata(second); in dw_mipi_dsi_rockchip_bind()
936 if (!dsi->slave) { in dw_mipi_dsi_rockchip_bind()
938 return -ENODEV; in dw_mipi_dsi_rockchip_bind()
941 dsi->slave->is_slave = true; in dw_mipi_dsi_rockchip_bind()
942 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); in dw_mipi_dsi_rockchip_bind()
946 pm_runtime_get_sync(dsi->dev); in dw_mipi_dsi_rockchip_bind()
947 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
948 pm_runtime_get_sync(dsi->slave->dev); in dw_mipi_dsi_rockchip_bind()
950 ret = clk_prepare_enable(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
957 * With the GRF clock running, write lane and dual-mode configurations in dw_mipi_dsi_rockchip_bind()
962 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
964 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_rockchip_bind()
969 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
970 dw_mipi_dsi_rockchip_config(dsi->slave); in dw_mipi_dsi_rockchip_bind()
972 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
979 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, in dw_mipi_dsi_rockchip_bind()
980 dev->of_node, 0, 0); in dw_mipi_dsi_rockchip_bind()
982 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); in dw_mipi_dsi_rockchip_bind()
988 dsi->dsi_bound = true; in dw_mipi_dsi_rockchip_bind()
993 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
995 pm_runtime_put(dsi->dev); in dw_mipi_dsi_rockchip_bind()
996 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
997 pm_runtime_put(dsi->slave->dev); in dw_mipi_dsi_rockchip_bind()
1008 if (dsi->is_slave) in dw_mipi_dsi_rockchip_unbind()
1011 dsi->dsi_bound = false; in dw_mipi_dsi_rockchip_unbind()
1013 dw_mipi_dsi_unbind(dsi->dmd); in dw_mipi_dsi_rockchip_unbind()
1015 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_unbind()
1017 pm_runtime_put(dsi->dev); in dw_mipi_dsi_rockchip_unbind()
1018 if (dsi->slave) in dw_mipi_dsi_rockchip_unbind()
1019 pm_runtime_put(dsi->slave->dev); in dw_mipi_dsi_rockchip_unbind()
1034 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1036 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { in dw_mipi_dsi_rockchip_host_attach()
1037 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); in dw_mipi_dsi_rockchip_host_attach()
1038 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1039 return -EBUSY; in dw_mipi_dsi_rockchip_host_attach()
1042 dsi->usage_mode = DW_DSI_USAGE_DSI; in dw_mipi_dsi_rockchip_host_attach()
1043 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1045 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_attach()
1047 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", in dw_mipi_dsi_rockchip_host_attach()
1070 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1071 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_rockchip_host_attach()
1072 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1086 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_detach()
1088 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_detach()
1089 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_rockchip_host_detach()
1090 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_detach()
1106 * Just make the rest of Rockchip-DRM happy in dw_mipi_dsi_rockchip_dphy_bind()
1130 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1132 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { in dw_mipi_dsi_dphy_init()
1133 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); in dw_mipi_dsi_dphy_init()
1134 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1135 return -EBUSY; in dw_mipi_dsi_dphy_init()
1138 dsi->usage_mode = DW_DSI_USAGE_PHY; in dw_mipi_dsi_dphy_init()
1139 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1141 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_init()
1145 if (dsi->cdata->dphy_rx_init) { in dw_mipi_dsi_dphy_init()
1146 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_dphy_init()
1150 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_init()
1152 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_init()
1156 ret = dsi->cdata->dphy_rx_init(phy); in dw_mipi_dsi_dphy_init()
1157 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_init()
1158 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_init()
1166 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_init()
1168 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1169 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_dphy_init()
1170 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1179 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_exit()
1181 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_exit()
1182 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_dphy_exit()
1183 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_exit()
1190 struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy; in dw_mipi_dsi_dphy_configure()
1194 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); in dw_mipi_dsi_dphy_configure()
1198 dsi->dphy_config = *config; in dw_mipi_dsi_dphy_configure()
1199 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); in dw_mipi_dsi_dphy_configure()
1209 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", in dw_mipi_dsi_dphy_power_on()
1210 dsi->dphy_config.lanes, dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1212 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1214 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", in dw_mipi_dsi_dphy_power_on()
1215 dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1219 ret = pm_runtime_resume_and_get(dsi->dev); in dw_mipi_dsi_dphy_power_on()
1221 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1225 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_dphy_power_on()
1227 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1231 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1233 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1237 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1239 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1243 /* do soc-variant specific init */ in dw_mipi_dsi_dphy_power_on()
1244 if (dsi->cdata->dphy_rx_power_on) { in dw_mipi_dsi_dphy_power_on()
1245 ret = dsi->cdata->dphy_rx_power_on(phy); in dw_mipi_dsi_dphy_power_on()
1247 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1266 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1267 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1272 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1274 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1276 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_power_on()
1278 pm_runtime_put(dsi->dev); in dw_mipi_dsi_dphy_power_on()
1287 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_power_off()
1289 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_off()
1293 if (dsi->cdata->dphy_rx_power_off) { in dw_mipi_dsi_dphy_power_off()
1294 ret = dsi->cdata->dphy_rx_power_off(phy); in dw_mipi_dsi_dphy_power_off()
1296 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); in dw_mipi_dsi_dphy_power_off()
1299 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_off()
1300 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_power_off()
1302 pm_runtime_put(dsi->dev); in dw_mipi_dsi_dphy_power_off()
1321 * Re-configure DSI state, if we were previously initialized. We need in dw_mipi_dsi_rockchip_resume()
1322 * to do this before rockchip_drm_drv tries to re-enable() any panels. in dw_mipi_dsi_rockchip_resume()
1324 if (dsi->dsi_bound) { in dw_mipi_dsi_rockchip_resume()
1325 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_rockchip_resume()
1327 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_rockchip_resume()
1332 if (dsi->slave) in dw_mipi_dsi_rockchip_resume()
1333 dw_mipi_dsi_rockchip_config(dsi->slave); in dw_mipi_dsi_rockchip_resume()
1335 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_rockchip_resume()
1347 struct device *dev = &pdev->dev; in dw_mipi_dsi_rockchip_probe()
1348 struct device_node *np = dev->of_node; in dw_mipi_dsi_rockchip_probe()
1358 return -ENOMEM; in dw_mipi_dsi_rockchip_probe()
1360 dsi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in dw_mipi_dsi_rockchip_probe()
1361 if (IS_ERR(dsi->base)) { in dw_mipi_dsi_rockchip_probe()
1363 return PTR_ERR(dsi->base); in dw_mipi_dsi_rockchip_probe()
1368 if (cdata[i].reg == res->start) { in dw_mipi_dsi_rockchip_probe()
1369 dsi->cdata = &cdata[i]; in dw_mipi_dsi_rockchip_probe()
1376 if (!dsi->cdata) { in dw_mipi_dsi_rockchip_probe()
1377 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); in dw_mipi_dsi_rockchip_probe()
1378 return -EINVAL; in dw_mipi_dsi_rockchip_probe()
1382 dsi->phy = devm_phy_optional_get(dev, "dphy"); in dw_mipi_dsi_rockchip_probe()
1383 if (IS_ERR(dsi->phy)) { in dw_mipi_dsi_rockchip_probe()
1384 ret = PTR_ERR(dsi->phy); in dw_mipi_dsi_rockchip_probe()
1385 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); in dw_mipi_dsi_rockchip_probe()
1389 dsi->pclk = devm_clk_get(dev, "pclk"); in dw_mipi_dsi_rockchip_probe()
1390 if (IS_ERR(dsi->pclk)) { in dw_mipi_dsi_rockchip_probe()
1391 ret = PTR_ERR(dsi->pclk); in dw_mipi_dsi_rockchip_probe()
1396 dsi->pllref_clk = devm_clk_get(dev, "ref"); in dw_mipi_dsi_rockchip_probe()
1397 if (IS_ERR(dsi->pllref_clk)) { in dw_mipi_dsi_rockchip_probe()
1398 if (dsi->phy) { in dw_mipi_dsi_rockchip_probe()
1403 dsi->pllref_clk = NULL; in dw_mipi_dsi_rockchip_probe()
1405 ret = PTR_ERR(dsi->pllref_clk); in dw_mipi_dsi_rockchip_probe()
1413 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { in dw_mipi_dsi_rockchip_probe()
1414 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); in dw_mipi_dsi_rockchip_probe()
1415 if (IS_ERR(dsi->phy_cfg_clk)) { in dw_mipi_dsi_rockchip_probe()
1416 ret = PTR_ERR(dsi->phy_cfg_clk); in dw_mipi_dsi_rockchip_probe()
1423 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { in dw_mipi_dsi_rockchip_probe()
1424 dsi->grf_clk = devm_clk_get(dev, "grf"); in dw_mipi_dsi_rockchip_probe()
1425 if (IS_ERR(dsi->grf_clk)) { in dw_mipi_dsi_rockchip_probe()
1426 ret = PTR_ERR(dsi->grf_clk); in dw_mipi_dsi_rockchip_probe()
1432 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in dw_mipi_dsi_rockchip_probe()
1433 if (IS_ERR(dsi->grf_regmap)) { in dw_mipi_dsi_rockchip_probe()
1435 return PTR_ERR(dsi->grf_regmap); in dw_mipi_dsi_rockchip_probe()
1438 dsi->dev = dev; in dw_mipi_dsi_rockchip_probe()
1439 dsi->pdata.base = dsi->base; in dw_mipi_dsi_rockchip_probe()
1440 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; in dw_mipi_dsi_rockchip_probe()
1441 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; in dw_mipi_dsi_rockchip_probe()
1442 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; in dw_mipi_dsi_rockchip_probe()
1443 dsi->pdata.priv_data = dsi; in dw_mipi_dsi_rockchip_probe()
1446 mutex_init(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_probe()
1448 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); in dw_mipi_dsi_rockchip_probe()
1449 if (IS_ERR(dsi->dphy)) { in dw_mipi_dsi_rockchip_probe()
1450 DRM_DEV_ERROR(&pdev->dev, "failed to create PHY\n"); in dw_mipi_dsi_rockchip_probe()
1451 return PTR_ERR(dsi->dphy); in dw_mipi_dsi_rockchip_probe()
1454 phy_set_drvdata(dsi->dphy, dsi); in dw_mipi_dsi_rockchip_probe()
1459 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); in dw_mipi_dsi_rockchip_probe()
1460 if (IS_ERR(dsi->dmd)) { in dw_mipi_dsi_rockchip_probe()
1461 ret = PTR_ERR(dsi->dmd); in dw_mipi_dsi_rockchip_probe()
1462 if (ret != -EPROBE_DEFER) in dw_mipi_dsi_rockchip_probe()
1475 dw_mipi_dsi_remove(dsi->dmd); in dw_mipi_dsi_rockchip_remove()
1524 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1526 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1528 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1530 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_init()
1544 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1546 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1549 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1551 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1555 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1557 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1566 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1567 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0), in rk3399_dphy_tx1rx1_power_on()
1579 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_off()
1671 .compatible = "rockchip,px30-mipi-dsi",
1674 .compatible = "rockchip,rk3288-mipi-dsi",
1677 .compatible = "rockchip,rk3399-mipi-dsi",
1680 .compatible = "rockchip,rk3568-mipi-dsi",
1683 .compatible = "rockchip,rv1126-mipi-dsi",
1696 .name = "dw-mipi-dsi-rockchip",
1698 * For dual-DSI display, one DSI pokes at the other DSI's