Lines Matching full:dsi
363 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) in dsi_write() argument
365 writel(val, dsi->base + reg); in dsi_write()
368 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, in dw_mipi_dsi_phy_write() argument
377 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
379 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | in dw_mipi_dsi_phy_write()
382 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
384 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | in dw_mipi_dsi_phy_write()
387 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
393 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) in ns2bc() argument
395 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); in ns2bc()
401 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) in ns2ui() argument
403 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); in ns2ui()
408 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_init() local
411 if (dsi->phy) in dw_mipi_dsi_phy_init()
426 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; in dw_mipi_dsi_phy_init()
428 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_phy_init()
430 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_phy_init()
432 dsi->lane_mbps); in dw_mipi_dsi_phy_init()
436 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
438 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); in dw_mipi_dsi_phy_init()
442 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, in dw_mipi_dsi_phy_init()
448 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, in dw_mipi_dsi_phy_init()
450 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, in dw_mipi_dsi_phy_init()
454 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, in dw_mipi_dsi_phy_init()
457 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
458 INPUT_DIVIDER(dsi->input_div)); in dw_mipi_dsi_phy_init()
459 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
460 LOOP_DIV_LOW_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
468 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, in dw_mipi_dsi_phy_init()
470 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
471 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
473 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, in dw_mipi_dsi_phy_init()
476 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, in dw_mipi_dsi_phy_init()
478 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, in dw_mipi_dsi_phy_init()
481 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, in dw_mipi_dsi_phy_init()
485 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, in dw_mipi_dsi_phy_init()
488 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, in dw_mipi_dsi_phy_init()
493 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
494 TLP_PROGRAM_EN | ns2bc(dsi, 500)); in dw_mipi_dsi_phy_init()
495 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
496 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); in dw_mipi_dsi_phy_init()
497 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
498 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); in dw_mipi_dsi_phy_init()
499 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
500 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); in dw_mipi_dsi_phy_init()
501 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
502 BIT(5) | ns2bc(dsi, 100)); in dw_mipi_dsi_phy_init()
503 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, in dw_mipi_dsi_phy_init()
504 BIT(5) | (ns2bc(dsi, 60) + 7)); in dw_mipi_dsi_phy_init()
506 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
507 TLP_PROGRAM_EN | ns2bc(dsi, 500)); in dw_mipi_dsi_phy_init()
508 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
509 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); in dw_mipi_dsi_phy_init()
510 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
511 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); in dw_mipi_dsi_phy_init()
512 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
513 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); in dw_mipi_dsi_phy_init()
514 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
515 BIT(5) | ns2bc(dsi, 100)); in dw_mipi_dsi_phy_init()
517 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
524 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_power_on() local
527 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); in dw_mipi_dsi_phy_power_on()
529 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); in dw_mipi_dsi_phy_power_on()
533 phy_configure(dsi->phy, &dsi->phy_opts); in dw_mipi_dsi_phy_power_on()
534 phy_power_on(dsi->phy); in dw_mipi_dsi_phy_power_on()
539 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_power_off() local
541 phy_power_off(dsi->phy); in dw_mipi_dsi_phy_power_off()
549 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_get_lane_mbps() local
561 dsi->format = format; in dw_mipi_dsi_get_lane_mbps()
562 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in dw_mipi_dsi_get_lane_mbps()
564 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
566 dsi->format); in dw_mipi_dsi_get_lane_mbps()
577 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
582 if (dsi->phy) { in dw_mipi_dsi_get_lane_mbps()
585 &dsi->phy_opts.mipi_dphy); in dw_mipi_dsi_get_lane_mbps()
586 dsi->lane_mbps = target_mbps; in dw_mipi_dsi_get_lane_mbps()
587 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
592 fin = clk_get_rate(dsi->pllref_clk); in dw_mipi_dsi_get_lane_mbps()
635 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); in dw_mipi_dsi_get_lane_mbps()
636 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
637 dsi->input_div = best_prediv; in dw_mipi_dsi_get_lane_mbps()
638 dsi->feedback_div = best_fbdiv; in dw_mipi_dsi_get_lane_mbps()
640 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); in dw_mipi_dsi_get_lane_mbps()
732 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) in dw_mipi_dsi_rockchip_config() argument
734 if (dsi->cdata->lanecfg1_grf_reg) in dw_mipi_dsi_rockchip_config()
735 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, in dw_mipi_dsi_rockchip_config()
736 dsi->cdata->lanecfg1); in dw_mipi_dsi_rockchip_config()
738 if (dsi->cdata->lanecfg2_grf_reg) in dw_mipi_dsi_rockchip_config()
739 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, in dw_mipi_dsi_rockchip_config()
740 dsi->cdata->lanecfg2); in dw_mipi_dsi_rockchip_config()
742 if (dsi->cdata->enable_grf_reg) in dw_mipi_dsi_rockchip_config()
743 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, in dw_mipi_dsi_rockchip_config()
744 dsi->cdata->enable); in dw_mipi_dsi_rockchip_config()
747 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, in dw_mipi_dsi_rockchip_set_lcdsel() argument
750 if (dsi->cdata->lcdsel_grf_reg) in dw_mipi_dsi_rockchip_set_lcdsel()
751 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, in dw_mipi_dsi_rockchip_set_lcdsel()
752 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); in dw_mipi_dsi_rockchip_set_lcdsel()
761 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); in dw_mipi_dsi_encoder_atomic_check() local
763 switch (dsi->format) { in dw_mipi_dsi_encoder_atomic_check()
779 if (dsi->slave) in dw_mipi_dsi_encoder_atomic_check()
787 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); in dw_mipi_dsi_encoder_enable() local
790 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, in dw_mipi_dsi_encoder_enable()
791 &dsi->encoder.encoder); in dw_mipi_dsi_encoder_enable()
800 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
802 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_encoder_enable()
806 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux); in dw_mipi_dsi_encoder_enable()
807 if (dsi->slave) in dw_mipi_dsi_encoder_enable()
808 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); in dw_mipi_dsi_encoder_enable()
810 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
819 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, in rockchip_dsi_drm_create_encoder() argument
822 struct drm_encoder *encoder = &dsi->encoder.encoder; in rockchip_dsi_drm_create_encoder()
826 dsi->dev->of_node); in rockchip_dsi_drm_create_encoder()
840 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) in dw_mipi_dsi_rockchip_find_second() argument
845 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); in dw_mipi_dsi_rockchip_find_second()
847 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); in dw_mipi_dsi_rockchip_find_second()
856 if (node == dsi->dev->of_node) in dw_mipi_dsi_rockchip_find_second()
903 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_rockchip_bind() local
909 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_bind()
914 master1 = of_property_read_bool(dsi->dev->of_node, in dw_mipi_dsi_rockchip_bind()
920 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); in dw_mipi_dsi_rockchip_bind()
925 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); in dw_mipi_dsi_rockchip_bind()
929 /* we are the slave in dual-DSI */ in dw_mipi_dsi_rockchip_bind()
931 dsi->is_slave = true; in dw_mipi_dsi_rockchip_bind()
935 dsi->slave = dev_get_drvdata(second); in dw_mipi_dsi_rockchip_bind()
936 if (!dsi->slave) { in dw_mipi_dsi_rockchip_bind()
941 dsi->slave->is_slave = true; in dw_mipi_dsi_rockchip_bind()
942 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); in dw_mipi_dsi_rockchip_bind()
946 pm_runtime_get_sync(dsi->dev); in dw_mipi_dsi_rockchip_bind()
947 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
948 pm_runtime_get_sync(dsi->slave->dev); in dw_mipi_dsi_rockchip_bind()
950 ret = clk_prepare_enable(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
960 * commands over DSI. in dw_mipi_dsi_rockchip_bind()
962 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
964 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_rockchip_bind()
968 dw_mipi_dsi_rockchip_config(dsi); in dw_mipi_dsi_rockchip_bind()
969 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
970 dw_mipi_dsi_rockchip_config(dsi->slave); in dw_mipi_dsi_rockchip_bind()
972 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
974 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); in dw_mipi_dsi_rockchip_bind()
979 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, in dw_mipi_dsi_rockchip_bind()
982 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); in dw_mipi_dsi_rockchip_bind()
988 dsi->dsi_bound = true; in dw_mipi_dsi_rockchip_bind()
993 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
995 pm_runtime_put(dsi->dev); in dw_mipi_dsi_rockchip_bind()
996 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
997 pm_runtime_put(dsi->slave->dev); in dw_mipi_dsi_rockchip_bind()
1006 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_rockchip_unbind() local
1008 if (dsi->is_slave) in dw_mipi_dsi_rockchip_unbind()
1011 dsi->dsi_bound = false; in dw_mipi_dsi_rockchip_unbind()
1013 dw_mipi_dsi_unbind(dsi->dmd); in dw_mipi_dsi_rockchip_unbind()
1015 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_unbind()
1017 pm_runtime_put(dsi->dev); in dw_mipi_dsi_rockchip_unbind()
1018 if (dsi->slave) in dw_mipi_dsi_rockchip_unbind()
1019 pm_runtime_put(dsi->slave->dev); in dw_mipi_dsi_rockchip_unbind()
1030 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_rockchip_host_attach() local
1034 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1036 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { in dw_mipi_dsi_rockchip_host_attach()
1037 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); in dw_mipi_dsi_rockchip_host_attach()
1038 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1042 dsi->usage_mode = DW_DSI_USAGE_DSI; in dw_mipi_dsi_rockchip_host_attach()
1043 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1045 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_attach()
1047 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", in dw_mipi_dsi_rockchip_host_attach()
1052 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_host_attach()
1070 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1071 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_rockchip_host_attach()
1072 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1079 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_rockchip_host_detach() local
1082 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_host_detach()
1086 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_detach()
1088 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_detach()
1089 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_rockchip_host_detach()
1090 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_detach()
1127 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_init() local
1130 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1132 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { in dw_mipi_dsi_dphy_init()
1133 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); in dw_mipi_dsi_dphy_init()
1134 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1138 dsi->usage_mode = DW_DSI_USAGE_PHY; in dw_mipi_dsi_dphy_init()
1139 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1141 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_init()
1145 if (dsi->cdata->dphy_rx_init) { in dw_mipi_dsi_dphy_init()
1146 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_dphy_init()
1150 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_init()
1152 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_init()
1156 ret = dsi->cdata->dphy_rx_init(phy); in dw_mipi_dsi_dphy_init()
1157 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_init()
1158 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_init()
1166 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_init()
1168 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1169 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_dphy_init()
1170 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1177 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_exit() local
1179 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_exit()
1181 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_exit()
1182 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_dphy_exit()
1183 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_exit()
1191 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_configure() local
1198 dsi->dphy_config = *config; in dw_mipi_dsi_dphy_configure()
1199 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); in dw_mipi_dsi_dphy_configure()
1206 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_power_on() local
1209 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", in dw_mipi_dsi_dphy_power_on()
1210 dsi->dphy_config.lanes, dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1212 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1214 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", in dw_mipi_dsi_dphy_power_on()
1215 dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1219 ret = pm_runtime_resume_and_get(dsi->dev); in dw_mipi_dsi_dphy_power_on()
1221 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1225 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_dphy_power_on()
1227 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1231 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1233 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1237 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1239 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1244 if (dsi->cdata->dphy_rx_power_on) { in dw_mipi_dsi_dphy_power_on()
1245 ret = dsi->cdata->dphy_rx_power_on(phy); in dw_mipi_dsi_dphy_power_on()
1247 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1256 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0); in dw_mipi_dsi_dphy_power_on()
1257 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, in dw_mipi_dsi_dphy_power_on()
1259 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0); in dw_mipi_dsi_dphy_power_on()
1260 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0); in dw_mipi_dsi_dphy_power_on()
1261 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0); in dw_mipi_dsi_dphy_power_on()
1264 dw_mipi_dsi_phy_write(dsi, 0x0, 0); in dw_mipi_dsi_dphy_power_on()
1266 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1267 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1272 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1274 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1276 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_power_on()
1278 pm_runtime_put(dsi->dev); in dw_mipi_dsi_dphy_power_on()
1284 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_power_off() local
1287 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_power_off()
1289 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_off()
1293 if (dsi->cdata->dphy_rx_power_off) { in dw_mipi_dsi_dphy_power_off()
1294 ret = dsi->cdata->dphy_rx_power_off(phy); in dw_mipi_dsi_dphy_power_off()
1296 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); in dw_mipi_dsi_dphy_power_off()
1299 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_off()
1300 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_power_off()
1302 pm_runtime_put(dsi->dev); in dw_mipi_dsi_dphy_power_off()
1317 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_rockchip_resume() local
1321 * Re-configure DSI state, if we were previously initialized. We need in dw_mipi_dsi_rockchip_resume()
1324 if (dsi->dsi_bound) { in dw_mipi_dsi_rockchip_resume()
1325 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_rockchip_resume()
1327 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_rockchip_resume()
1331 dw_mipi_dsi_rockchip_config(dsi); in dw_mipi_dsi_rockchip_resume()
1332 if (dsi->slave) in dw_mipi_dsi_rockchip_resume()
1333 dw_mipi_dsi_rockchip_config(dsi->slave); in dw_mipi_dsi_rockchip_resume()
1335 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_rockchip_resume()
1349 struct dw_mipi_dsi_rockchip *dsi; in dw_mipi_dsi_rockchip_probe() local
1356 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); in dw_mipi_dsi_rockchip_probe()
1357 if (!dsi) in dw_mipi_dsi_rockchip_probe()
1360 dsi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in dw_mipi_dsi_rockchip_probe()
1361 if (IS_ERR(dsi->base)) { in dw_mipi_dsi_rockchip_probe()
1362 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); in dw_mipi_dsi_rockchip_probe()
1363 return PTR_ERR(dsi->base); in dw_mipi_dsi_rockchip_probe()
1369 dsi->cdata = &cdata[i]; in dw_mipi_dsi_rockchip_probe()
1376 if (!dsi->cdata) { in dw_mipi_dsi_rockchip_probe()
1377 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); in dw_mipi_dsi_rockchip_probe()
1382 dsi->phy = devm_phy_optional_get(dev, "dphy"); in dw_mipi_dsi_rockchip_probe()
1383 if (IS_ERR(dsi->phy)) { in dw_mipi_dsi_rockchip_probe()
1384 ret = PTR_ERR(dsi->phy); in dw_mipi_dsi_rockchip_probe()
1389 dsi->pclk = devm_clk_get(dev, "pclk"); in dw_mipi_dsi_rockchip_probe()
1390 if (IS_ERR(dsi->pclk)) { in dw_mipi_dsi_rockchip_probe()
1391 ret = PTR_ERR(dsi->pclk); in dw_mipi_dsi_rockchip_probe()
1396 dsi->pllref_clk = devm_clk_get(dev, "ref"); in dw_mipi_dsi_rockchip_probe()
1397 if (IS_ERR(dsi->pllref_clk)) { in dw_mipi_dsi_rockchip_probe()
1398 if (dsi->phy) { in dw_mipi_dsi_rockchip_probe()
1403 dsi->pllref_clk = NULL; in dw_mipi_dsi_rockchip_probe()
1405 ret = PTR_ERR(dsi->pllref_clk); in dw_mipi_dsi_rockchip_probe()
1413 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { in dw_mipi_dsi_rockchip_probe()
1414 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); in dw_mipi_dsi_rockchip_probe()
1415 if (IS_ERR(dsi->phy_cfg_clk)) { in dw_mipi_dsi_rockchip_probe()
1416 ret = PTR_ERR(dsi->phy_cfg_clk); in dw_mipi_dsi_rockchip_probe()
1423 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { in dw_mipi_dsi_rockchip_probe()
1424 dsi->grf_clk = devm_clk_get(dev, "grf"); in dw_mipi_dsi_rockchip_probe()
1425 if (IS_ERR(dsi->grf_clk)) { in dw_mipi_dsi_rockchip_probe()
1426 ret = PTR_ERR(dsi->grf_clk); in dw_mipi_dsi_rockchip_probe()
1432 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in dw_mipi_dsi_rockchip_probe()
1433 if (IS_ERR(dsi->grf_regmap)) { in dw_mipi_dsi_rockchip_probe()
1435 return PTR_ERR(dsi->grf_regmap); in dw_mipi_dsi_rockchip_probe()
1438 dsi->dev = dev; in dw_mipi_dsi_rockchip_probe()
1439 dsi->pdata.base = dsi->base; in dw_mipi_dsi_rockchip_probe()
1440 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; in dw_mipi_dsi_rockchip_probe()
1441 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; in dw_mipi_dsi_rockchip_probe()
1442 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; in dw_mipi_dsi_rockchip_probe()
1443 dsi->pdata.priv_data = dsi; in dw_mipi_dsi_rockchip_probe()
1444 platform_set_drvdata(pdev, dsi); in dw_mipi_dsi_rockchip_probe()
1446 mutex_init(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_probe()
1448 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); in dw_mipi_dsi_rockchip_probe()
1449 if (IS_ERR(dsi->dphy)) { in dw_mipi_dsi_rockchip_probe()
1451 return PTR_ERR(dsi->dphy); in dw_mipi_dsi_rockchip_probe()
1454 phy_set_drvdata(dsi->dphy, dsi); in dw_mipi_dsi_rockchip_probe()
1459 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); in dw_mipi_dsi_rockchip_probe()
1460 if (IS_ERR(dsi->dmd)) { in dw_mipi_dsi_rockchip_probe()
1461 ret = PTR_ERR(dsi->dmd); in dw_mipi_dsi_rockchip_probe()
1473 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); in dw_mipi_dsi_rockchip_remove() local
1475 dw_mipi_dsi_remove(dsi->dmd); in dw_mipi_dsi_rockchip_remove()
1518 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_init() local
1524 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1526 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1528 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1530 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_init()
1538 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_power_on() local
1541 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR); in rk3399_dphy_tx1rx1_power_on()
1544 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1546 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1549 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1551 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1555 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1557 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1562 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in rk3399_dphy_tx1rx1_power_on()
1566 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1567 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0), in rk3399_dphy_tx1rx1_power_on()
1577 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_power_off() local
1579 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_off()
1671 .compatible = "rockchip,px30-mipi-dsi",
1674 .compatible = "rockchip,rk3288-mipi-dsi",
1677 .compatible = "rockchip,rk3399-mipi-dsi",
1680 .compatible = "rockchip,rk3568-mipi-dsi",
1683 .compatible = "rockchip,rv1126-mipi-dsi",
1696 .name = "dw-mipi-dsi-rockchip",
1698 * For dual-DSI display, one DSI pokes at the other DSI's