30 #define DSI_PHY_RSTZ			0xa0
31 #define PHY_DISFORCEPLL			0
33 #define PHY_DISABLECLK			0
35 #define PHY_RSTZ			0
37 #define PHY_SHUTDOWNZ			0
38 #define PHY_UNSHUTDOWNZ			BIT(0)
40 #define DSI_PHY_IF_CFG			0xa4
41 #define N_LANES(n)			((((n) - 1) & 0x3) << 0)
42 #define PHY_STOP_WAIT_TIME(cycle)	(((cycle) & 0xff) << 8)
44 #define DSI_PHY_STATUS			0xb0
45 #define LOCK				BIT(0)
48 #define DSI_PHY_TST_CTRL0		0xb4
50 #define PHY_UNTESTCLK			0
51 #define PHY_TESTCLR			BIT(0)
52 #define PHY_UNTESTCLR			0
54 #define DSI_PHY_TST_CTRL1		0xb8
56 #define PHY_UNTESTEN			0
57 #define PHY_TESTDOUT(n)			(((n) & 0xff) << 8)
58 #define PHY_TESTDIN(n)			(((n) & 0xff) << 0)
60 #define DSI_INT_ST0			0xbc
61 #define DSI_INT_ST1			0xc0
62 #define DSI_INT_MSK0			0xc4
63 #define DSI_INT_MSK1			0xc8
69 #define VCO_RANGE_CON_SEL(val)	(((val) & 0x7) << 3)
70 #define VCO_IN_CAP_CON_DEFAULT	(0x0 << 1)
71 #define VCO_IN_CAP_CON_LOW	(0x1 << 1)
72 #define VCO_IN_CAP_CON_HIGH	(0x2 << 1)
73 #define REF_BIAS_CUR_SEL	BIT(0)
75 #define CP_CURRENT_3UA	0x1
76 #define CP_CURRENT_4_5UA	0x2
77 #define CP_CURRENT_7_5UA	0x6
78 #define CP_CURRENT_6UA	0x9
79 #define CP_CURRENT_12UA	0xb
80 #define CP_CURRENT_SEL(val)	((val) & 0xf)
83 #define LPF_RESISTORS_15_5KOHM	0x1
84 #define LPF_RESISTORS_13KOHM	0x2
85 #define LPF_RESISTORS_11_5KOHM	0x4
86 #define LPF_RESISTORS_10_5KOHM	0x8
87 #define LPF_RESISTORS_8KOHM	0x10
89 #define LPF_RESISTORS_SEL(val)	((val) & 0x3f)
91 #define HSFREQRANGE_SEL(val)	(((val) & 0x3f) << 1)
93 #define INPUT_DIVIDER(val)	(((val) - 1) & 0x7f)
94 #define LOW_PROGRAM_EN		0
96 #define LOOP_DIV_LOW_SEL(val)	(((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val)	((((val) - 1) >> 5) & 0xf)
104 #define BANDGAP_ON		BIT(0)
107 #define	TER_RESISTOR_LOW	0
110 #define SETRD_MAX		(0x7 << 2)
112 #define TER_RESISTORS_ON	BIT(0)
114 #define BIASEXTR_SEL(val)	((val) & 0x7)
115 #define BANDGAP_SEL(val)	((val) & 0x7)
120 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL		0x10
121 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS			0x11
122 #define PLL_LPF_AND_CP_CONTROL				0x12
123 #define PLL_INPUT_DIVIDER_RATIO				0x17
124 #define PLL_LOOP_DIVIDER_RATIO				0x18
125 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL	0x19
126 #define BANDGAP_AND_BIAS_CONTROL			0x20
127 #define TERMINATION_RESISTER_CONTROL			0x21
128 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY		0x22
129 #define HS_RX_CONTROL_OF_LANE_CLK			0x34
130 #define HS_RX_CONTROL_OF_LANE_0				0x44
131 #define HS_RX_CONTROL_OF_LANE_1				0x54
132 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL	0x60
133 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL	0x61
134 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL	0x62
135 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL	0x63
136 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL	0x64
137 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL		0x65
138 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL	0x70
139 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL	0x71
140 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL	0x72
141 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL	0x73
142 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL		0x74
143 #define HS_RX_DATA_LANE_THS_SETTLE_CONTROL		0x75
144 #define HS_RX_CONTROL_OF_LANE_2				0x84
145 #define HS_RX_CONTROL_OF_LANE_3				0x94
147 #define DW_MIPI_NEEDS_PHY_CFG_CLK	BIT(0)
150 #define PX30_GRF_PD_VO_CON1		0x0438
151 #define PX30_DSI_FORCETXSTOPMODE	(0xf << 7)
154 #define PX30_DSI_LCDC_SEL		BIT(0)
156 #define RK3288_GRF_SOC_CON6		0x025c
160 #define RK3399_GRF_SOC_CON20		0x6250
161 #define RK3399_DSI0_LCDC_SEL		BIT(0)
164 #define RK3399_GRF_SOC_CON22		0x6258
165 #define RK3399_DSI0_TURNREQUEST		(0xf << 12)
166 #define RK3399_DSI0_TURNDISABLE		(0xf << 8)
167 #define RK3399_DSI0_FORCETXSTOPMODE	(0xf << 4)
168 #define RK3399_DSI0_FORCERXMODE		(0xf << 0)
170 #define RK3399_GRF_SOC_CON23		0x625c
171 #define RK3399_DSI1_TURNDISABLE		(0xf << 12)
172 #define RK3399_DSI1_FORCETXSTOPMODE	(0xf << 8)
173 #define RK3399_DSI1_FORCERXMODE		(0xf << 4)
174 #define RK3399_DSI1_ENABLE		(0xf << 0)
176 #define RK3399_GRF_SOC_CON24		0x6260
181 #define RK3399_TXRX_TURNREQUEST		GENMASK(3, 0)
183 #define RK3568_GRF_VO_CON2		0x0368
184 #define RK3568_DSI0_SKEWCALHS		(0x1f << 11)
185 #define RK3568_DSI0_FORCETXSTOPMODE	(0xf << 4)
187 #define RK3568_DSI0_FORCERXMODE		BIT(0)
194 #define RK3568_GRF_VO_CON3		0x36c
195 #define RK3568_DSI1_SKEWCALHS		(0x1f << 11)
196 #define RK3568_DSI1_FORCETXSTOPMODE	(0xf << 4)
198 #define RK3568_DSI1_FORCERXMODE		BIT(0)
200 #define RV1126_GRF_DSIPHY_CON		0x10220
201 #define RV1126_DSI_FORCETXSTOPMODE	(0xf << 4)
203 #define RV1126_DSI_FORCERXMODE		BIT(0)
311 	{  89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
312 	{  99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
313 	{ 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
314 	{ 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
315 	{ 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
316 	{ 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
317 	{ 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
318 	{ 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
319 	{ 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
320 	{ 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
321 	{ 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
322 	{ 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
323 	{ 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
324 	{ 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
325 	{ 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
326 	{ 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
327 	{ 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
328 	{ 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
329 	{ 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
330 	{ 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
331 	{ 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
332 	{ 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
333 	{ 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
334 	{ 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
335 	{ 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
336 	{ 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
337 	{ 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
338 	{ 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
339 	{ 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
340 	{1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
341 	{1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
342 	{1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
343 	{1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
344 	{1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
345 	{1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
346 	{1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
347 	{1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
348 	{1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
349 	{1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }
356 	for (i = 0; i < ARRAY_SIZE(dppa_map); i++)  in max_mbps_to_parameter()
373 	 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content  in dw_mipi_dsi_phy_write()
379 	dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |  in dw_mipi_dsi_phy_write()
384 	dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |  in dw_mipi_dsi_phy_write()
412 		return 0;  in dw_mipi_dsi_phy_init()
426 	vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;  in dw_mipi_dsi_phy_init()
429 	if (i < 0) {  in dw_mipi_dsi_phy_init()
554 	unsigned long best_freq = 0;  in dw_mipi_dsi_get_lane_mbps()
563 	if (bpp < 0) {  in dw_mipi_dsi_get_lane_mbps()
589 		return 0;  in dw_mipi_dsi_get_lane_mbps()
644 	return 0;  in dw_mipi_dsi_get_lane_mbps()
712 	for (i = 0; i < ARRAY_SIZE(hstt_table); i++)  in dw_mipi_dsi_phy_get_timing()
721 	return 0;  in dw_mipi_dsi_phy_get_timing()
782 	return 0;  in dw_mipi_dsi_encoder_atomic_check()
792 	if (mux < 0)  in dw_mipi_dsi_encoder_enable()
836 	return 0;  in rockchip_dsi_drm_create_encoder()
847 	local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0);  in dw_mipi_dsi_rockchip_find_second()
859 		remote = of_graph_get_remote_node(node, 1, 0);  in dw_mipi_dsi_rockchip_find_second()
932 			return 0;  in dw_mipi_dsi_rockchip_bind()
980 						  dev->of_node, 0, 0);  in dw_mipi_dsi_rockchip_bind()
990 	return 0;  in dw_mipi_dsi_rockchip_bind()
1067 	return 0;  in dw_mipi_dsi_rockchip_host_attach()
1092 	return 0;  in dw_mipi_dsi_rockchip_host_detach()
1110 	return 0;  in dw_mipi_dsi_rockchip_dphy_bind()
1142 	if (ret < 0)  in dw_mipi_dsi_dphy_init()
1147 		if (ret < 0)  in dw_mipi_dsi_dphy_init()
1159 		if (ret < 0)  in dw_mipi_dsi_dphy_init()
1163 	return 0;  in dw_mipi_dsi_dphy_init()
1185 	return 0;  in dw_mipi_dsi_dphy_exit()
1201 	return 0;  in dw_mipi_dsi_dphy_configure()
1213 	if (i < 0) {  in dw_mipi_dsi_dphy_power_on()
1220 	if (ret < 0) {  in dw_mipi_dsi_dphy_power_on()
1246 		if (ret < 0) {  in dw_mipi_dsi_dphy_power_on()
1254 	 * Set clock lane and hsfreqrange by lane0(test code 0x44)  in dw_mipi_dsi_dphy_power_on()
1256 	dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0);  in dw_mipi_dsi_dphy_power_on()
1259 	dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0);  in dw_mipi_dsi_dphy_power_on()
1260 	dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0);  in dw_mipi_dsi_dphy_power_on()
1261 	dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0);  in dw_mipi_dsi_dphy_power_on()
1264 	dw_mipi_dsi_phy_write(dsi, 0x0, 0);  in dw_mipi_dsi_dphy_power_on()
1295 		if (ret < 0)  in dw_mipi_dsi_dphy_power_off()
1338 	return 0;  in dw_mipi_dsi_rockchip_resume()
1360 	dsi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in dw_mipi_dsi_rockchip_probe()
1366 	i = 0;  in dw_mipi_dsi_rockchip_probe()
1468 	return 0;  in dw_mipi_dsi_rockchip_probe()
1480 		.reg = 0xff450000,
1482 		.lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1487 		.lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1498 		.reg = 0xff960000,
1500 		.lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1506 		.reg = 0xff964000,
1508 		.lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1525 		     HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0));  in rk3399_dphy_tx1rx1_init()
1527 		     HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));  in rk3399_dphy_tx1rx1_init()
1529 		     HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR));  in rk3399_dphy_tx1rx1_init()
1531 		     HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));  in rk3399_dphy_tx1rx1_init()
1533 	return 0;  in rk3399_dphy_tx1rx1_init()
1545 		     HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));  in rk3399_dphy_tx1rx1_power_on()
1550 		     HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE));  in rk3399_dphy_tx1rx1_power_on()
1552 		     HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE));  in rk3399_dphy_tx1rx1_power_on()
1556 		     HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST));  in rk3399_dphy_tx1rx1_power_on()
1567 		     HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0),  in rk3399_dphy_tx1rx1_power_on()
1572 	return 0;  in rk3399_dphy_tx1rx1_power_on()
1580 		     HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));  in rk3399_dphy_tx1rx1_power_off()
1582 	return 0;  in rk3399_dphy_tx1rx1_power_off()
1587 		.reg = 0xff960000,
1589 		.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1594 		.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
1603 		.reg = 0xff968000,
1605 		.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
1610 		.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
1637 		.reg = 0xfe060000,
1639 		.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS |
1646 		.reg = 0xfe070000,
1648 		.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS |
1659 		.reg = 0xffb30000,
1661 		.lanecfg1 = HIWORD_UPDATE(0, RV1126_DSI_TURNDISABLE |