1 /* SPDX-License-Identifier: GPL-2.0 */
3  * R-Car Display Unit Registers Definitions
5  * Copyright (C) 2013-2015 Renesas Electronics Corporation
18 /* -----------------------------------------------------------------------------
31 #define DSYSR_TVM_MASK		(3 << 6)
34 #define DSYSR_SCM_INT_VIDEO	(3 << 4)
35 #define DSYSR_SCM_MASK		(3 << 4)
42 #define DSMR_DIPM_DE		(3 << 25)
43 #define DSMR_DIPM_MASK		(3 << 25)
52 #define DSMR_CDEM_HIGH		(3 << 13)
53 #define DSMR_CDEM_MASK		(3 << 13)
58 #define DSMR_CSY_222		(3 << 6)
59 #define DSMR_CSY_MASK		(3 << 6)
65 #define DSSR_VC1FB_INIT		(3 << 30)
66 #define DSSR_VC1FB_MASK		(3 << 30)
70 #define DSSR_VC0FB_INIT		(3 << 28)
71 #define DSSR_VC0FB_MASK		(3 << 28)
72 #define DSSR_DFB(n)		(1 << ((n)+15))  argument
78 #define DSSR_ADC(n)		(1 << ((n)-1))  argument
86 #define DSRCR_ADCL(n)		(1 << ((n)-1))  argument
95 #define DIER_ADCE(n)		(1 << ((n)-1))  argument
104 #define DPPR_DPE(n)		(1 << ((n)*4-1))  argument
105 #define DPPR_DPS(n, p)		(((p)-1) << DPPR_DPS_SHIFT(n))  argument
106 #define DPPR_DPS_SHIFT(n)	(((n)-1)*4)  argument
143 #define DEFR3_EVDM_3		(3 << 12)
154 #define DVCSR_VCnFB2_DSA0(n)	(0 << ((n)*2+16))  argument
155 #define DVCSR_VCnFB2_DSA1(n)	(1 << ((n)*2+16))  argument
156 #define DVCSR_VCnFB2_DSA2(n)	(2 << ((n)*2+16))  argument
157 #define DVCSR_VCnFB2_INIT(n)	(3 << ((n)*2+16))  argument
158 #define DVCSR_VCnFB2_MASK(n)	(3 << ((n)*2+16))  argument
159 #define DVCSR_VCnFB_DSA0(n)	(0 << ((n)*2))  argument
160 #define DVCSR_VCnFB_DSA1(n)	(1 << ((n)*2))  argument
161 #define DVCSR_VCnFB_DSA2(n)	(2 << ((n)*2))  argument
162 #define DVCSR_VCnFB_INIT(n)	(3 << ((n)*2))  argument
163 #define DVCSR_VCnFB_MASK(n)	(3 << ((n)*2))  argument
170 #define DEFR5_YCRGB2_PRI3	(3 << 14)
171 #define DEFR5_YCRGB2_MASK	(3 << 14)
175 #define DEFR5_YCRGB1_PRI3	(3 << 12)
176 #define DEFR5_YCRGB1_MASK	(3 << 12)
189 #define DEFR6_ODPM12_CDE	(3 << 10)
190 #define DEFR6_ODPM12_MASK	(3 << 10)
193 #define DEFR6_ODPM02_CDE	(3 << 8)
194 #define DEFR6_ODPM02_MASK	(3 << 8)
205 /* -----------------------------------------------------------------------------
206  * R8A7790-only Control Registers
216 #define DD1SSR_ADC(n)		(1 << ((n)-1))  argument
225 #define DD1SRCR_ADC(n)		(1 << ((n)-1))  argument
234 #define DD1IER_ADC(n)		(1 << ((n)-1))  argument
239 #define DEFR8_DRGBS_DU(n)	((n) << 4)  argument
240 #define DEFR8_DRGBS_MASK	(3 << 4)
253 #define DOFLR_ODDFL0		(1 << 3)
260 #define DIDSR_LDCS_DCLKIN(n)	(0 << (8 + (n) * 2))  argument
261 #define DIDSR_LDCS_DSI(n)	(2 << (8 + (n) * 2))	/* V3U only */  argument
262 #define DIDSR_LDCS_LVDS0(n)	(2 << (8 + (n) * 2))  argument
263 #define DIDSR_LDCS_LVDS1(n)	(3 << (8 + (n) * 2))  argument
264 #define DIDSR_LDCS_MASK(n)	(3 << (8 + (n) * 2))  argument
265 #define DIDSR_PDCS_CLK(n, clk)	(clk << ((n) * 2))  argument
266 #define DIDSR_PDCS_MASK(n)	(3 << ((n) * 2))  argument
288 #define DPLLCR_FDPLL(n)		((n) << 12)  argument
289 #define DPLLCR_N(n)		((n) << 5)  argument
290 #define DPLLCR_M(n)		((n) << 3)  argument
298 #define DPLLC2R_M(n)		((n) << 8)  argument
299 #define DPLLC2R_FDPLL(n)	((n) << 0)  argument
301 /* -----------------------------------------------------------------------------
320 /* -----------------------------------------------------------------------------
344 /* -----------------------------------------------------------------------------
354 #define PnMR_VISL_VIN3		(3 << 26)	/* use Video Input 3 */
365 #define PnMR_CPSL_CP3		(2 << 8)	/* Color Palette selected 3 */
366 #define PnMR_CPSL_CP4		(3 << 8)	/* Color Palette selected 4 */
371 #define PnMR_BM_VC		(3 << 4)	/* Video Capture Mode */
375 #define PnMR_DDDF_YC		(3 << 0)	/* YC */
376 #define PnMR_DDDF_MASK		(3 << 0)
411 #define PnSWAPR_SPQW		(1 << 3)
437 #define PnDDCR4_EDF_RGB666	(3 << 0)
467 /* -----------------------------------------------------------------------------
476 /* -----------------------------------------------------------------------------
489 /* -----------------------------------------------------------------------------
502 #define ESCR_SYNCSEL_EXHSYNC	(3 << 8)
508 /* -----------------------------------------------------------------------------
518 #define DORCR_PG1D_DOOR		(3 << 24)
519 #define DORCR_PG1D_MASK		(3 << 24)
524 #define DORCR_PG0D_DOOR		(3 << 16)
525 #define DORCR_PG0D_MASK		(3 << 16)
530 #define DPTSR_PnDK(n)		(1 << ((n) + 16))  argument
531 #define DPTSR_PnTS(n)		(1 << (n))  argument
534 #define DAPTSR_APnDK(n)		(1 << ((n) + 16))  argument
535 #define DAPTSR_APnTS(n)		(1 << (n))  argument
540 /* -----------------------------------------------------------------------------
541  * YC-RGB Conversion Coefficient Registers