1 // SPDX-License-Identifier: GPL-2.0+
3  * R-Car Display Unit Channels Pair
5  * Copyright (C) 2013-2015 Renesas Electronics Corporation
11  * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
12  * unit, timings generator, ...) and device-global resources (start/stop
18  * related to input and output routing). For this reason the R8A7790 DU must be
19  * modeled as a single device with three CRTCs, two sets of "semi-global"
20  * resources, and a few device-global resources.
23  * counterpart in the DU documentation, that models those semi-global resources.
35 	return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);  in rcar_du_group_read()
40 	rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);  in rcar_du_group_write()
47 	if (rgrp->channels_mask & BIT(0))  in rcar_du_group_setup_pins()
50 	if (rgrp->channels_mask & BIT(1))  in rcar_du_group_setup_pins()
58 	struct rcar_du_device *rcdu = rgrp->dev;  in rcar_du_group_setup_defr8()
61 	if (rcdu->info->gen < 3) {  in rcar_du_group_setup_defr8()
69 		if (rgrp->index == 0) {  in rcar_du_group_setup_defr8()
70 			defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);  in rcar_du_group_setup_defr8()
71 			if (rgrp->dev->vspd1_sink == 2)  in rcar_du_group_setup_defr8()
80 		if (rgrp->index == rcdu->dpad0_source / 2)  in rcar_du_group_setup_defr8()
81 			defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);  in rcar_du_group_setup_defr8()
89 	struct rcar_du_device *rcdu = rgrp->dev;  in rcar_du_group_setup_didsr()
103 	if (rcdu->info->gen < 3 && rgrp->index == 0) {  in rcar_du_group_setup_didsr()
108 		rcrtc = rcdu->crtcs;  in rcar_du_group_setup_didsr()
109 		num_crtcs = rcdu->num_crtcs;  in rcar_du_group_setup_didsr()
110 	} else if (rcdu->info->gen >= 3 && rgrp->num_crtcs > 1) {  in rcar_du_group_setup_didsr()
112 		 * On Gen3 dot clocks are setup through per-group registers,  in rcar_du_group_setup_didsr()
115 		rcrtc = &rcdu->crtcs[rgrp->index * 2];  in rcar_du_group_setup_didsr()
116 		num_crtcs = rgrp->num_crtcs;  in rcar_du_group_setup_didsr()
124 		if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index))  in rcar_du_group_setup_didsr()
127 		else if (rcdu->info->dsi_clk_mask & BIT(rcrtc->index))  in rcar_du_group_setup_didsr()
139 	struct rcar_du_device *rcdu = rgrp->dev;  in rcar_du_group_setup()
145 	if (rcdu->info->gen < 3) {  in rcar_du_group_setup()
152 	if (rcdu->info->gen < 4)  in rcar_du_group_setup()
155 	if (rcdu->info->gen < 4) {  in rcar_du_group_setup()
161 		defr7 |= (rgrp->cmms_mask & BIT(1) ? DEFR7_CMME1 : 0) |  in rcar_du_group_setup()
162 			 (rgrp->cmms_mask & BIT(0) ? DEFR7_CMME0 : 0);  in rcar_du_group_setup()
166 	if (rcdu->info->gen >= 2) {  in rcar_du_group_setup()
167 		if (rcdu->info->gen < 4)  in rcar_du_group_setup()
172 	if (rcdu->info->gen >= 3)  in rcar_du_group_setup()
184 	if (rcdu->info->gen >= 3 && rgrp->num_crtcs == 1)  in rcar_du_group_setup()
189 	mutex_lock(&rgrp->lock);  in rcar_du_group_setup()
190 	rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) |  in rcar_du_group_setup()
191 			    rgrp->dptsr_planes);  in rcar_du_group_setup()
192 	mutex_unlock(&rgrp->lock);  in rcar_du_group_setup()
196  * rcar_du_group_get - Acquire a reference to the DU channels group
207 	if (rgrp->use_count)  in rcar_du_group_get()
213 	rgrp->use_count++;  in rcar_du_group_get()
218  * rcar_du_group_put - Release a reference to the DU
224 	--rgrp->use_count;  in rcar_du_group_put()
229 	struct rcar_du_device *rcdu = rgrp->dev;  in __rcar_du_group_start_stop()
236 	 * M3-N, however, DU2 doesn't exist, but DSYSR2 does. We thus need to  in __rcar_du_group_start_stop()
239 	if (rcdu->info->channels_mask & BIT(rgrp->index * 2)) {  in __rcar_du_group_start_stop()
240 		struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2];  in __rcar_du_group_start_stop()
253 	 * Many of the configuration bits are only updated when the display  in rcar_du_group_start_stop()
255 	 * of those bits could be pre-configured, but others (especially the  in rcar_du_group_start_stop()
256 	 * bits related to plane assignment to display timing controllers) need  in rcar_du_group_start_stop()
259 	 * Restart the display controller if a start is requested. Sorry for the  in rcar_du_group_start_stop()
260 	 * flicker. It should be possible to move most of the "DRES-update" bits  in rcar_du_group_start_stop()
262 	 * when the display controller will have to be restarted.  in rcar_du_group_start_stop()
265 		if (rgrp->used_crtcs++ != 0)  in rcar_du_group_start_stop()
269 		if (--rgrp->used_crtcs == 0)  in rcar_du_group_start_stop()
276 	rgrp->need_restart = false;  in rcar_du_group_restart()
289 	if (rcdu->info->gen < 2)  in rcar_du_set_dpad0_vsp1_routing()
299 	index = rcdu->info->gen < 3 ? 0 : DIV_ROUND_UP(rcdu->num_crtcs, 2) - 1;  in rcar_du_set_dpad0_vsp1_routing()
300 	rgrp = &rcdu->groups[index];  in rcar_du_set_dpad0_vsp1_routing()
301 	crtc = &rcdu->crtcs[index * 2];  in rcar_du_set_dpad0_vsp1_routing()
303 	ret = clk_prepare_enable(crtc->clock);  in rcar_du_set_dpad0_vsp1_routing()
309 	clk_disable_unprepare(crtc->clock);  in rcar_du_set_dpad0_vsp1_routing()
324 	struct rcar_du_device *rcdu = rgrp->dev;  in rcar_du_group_set_dpad_levels()
328 	if (rcdu->info->gen < 2)  in rcar_du_group_set_dpad_levels()
335 	 * by driving fixed low-level signals at the output of any DU channel  in rcar_du_group_set_dpad_levels()
341 	for (i = 0; i < rgrp->num_crtcs; ++i) {  in rcar_du_group_set_dpad_levels()
345 		rcrtc = &rcdu->crtcs[rgrp->index * 2 + i];  in rcar_du_group_set_dpad_levels()
346 		rstate = to_rcar_crtc_state(rcrtc->crtc.state);  in rcar_du_group_set_dpad_levels()
348 		if (!(rstate->outputs & dpad_mask))  in rcar_du_group_set_dpad_levels()
357 	struct rcar_du_device *rcdu = rgrp->dev;  in rcar_du_group_set_routing()
367 	if (rcdu->dpad1_source == rgrp->index * 2)  in rcar_du_group_set_routing()
376 	return rcar_du_set_dpad0_vsp1_routing(rgrp->dev);  in rcar_du_group_set_routing()