drm/radeon/radeon.h

32  *	- surface allocator & initializer : (bit like scratch reg) should
35  *	- WB : write back stuff (do it bit like scratch reg things)
36  *	- Vblank : look at Jesse's rework and what we should do
37  *	- r600/r700: gart & cp
38  *	- cs : clean cs ioctl use bitmap & things like that.
39  *	- power management stuff
40  *	- Barrier in gart code
41  *	- Unmappabled vram ?
42  *	- TESTING, TESTING, TESTING
70 #include <linux/dma-fence.h>
265  * Clocks
368 	/* sync_seq is protected by ring emission lock */
417 	BUG_ON(a->ring != b->ring);  in radeon_fence_later()
419 	if (a->seq > b->seq) {  in radeon_fence_later()
437 	BUG_ON(a->ring != b->ring);  in radeon_fence_is_earlier()
439 	return a->seq < b->seq;  in radeon_fence_is_earlier()
470 	/* protected by bo being reserved */
476 	/* protected by vm mutex */
486 	/* Protected by gem.mutex */
488 	/* Protected by tbo.reserved */
596 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
677 #define RADEON_MAX_DOORBELLS 1024	/* Reserve at most 1024 doorbell slots for radeon-owned rings. */
845 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
1052 	struct radeon_cs_chunk *ibc = p->chunk_ib;  in radeon_get_ib_value()
1054 	if (ibc->kdata)  in radeon_get_ib_value()
1055 		return ibc->kdata[idx];  in radeon_get_ib_value()
1056 	return p->ib.ptr[idx];  in radeon_get_ib_value()
1148  * struct radeon_pm - power management datas
1335 	/* UVD clocks */
1338 	/* VCE clocks */
1522 	/* vce clocks */
1525 	/* gpu clocks */
1633 	/* profile-based power management */
1791 	return -ENODEV;  in radeon_mn_register()
2462 	if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)  in r100_mm_rreg()
2463 		return readl(((void __iomem *)rdev->rmmio) + reg);  in r100_mm_rreg()
2470 	if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)  in r100_mm_wreg()
2471 		writel(v, ((void __iomem *)rdev->rmmio) + reg);  in r100_mm_wreg()
2491 	if (__f->base.ops == &radeon_fence_ops)  in to_radeon_fence()
2500 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2501 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2502 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2503 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2512 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2513 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2514 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2515 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2518 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2519 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2595 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2596 			    (rdev->pdev->device == 0x5969))
2597 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2598 		(rdev->family == CHIP_RV200) || \
2599 		(rdev->family == CHIP_RS100) || \
2600 		(rdev->family == CHIP_RS200) || \
2601 		(rdev->family == CHIP_RV250) || \
2602 		(rdev->family == CHIP_RV280) || \
2603 		(rdev->family == CHIP_RS300))
2604 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||	\
2605 		(rdev->family == CHIP_RV350) ||			\
2606 		(rdev->family == CHIP_R350)  ||			\
2607 		(rdev->family == CHIP_RV380) ||			\
2608 		(rdev->family == CHIP_R420)  ||			\
2609 		(rdev->family == CHIP_R423)  ||			\
2610 		(rdev->family == CHIP_RV410) ||			\
2611 		(rdev->family == CHIP_RS400) ||			\
2612 		(rdev->family == CHIP_RS480))
2613 #define ASIC_IS_X2(rdev) ((rdev->pdev->device == 0x9441) || \
2614 		(rdev->pdev->device == 0x9443) || \
2615 		(rdev->pdev->device == 0x944B) || \
2616 		(rdev->pdev->device == 0x9506) || \
2617 		(rdev->pdev->device == 0x9509) || \
2618 		(rdev->pdev->device == 0x950F) || \
2619 		(rdev->pdev->device == 0x689C) || \
2620 		(rdev->pdev->device == 0x689D))
2621 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2622 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||	\
2623 			    (rdev->family == CHIP_RS690)  ||	\
2624 			    (rdev->family == CHIP_RS740)  ||	\
2625 			    (rdev->family >= CHIP_R600))
2626 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2627 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2628 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2629 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2630 			     (rdev->flags & RADEON_IS_IGP))
2631 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2632 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2633 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2634 			     (rdev->flags & RADEON_IS_IGP))
2635 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2636 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2637 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2638 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2639 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2640 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2641 			     (rdev->family == CHIP_MULLINS))
2643 #define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) || \
2644 			      (rdev->pdev->device == 0x6850) || \
2645 			      (rdev->pdev->device == 0x6858) || \
2646 			      (rdev->pdev->device == 0x6859) || \
2647 			      (rdev->pdev->device == 0x6840) || \
2648 			      (rdev->pdev->device == 0x6841) || \
2649 			      (rdev->pdev->device == 0x6842) || \
2650 			      (rdev->pdev->device == 0x6843))
2655 #define RBIOS8(i) (rdev->bios[i])
2670  * radeon_ring_write - write a value to the ring
2679 	if (ring->count_dw <= 0)  in radeon_ring_write()
2682 	ring->ring[ring->wptr++] = v;  in radeon_ring_write()
2683 	ring->wptr &= ring->ptr_mask;  in radeon_ring_write()
2684 	ring->count_dw--;  in radeon_ring_write()
2685 	ring->ring_free_dw--;  in radeon_ring_write()
2691 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2692 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2693 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2694 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2695 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2696 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2697 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
2698 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2699 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2700 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2701 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2702 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2703 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (i…
2704 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_…
2705 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page…
2706 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2707 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2708 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2709 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2710 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2711 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2712 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2713 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev)…
2714 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2715 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2716 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2717 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2718 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2719 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crt…
2720 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2721 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2722 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2723 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2724 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2725 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit…
2726 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (res…
2727 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2728 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2729 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2730 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2731 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2732 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2733 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2734 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2735 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2736 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2737 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2738 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2739 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2740 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2741 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2742 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f)…
2743 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2744 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2745 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2746 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2747 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2748 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2749 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2750 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2751 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2752 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2753 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2754 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2755 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (ba…
2756 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2757 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2758 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2759 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2760 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2761 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev)…
2762 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2763 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2764 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2765 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2766 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2767 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2768 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2769 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2770 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_change…
2771 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2772 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2773 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2774 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2775 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_c…
2776 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev),…
2777 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2778 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2779 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2780 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2781 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))