Lines Matching full:pi
174 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi() local
176 return pi; in ci_get_pi()
188 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_powertune_defaults() local
198 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
204 pi->powertune_defaults = &defaults_saturn_xt; in ci_initialize_powertune_defaults()
208 pi->powertune_defaults = &defaults_hawaii_xt; in ci_initialize_powertune_defaults()
212 pi->powertune_defaults = &defaults_hawaii_pro; in ci_initialize_powertune_defaults()
222 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
226 pi->dte_tj_offset = 0; in ci_initialize_powertune_defaults()
228 pi->caps_power_containment = true; in ci_initialize_powertune_defaults()
229 pi->caps_cac = false; in ci_initialize_powertune_defaults()
230 pi->caps_sq_ramping = false; in ci_initialize_powertune_defaults()
231 pi->caps_db_ramping = false; in ci_initialize_powertune_defaults()
232 pi->caps_td_ramping = false; in ci_initialize_powertune_defaults()
233 pi->caps_tcp_ramping = false; in ci_initialize_powertune_defaults()
235 if (pi->caps_power_containment) { in ci_initialize_powertune_defaults()
236 pi->caps_cac = true; in ci_initialize_powertune_defaults()
238 pi->enable_bapm_feature = false; in ci_initialize_powertune_defaults()
240 pi->enable_bapm_feature = true; in ci_initialize_powertune_defaults()
241 pi->enable_tdc_limit_feature = true; in ci_initialize_powertune_defaults()
242 pi->enable_pkg_pwr_tracking_feature = true; in ci_initialize_powertune_defaults()
253 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_vid_sidd() local
254 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_populate_bapm_vddc_vid_sidd()
255 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_populate_bapm_vddc_vid_sidd()
256 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; in ci_populate_bapm_vddc_vid_sidd()
282 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_vddc_vid() local
283 u8 *vid = pi->smc_powertune_table.VddCVid; in ci_populate_vddc_vid()
286 if (pi->vddc_voltage_table.count > 8) in ci_populate_vddc_vid()
289 for (i = 0; i < pi->vddc_voltage_table.count; i++) in ci_populate_vddc_vid()
290 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); in ci_populate_vddc_vid()
297 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_svi_load_line() local
298 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_svi_load_line()
300 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; in ci_populate_svi_load_line()
301 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; in ci_populate_svi_load_line()
302 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; in ci_populate_svi_load_line()
303 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; in ci_populate_svi_load_line()
310 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_tdc_limit() local
311 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_tdc_limit()
315 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); in ci_populate_tdc_limit()
316 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = in ci_populate_tdc_limit()
318 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; in ci_populate_tdc_limit()
325 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_dw8() local
326 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_dw8()
333 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, in ci_populate_dw8()
334 pi->sram_end); in ci_populate_dw8()
338 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; in ci_populate_dw8()
345 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_fuzzy_fan() local
352 pi->smc_powertune_table.FuzzyFan_PwmSetDelta = in ci_populate_fuzzy_fan()
360 struct ci_power_info *pi = ci_get_pi(rdev); in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc() local
361 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
362 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
384 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
385 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
392 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_base_leakage_sidd() local
400 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
401 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
408 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_parameters_in_dpm_table() local
409 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_bapm_parameters_in_dpm_table()
410 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table()
421 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
423 (u8)(pi->thermal_temp_setting.temperature_high / 1000); in ci_populate_bapm_parameters_in_dpm_table()
456 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_pm_base() local
460 if (pi->caps_power_containment) { in ci_populate_pm_base()
464 &pm_fuse_table_offset, pi->sram_end); in ci_populate_pm_base()
492 (u8 *)&pi->smc_powertune_table, in ci_populate_pm_base()
493 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); in ci_populate_pm_base()
503 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_enable_didt() local
506 if (pi->caps_sq_ramping) { in ci_do_enable_didt()
515 if (pi->caps_db_ramping) { in ci_do_enable_didt()
524 if (pi->caps_td_ramping) { in ci_do_enable_didt()
533 if (pi->caps_tcp_ramping) { in ci_do_enable_didt()
593 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_didt() local
596 if (pi->caps_sq_ramping || pi->caps_db_ramping || in ci_enable_didt()
597 pi->caps_td_ramping || pi->caps_tcp_ramping) { in ci_enable_didt()
618 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_power_containment() local
623 pi->power_containment_features = 0; in ci_enable_power_containment()
624 if (pi->caps_power_containment) { in ci_enable_power_containment()
625 if (pi->enable_bapm_feature) { in ci_enable_power_containment()
630 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; in ci_enable_power_containment()
633 if (pi->enable_tdc_limit_feature) { in ci_enable_power_containment()
638 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; in ci_enable_power_containment()
641 if (pi->enable_pkg_pwr_tracking_feature) { in ci_enable_power_containment()
651 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; in ci_enable_power_containment()
658 if (pi->caps_power_containment && pi->power_containment_features) { in ci_enable_power_containment()
659 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) in ci_enable_power_containment()
662 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) in ci_enable_power_containment()
665 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) in ci_enable_power_containment()
667 pi->power_containment_features = 0; in ci_enable_power_containment()
676 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_smc_cac() local
680 if (pi->caps_cac) { in ci_enable_smc_cac()
685 pi->cac_enabled = false; in ci_enable_smc_cac()
687 pi->cac_enabled = true; in ci_enable_smc_cac()
689 } else if (pi->cac_enabled) { in ci_enable_smc_cac()
691 pi->cac_enabled = false; in ci_enable_smc_cac()
701 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_thermal_based_sclk_dpm() local
704 if (pi->thermal_sclk_dpm_enabled) { in ci_enable_thermal_based_sclk_dpm()
719 struct ci_power_info *pi = ci_get_pi(rdev); in ci_power_control_set_level() local
727 if (pi->caps_power_containment) { in ci_power_control_set_level()
741 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_powergate_uvd() local
743 if (pi->uvd_power_gated == gate) in ci_dpm_powergate_uvd()
746 pi->uvd_power_gated = gate; in ci_dpm_powergate_uvd()
753 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_vblank_too_short() local
755 u32 switch_limit = pi->mem_gddr5 ? 450 : 300; in ci_dpm_vblank_too_short()
774 struct ci_power_info *pi = ci_get_pi(rdev); in ci_apply_state_adjust_rules() local
795 pi->battery_state = true; in ci_apply_state_adjust_rules()
797 pi->battery_state = false; in ci_apply_state_adjust_rules()
912 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_static_mode() local
915 if (pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_static_mode()
917 pi->fan_ctrl_default_mode = tmp; in ci_fan_ctrl_set_static_mode()
919 pi->t_min = tmp; in ci_fan_ctrl_set_static_mode()
920 pi->fan_ctrl_is_in_default_mode = false; in ci_fan_ctrl_set_static_mode()
934 struct ci_power_info *pi = ci_get_pi(rdev); in ci_thermal_setup_fan_table() local
943 if (!pi->fan_table_start) { in ci_thermal_setup_fan_table()
996 pi->fan_table_start, in ci_thermal_setup_fan_table()
999 pi->sram_end); in ci_thermal_setup_fan_table()
1011 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_start_smc_fan_control() local
1014 if (pi->caps_od_fuzzy_fan_control_support) { in ci_fan_ctrl_start_smc_fan_control()
1033 pi->fan_is_controlled_by_smc = true; in ci_fan_ctrl_start_smc_fan_control()
1040 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_stop_smc_fan_control() local
1044 pi->fan_is_controlled_by_smc = false; in ci_fan_ctrl_stop_smc_fan_control()
1081 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_fan_speed_percent() local
1086 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_set_fan_speed_percent()
1126 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_get_mode() local
1129 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_get_mode()
1190 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_default_mode() local
1193 if (!pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_default_mode()
1195 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode); in ci_fan_ctrl_set_default_mode()
1199 tmp |= TMIN(pi->t_min); in ci_fan_ctrl_set_default_mode()
1201 pi->fan_ctrl_is_in_default_mode = true; in ci_fan_ctrl_set_default_mode()
1259 struct ci_power_info *pi = ci_get_pi(rdev);
1262 pi->soft_regs_start + reg_offset,
1263 value, pi->sram_end);
1270 struct ci_power_info *pi = ci_get_pi(rdev); in ci_write_smc_soft_register() local
1273 pi->soft_regs_start + reg_offset, in ci_write_smc_soft_register()
1274 value, pi->sram_end); in ci_write_smc_soft_register()
1279 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_fps_limits() local
1280 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits()
1282 if (pi->caps_fps) { in ci_init_fps_limits()
1295 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_sclk_t() local
1299 if (pi->caps_sclk_throttle_low_notification) { in ci_update_sclk_t()
1300 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in ci_update_sclk_t()
1303 pi->dpm_table_start + in ci_update_sclk_t()
1306 sizeof(u32), pi->sram_end); in ci_update_sclk_t()
1315 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_leakage_voltages() local
1320 pi->vddc_leakage.count = 0; in ci_get_leakage_voltages()
1321 pi->vddci_leakage.count = 0; in ci_get_leakage_voltages()
1329 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1330 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1331 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1341 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1342 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1343 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1346 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; in ci_get_leakage_voltages()
1347 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1348 pi->vddci_leakage.count++; in ci_get_leakage_voltages()
1357 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_dpm_event_sources() local
1380 if (pi->thermal_protection) in ci_set_dpm_event_sources()
1396 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_auto_throttle_source() local
1399 if (!(pi->active_auto_throttle_sources & (1 << source))) { in ci_enable_auto_throttle_source()
1400 pi->active_auto_throttle_sources |= 1 << source; in ci_enable_auto_throttle_source()
1401 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1404 if (pi->active_auto_throttle_sources & (1 << source)) { in ci_enable_auto_throttle_source()
1405 pi->active_auto_throttle_sources &= ~(1 << source); in ci_enable_auto_throttle_source()
1406 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1419 struct ci_power_info *pi = ci_get_pi(rdev); in ci_unfreeze_sclk_mclk_dpm() local
1422 if (!pi->need_update_smu7_dpm_table) in ci_unfreeze_sclk_mclk_dpm()
1425 if ((!pi->sclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1426 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_unfreeze_sclk_mclk_dpm()
1432 if ((!pi->mclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1433 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_unfreeze_sclk_mclk_dpm()
1439 pi->need_update_smu7_dpm_table = 0; in ci_unfreeze_sclk_mclk_dpm()
1445 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_sclk_mclk_dpm() local
1449 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1455 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1473 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1479 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1491 struct ci_power_info *pi = ci_get_pi(rdev); in ci_start_dpm() local
1516 if (!pi->pcie_dpm_key_disabled) { in ci_start_dpm()
1527 struct ci_power_info *pi = ci_get_pi(rdev); in ci_freeze_sclk_mclk_dpm() local
1530 if (!pi->need_update_smu7_dpm_table) in ci_freeze_sclk_mclk_dpm()
1533 if ((!pi->sclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1534 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_freeze_sclk_mclk_dpm()
1540 if ((!pi->mclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1541 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_freeze_sclk_mclk_dpm()
1552 struct ci_power_info *pi = ci_get_pi(rdev); in ci_stop_dpm() local
1565 if (!pi->pcie_dpm_key_disabled) { in ci_stop_dpm()
1597 struct ci_power_info *pi = ci_get_pi(rdev);
1609 if (pi->caps_automatic_dc_transition) {
1663 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_sclk() local
1665 if (!pi->sclk_dpm_key_disabled) { in ci_dpm_force_state_sclk()
1677 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_mclk() local
1679 if (!pi->mclk_dpm_key_disabled) { in ci_dpm_force_state_mclk()
1691 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_pcie() local
1693 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_state_pcie()
1705 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_power_limit() local
1707 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { in ci_set_power_limit()
1781 struct ci_power_info *pi = ci_get_pi(rdev); in ci_process_firmware_header() local
1788 &tmp, pi->sram_end); in ci_process_firmware_header()
1792 pi->dpm_table_start = tmp; in ci_process_firmware_header()
1797 &tmp, pi->sram_end); in ci_process_firmware_header()
1801 pi->soft_regs_start = tmp; in ci_process_firmware_header()
1806 &tmp, pi->sram_end); in ci_process_firmware_header()
1810 pi->mc_reg_table_start = tmp; in ci_process_firmware_header()
1815 &tmp, pi->sram_end); in ci_process_firmware_header()
1819 pi->fan_table_start = tmp; in ci_process_firmware_header()
1824 &tmp, pi->sram_end); in ci_process_firmware_header()
1828 pi->arb_table_start = tmp; in ci_process_firmware_header()
1835 struct ci_power_info *pi = ci_get_pi(rdev); in ci_read_clock_registers() local
1837 pi->clock_registers.cg_spll_func_cntl = in ci_read_clock_registers()
1839 pi->clock_registers.cg_spll_func_cntl_2 = in ci_read_clock_registers()
1841 pi->clock_registers.cg_spll_func_cntl_3 = in ci_read_clock_registers()
1843 pi->clock_registers.cg_spll_func_cntl_4 = in ci_read_clock_registers()
1845 pi->clock_registers.cg_spll_spread_spectrum = in ci_read_clock_registers()
1847 pi->clock_registers.cg_spll_spread_spectrum_2 = in ci_read_clock_registers()
1849 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); in ci_read_clock_registers()
1850 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in ci_read_clock_registers()
1851 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); in ci_read_clock_registers()
1852 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
1853 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); in ci_read_clock_registers()
1854 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in ci_read_clock_registers()
1855 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); in ci_read_clock_registers()
1856 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in ci_read_clock_registers()
1857 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); in ci_read_clock_registers()
1862 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_sclk_t() local
1864 pi->low_sclk_interrupt_t = 0; in ci_init_sclk_t()
1928 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ds_master_switch() local
1931 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
1939 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
1984 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_spread_spectrum() local
1988 if (pi->caps_sclk_ss_support) { in ci_enable_spread_spectrum()
2058 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_firmware() local
2070 return ci_load_smc_ucode(rdev, pi->sram_end); in ci_upload_firmware()
2097 struct ci_power_info *pi = ci_get_pi(rdev); in ci_construct_voltage_tables() local
2100 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2103 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2106 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2109 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2114 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) in ci_construct_voltage_tables()
2116 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2118 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2121 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2124 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2127 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2132 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) in ci_construct_voltage_tables()
2134 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2136 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2139 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2142 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2145 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2150 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) in ci_construct_voltage_tables()
2152 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2182 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddc_table() local
2185 table->VddcLevelCount = pi->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
2188 &pi->vddc_voltage_table.entries[count], in ci_populate_smc_vddc_table()
2191 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddc_table()
2193 pi->vddc_voltage_table.entries[count].smio_low; in ci_populate_smc_vddc_table()
2206 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddci_table() local
2208 table->VddciLevelCount = pi->vddci_voltage_table.count; in ci_populate_smc_vddci_table()
2211 &pi->vddci_voltage_table.entries[count], in ci_populate_smc_vddci_table()
2214 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddci_table()
2216 pi->vddci_voltage_table.entries[count].smio_low; in ci_populate_smc_vddci_table()
2228 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_mvdd_table() local
2231 table->MvddLevelCount = pi->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
2234 &pi->mvdd_voltage_table.entries[count], in ci_populate_smc_mvdd_table()
2237 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_mvdd_table()
2239 pi->mvdd_voltage_table.entries[count].smio_low; in ci_populate_smc_mvdd_table()
2271 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mvdd_value() local
2274 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_mvdd_value()
2277 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; in ci_populate_mvdd_value()
2376 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_arb_table_index() local
2380 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2381 &tmp, pi->sram_end); in ci_init_arb_table_index()
2388 return ci_write_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2389 tmp, pi->sram_end); in ci_init_arb_table_index()
2509 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_program_memory_timing_parameters() local
2516 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2517 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2519 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2520 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2529 pi->arb_table_start, in ci_do_program_memory_timing_parameters()
2532 pi->sram_end); in ci_do_program_memory_timing_parameters()
2539 struct ci_power_info *pi = ci_get_pi(rdev); in ci_program_memory_timing_parameters() local
2541 if (pi->need_update_smu7_dpm_table == 0) in ci_program_memory_timing_parameters()
2551 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_initial_state() local
2557 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()
2565 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()
2590 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_link_level() local
2591 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_smc_link_level()
2604 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
2605 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()
2755 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_mclk_params() local
2756 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_calculate_mclk_params()
2757 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_calculate_mclk_params()
2758 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; in ci_calculate_mclk_params()
2759 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; in ci_calculate_mclk_params()
2760 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; in ci_calculate_mclk_params()
2761 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; in ci_calculate_mclk_params()
2762 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; in ci_calculate_mclk_params()
2763 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; in ci_calculate_mclk_params()
2764 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; in ci_calculate_mclk_params()
2782 if (pi->mem_gddr5) { in ci_calculate_mclk_params()
2788 if (pi->caps_mclk_ss_support) { in ci_calculate_mclk_params()
2840 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_memory_level() local
2870 if (pi->vddc_phase_shed_control) in ci_populate_single_memory_level()
2880 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; in ci_populate_single_memory_level()
2890 if (pi->mclk_stutter_mode_threshold && in ci_populate_single_memory_level()
2891 (memory_clock <= pi->mclk_stutter_mode_threshold) && in ci_populate_single_memory_level()
2892 (pi->uvd_enabled == false) && in ci_populate_single_memory_level()
2897 if (pi->mclk_strobe_mode_threshold && in ci_populate_single_memory_level()
2898 (memory_clock <= pi->mclk_strobe_mode_threshold)) in ci_populate_single_memory_level()
2901 if (pi->mem_gddr5) { in ci_populate_single_memory_level()
2904 if (pi->mclk_edc_enable_threshold && in ci_populate_single_memory_level()
2905 (memory_clock > pi->mclk_edc_enable_threshold)) in ci_populate_single_memory_level()
2908 if (pi->mclk_edc_wr_enable_threshold && in ci_populate_single_memory_level()
2909 (memory_clock > pi->mclk_edc_wr_enable_threshold)) in ci_populate_single_memory_level()
2919 dll_state_on = pi->dll_default_on; in ci_populate_single_memory_level()
2953 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_acpi_level() local
2956 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; in ci_populate_smc_acpi_level()
2957 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; in ci_populate_smc_acpi_level()
2958 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_populate_smc_acpi_level()
2959 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_populate_smc_acpi_level()
2964 if (pi->acpi_vddc) in ci_populate_smc_acpi_level()
2965 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2967 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2969 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
2991 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_populate_smc_acpi_level()
2992 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_populate_smc_acpi_level()
2993 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_populate_smc_acpi_level()
2994 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_populate_smc_acpi_level()
3013 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_smc_acpi_level()
3014 if (pi->acpi_vddci) in ci_populate_smc_acpi_level()
3016 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3019 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3036 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); in ci_populate_smc_acpi_level()
3038 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); in ci_populate_smc_acpi_level()
3040 cpu_to_be32(pi->clock_registers.mpll_func_cntl); in ci_populate_smc_acpi_level()
3042 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); in ci_populate_smc_acpi_level()
3044 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); in ci_populate_smc_acpi_level()
3045 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); in ci_populate_smc_acpi_level()
3046 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); in ci_populate_smc_acpi_level()
3054 cpu_to_be16((u16)pi->mclk_activity_target); in ci_populate_smc_acpi_level()
3068 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ulv() local
3069 struct ci_ulv_parm *ulv = &pi->ulv; in ci_enable_ulv()
3086 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_ulv_level() local
3093 pi->ulv.supported = false; in ci_populate_ulv_level()
3097 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_populate_ulv_level()
3111 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_ulv_level()
3124 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_sclk_params() local
3126 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_calculate_sclk_params()
3127 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_calculate_sclk_params()
3128 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_calculate_sclk_params()
3129 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_calculate_sclk_params()
3148 if (pi->caps_sclk_ss_support) { in ci_calculate_sclk_params()
3181 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_graphic_level() local
3199 if (pi->vddc_phase_shed_control) in ci_populate_single_graphic_level()
3215 if (pi->caps_sclk_ds) in ci_populate_single_graphic_level()
3239 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_graphic_levels() local
3240 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_graphic_levels()
3241 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_graphic_levels()
3245 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3253 (u16)pi->activity_target[i], in ci_populate_all_graphic_levels()
3254 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3258 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3260 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3263 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
3265 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3266 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()
3271 pi->sram_end); in ci_populate_all_graphic_levels()
3286 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_memory_levels() local
3287 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_memory_levels()
3288 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_memory_levels()
3292 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
3302 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3307 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
3311 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3312 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3313 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()
3314 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3317 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3319 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3320 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()
3323 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3328 pi->sram_end); in ci_populate_all_memory_levels()
3356 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_pcie_tables() local
3358 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) in ci_setup_default_pcie_tables()
3361 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3362 pi->pcie_gen_powersaving = pi->pcie_gen_performance; in ci_setup_default_pcie_tables()
3363 pi->pcie_lane_powersaving = pi->pcie_lane_performance; in ci_setup_default_pcie_tables()
3364 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3365 pi->pcie_gen_performance = pi->pcie_gen_powersaving; in ci_setup_default_pcie_tables()
3366 pi->pcie_lane_performance = pi->pcie_lane_powersaving; in ci_setup_default_pcie_tables()
3370 &pi->dpm_table.pcie_speed_table, in ci_setup_default_pcie_tables()
3374 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3375 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3376 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3378 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3379 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3380 pi->pcie_lane_powersaving.min); in ci_setup_default_pcie_tables()
3381 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, in ci_setup_default_pcie_tables()
3382 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3383 pi->pcie_lane_performance.min); in ci_setup_default_pcie_tables()
3384 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, in ci_setup_default_pcie_tables()
3385 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3386 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3387 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, in ci_setup_default_pcie_tables()
3388 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3389 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3390 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, in ci_setup_default_pcie_tables()
3391 pi->pcie_gen_powersaving.max, in ci_setup_default_pcie_tables()
3392 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3393 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, in ci_setup_default_pcie_tables()
3394 pi->pcie_gen_performance.max, in ci_setup_default_pcie_tables()
3395 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3397 pi->dpm_table.pcie_speed_table.count = 6; in ci_setup_default_pcie_tables()
3404 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_dpm_tables() local
3422 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); in ci_setup_default_dpm_tables()
3425 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3428 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
3431 &pi->dpm_table.vddc_table, in ci_setup_default_dpm_tables()
3434 &pi->dpm_table.vddci_table, in ci_setup_default_dpm_tables()
3437 &pi->dpm_table.mvdd_table, in ci_setup_default_dpm_tables()
3440 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3443 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
3445 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = in ci_setup_default_dpm_tables()
3447 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = in ci_setup_default_dpm_tables()
3449 pi->dpm_table.sclk_table.count++; in ci_setup_default_dpm_tables()
3453 pi->dpm_table.mclk_table.count = 0; in ci_setup_default_dpm_tables()
3456 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != in ci_setup_default_dpm_tables()
3458 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = in ci_setup_default_dpm_tables()
3460 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = in ci_setup_default_dpm_tables()
3462 pi->dpm_table.mclk_table.count++; in ci_setup_default_dpm_tables()
3467 pi->dpm_table.vddc_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3469 pi->dpm_table.vddc_table.dpm_levels[i].param1 = in ci_setup_default_dpm_tables()
3471 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3473 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()
3478 pi->dpm_table.vddci_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3480 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3482 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3488 pi->dpm_table.mvdd_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3490 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3492 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3518 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_smc_table() local
3519 struct ci_ulv_parm *ulv = &pi->ulv; in ci_init_smc_table()
3521 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table()
3528 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) in ci_init_smc_table()
3539 if (pi->mem_gddr5) in ci_init_smc_table()
3543 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); in ci_init_smc_table()
3590 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, in ci_init_smc_table()
3591 pi->vbios_boot_state.sclk_bootup_value, in ci_init_smc_table()
3592 (u32 *)&pi->smc_state_table.GraphicsBootLevel); in ci_init_smc_table()
3594 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, in ci_init_smc_table()
3595 pi->vbios_boot_state.mclk_bootup_value, in ci_init_smc_table()
3596 (u32 *)&pi->smc_state_table.MemoryBootLevel); in ci_init_smc_table()
3598 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; in ci_init_smc_table()
3599 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; in ci_init_smc_table()
3600 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; in ci_init_smc_table()
3617 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * in ci_init_smc_table()
3619 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * in ci_init_smc_table()
3627 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3629 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) in ci_init_smc_table()
3653 pi->dpm_table_start + in ci_init_smc_table()
3657 pi->sram_end); in ci_init_smc_table()
3683 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_pcie_dpm_states() local
3684 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; in ci_trim_pcie_dpm_states()
3714 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_dpm_states() local
3726 &pi->dpm_table.sclk_table, in ci_trim_dpm_states()
3731 &pi->dpm_table.mclk_table, in ci_trim_dpm_states()
3778 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_dpm_level_enable_mask() local
3783 if (!pi->sclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3784 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3787 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3793 if (!pi->mclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3794 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3797 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3803 if (!pi->pcie_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3804 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3807 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3819 struct ci_power_info *pi = ci_get_pi(rdev); in ci_find_dpm_states_clocks_in_dpm_table() local
3821 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3823 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3827 pi->need_update_smu7_dpm_table = 0; in ci_find_dpm_states_clocks_in_dpm_table()
3835 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3842 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3851 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3855 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3861 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_and_upload_sclk_mclk_dpm_levels() local
3865 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3868 if (!pi->need_update_smu7_dpm_table) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3871 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3874 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3877 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3883 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3894 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_uvd_dpm() local
3904 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()
3908 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; in ci_enable_uvd_dpm()
3910 if (!pi->caps_uvd_dpm) in ci_enable_uvd_dpm()
3917 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); in ci_enable_uvd_dpm()
3919 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3920 pi->uvd_enabled = true; in ci_enable_uvd_dpm()
3921 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_enable_uvd_dpm()
3924 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3927 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3928 pi->uvd_enabled = false; in ci_enable_uvd_dpm()
3929 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; in ci_enable_uvd_dpm()
3932 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3943 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_vce_dpm() local
3953 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; in ci_enable_vce_dpm()
3956 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; in ci_enable_vce_dpm()
3958 if (!pi->caps_vce_dpm) in ci_enable_vce_dpm()
3965 pi->dpm_level_enable_mask.vce_dpm_enable_mask); in ci_enable_vce_dpm()
3976 struct ci_power_info *pi = ci_get_pi(rdev);
3986 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3989 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3991 if (!pi->caps_samu_dpm)
3998 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4007 struct ci_power_info *pi = ci_get_pi(rdev);
4017 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4020 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4022 if (!pi->caps_acp_dpm)
4029 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4040 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_uvd_dpm() local
4044 if (pi->caps_uvd_dpm || in ci_update_uvd_dpm()
4046 pi->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_dpm()
4048 pi->smc_state_table.UvdBootLevel = in ci_update_uvd_dpm()
4053 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); in ci_update_uvd_dpm()
4079 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_vce_dpm() local
4088 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); in ci_update_vce_dpm()
4091 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); in ci_update_vce_dpm()
4113 struct ci_power_info *pi = ci_get_pi(rdev);
4117 pi->smc_state_table.AcpBootLevel = 0;
4121 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4132 struct ci_power_info *pi = ci_get_pi(rdev); in ci_generate_dpm_level_enable_mask() local
4139 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4140 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); in ci_generate_dpm_level_enable_mask()
4141 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4142 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); in ci_generate_dpm_level_enable_mask()
4143 pi->last_mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4144 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_generate_dpm_level_enable_mask()
4145 if (pi->uvd_enabled) { in ci_generate_dpm_level_enable_mask()
4146 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) in ci_generate_dpm_level_enable_mask()
4147 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_generate_dpm_level_enable_mask()
4149 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4150 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); in ci_generate_dpm_level_enable_mask()
4170 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_performance_level() local
4175 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4176 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4178 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; in ci_dpm_force_performance_level()
4194 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4195 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4197 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4213 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4214 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4216 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4233 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4234 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4236 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4248 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4249 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4251 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4263 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4264 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4266 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_dpm_force_performance_level()
4279 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_performance_level()
4300 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_mc_special_registers() local
4326 if (!pi->mem_gddr5) in ci_set_mc_special_registers()
4333 if (!pi->mem_gddr5) { in ci_set_mc_special_registers()
4587 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_mc_reg_table() local
4589 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; in ci_initialize_mc_reg_table()
4647 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mc_reg_addresses() local
4650 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { in ci_populate_mc_reg_addresses()
4651 if (pi->mc_reg_table.valid_flag & (1 << j)) { in ci_populate_mc_reg_addresses()
4654 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); in ci_populate_mc_reg_addresses()
4655 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); in ci_populate_mc_reg_addresses()
4683 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_entry_to_smc() local
4686 for(i = 0; i < pi->mc_reg_table.num_entries; i++) { in ci_convert_mc_reg_table_entry_to_smc()
4687 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in ci_convert_mc_reg_table_entry_to_smc()
4691 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) in ci_convert_mc_reg_table_entry_to_smc()
4694 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], in ci_convert_mc_reg_table_entry_to_smc()
4695 mc_reg_table_data, pi->mc_reg_table.last, in ci_convert_mc_reg_table_entry_to_smc()
4696 pi->mc_reg_table.valid_flag); in ci_convert_mc_reg_table_entry_to_smc()
4702 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_to_smc() local
4705 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) in ci_convert_mc_reg_table_to_smc()
4707 pi->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
4713 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_initial_mc_reg_table() local
4716 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_populate_initial_mc_reg_table()
4718 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4721 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4724 pi->mc_reg_table_start, in ci_populate_initial_mc_reg_table()
4725 (u8 *)&pi->smc_mc_reg_table, in ci_populate_initial_mc_reg_table()
4727 pi->sram_end); in ci_populate_initial_mc_reg_table()
4732 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_and_upload_mc_reg_table() local
4734 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
4737 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_update_and_upload_mc_reg_table()
4739 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_update_and_upload_mc_reg_table()
4742 pi->mc_reg_table_start + in ci_update_and_upload_mc_reg_table()
4744 (u8 *)&pi->smc_mc_reg_table.data[0], in ci_update_and_upload_mc_reg_table()
4746 pi->dpm_table.mclk_table.count, in ci_update_and_upload_mc_reg_table()
4747 pi->sram_end); in ci_update_and_upload_mc_reg_table()
4814 struct ci_power_info *pi = ci_get_pi(rdev); in ci_request_link_speed_change_before_state_change() local
4819 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) in ci_request_link_speed_change_before_state_change()
4822 current_link_speed = pi->force_pcie_gen; in ci_request_link_speed_change_before_state_change()
4824 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_request_link_speed_change_before_state_change()
4825 pi->pspp_notify_required = false; in ci_request_link_speed_change_before_state_change()
4832 pi->force_pcie_gen = RADEON_PCIE_GEN2; in ci_request_link_speed_change_before_state_change()
4842 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); in ci_request_link_speed_change_before_state_change()
4847 pi->pspp_notify_required = true; in ci_request_link_speed_change_before_state_change()
4855 struct ci_power_info *pi = ci_get_pi(rdev); in ci_notify_link_speed_change_after_state_change() local
4860 if (pi->pspp_notify_required) { in ci_notify_link_speed_change_after_state_change()
4880 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_private_data_variables_based_on_pptable() local
4901 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4902 pi->max_vddc_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4905 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4906 pi->max_vddci_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4923 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddc_leakage() local
4924 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; in ci_patch_with_vddc_leakage()
4937 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddci_leakage() local
4938 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; in ci_patch_with_vddci_leakage()
5056 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_memory_type() local
5063 pi->mem_gddr5 = true; in ci_get_memory_type()
5065 pi->mem_gddr5 = false; in ci_get_memory_type()
5073 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_current_ps() local
5075 pi->current_rps = *rps; in ci_update_current_ps()
5076 pi->current_ps = *new_ps; in ci_update_current_ps()
5077 pi->current_rps.ps_priv = &pi->current_ps; in ci_update_current_ps()
5084 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_requested_ps() local
5086 pi->requested_rps = *rps; in ci_update_requested_ps()
5087 pi->requested_ps = *new_ps; in ci_update_requested_ps()
5088 pi->requested_rps.ps_priv = &pi->requested_ps; in ci_update_requested_ps()
5093 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_pre_set_power_state() local
5099 ci_apply_state_adjust_rules(rdev, &pi->requested_rps); in ci_dpm_pre_set_power_state()
5106 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_post_set_power_state() local
5107 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_post_set_power_state()
5128 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_enable() local
5134 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_dpm_enable()
5142 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5145 pi->caps_dynamic_ac_timing = false; in ci_dpm_enable()
5147 if (pi->dynamic_ss) in ci_dpm_enable()
5149 if (pi->thermal_protection) in ci_dpm_enable()
5179 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5283 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_disable() local
5293 if (pi->thermal_protection) in ci_dpm_disable()
5314 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_set_power_state() local
5315 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_set_power_state()
5316 struct radeon_ps *old_ps = &pi->current_rps; in ci_dpm_set_power_state()
5320 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5349 if (pi->caps_dynamic_ac_timing) { in ci_dpm_set_power_state()
5371 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5439 struct ci_power_info *pi = ci_get_pi(rdev); in ci_parse_pplib_clock_info() local
5451 pi->sys_pcie_mask, in ci_parse_pplib_clock_info()
5452 pi->vbios_boot_state.pcie_gen_bootup_value, in ci_parse_pplib_clock_info()
5455 pi->vbios_boot_state.pcie_lane_bootup_value, in ci_parse_pplib_clock_info()
5459 pi->acpi_pcie_gen = pl->pcie_gen; in ci_parse_pplib_clock_info()
5463 pi->ulv.supported = true; in ci_parse_pplib_clock_info()
5464 pi->ulv.pl = *pl; in ci_parse_pplib_clock_info()
5465 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; in ci_parse_pplib_clock_info()
5470 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; in ci_parse_pplib_clock_info()
5471 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; in ci_parse_pplib_clock_info()
5472 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; in ci_parse_pplib_clock_info()
5473 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; in ci_parse_pplib_clock_info()
5478 pi->use_pcie_powersaving_levels = true; in ci_parse_pplib_clock_info()
5479 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5480 pi->pcie_gen_powersaving.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5481 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5482 pi->pcie_gen_powersaving.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5483 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5484 pi->pcie_lane_powersaving.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5485 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5486 pi->pcie_lane_powersaving.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5489 pi->use_pcie_performance_levels = true; in ci_parse_pplib_clock_info()
5490 if (pi->pcie_gen_performance.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5491 pi->pcie_gen_performance.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5492 if (pi->pcie_gen_performance.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5493 pi->pcie_gen_performance.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5494 if (pi->pcie_lane_performance.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5495 pi->pcie_lane_performance.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5496 if (pi->pcie_lane_performance.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5497 pi->pcie_lane_performance.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5653 struct ci_power_info *pi; in ci_dpm_init() local
5658 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); in ci_dpm_init()
5659 if (pi == NULL) in ci_dpm_init()
5661 rdev->pm.dpm.priv = pi; in ci_dpm_init()
5666 pi->sys_pcie_mask = 0; in ci_dpm_init()
5669 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | in ci_dpm_init()
5673 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | in ci_dpm_init()
5676 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; in ci_dpm_init()
5678 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_dpm_init()
5680 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5681 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5682 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5683 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5685 pi->pcie_lane_performance.max = 0; in ci_dpm_init()
5686 pi->pcie_lane_performance.min = 16; in ci_dpm_init()
5687 pi->pcie_lane_powersaving.max = 0; in ci_dpm_init()
5688 pi->pcie_lane_powersaving.min = 16; in ci_dpm_init()
5690 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); in ci_dpm_init()
5715 pi->dll_default_on = false; in ci_dpm_init()
5716 pi->sram_end = SMC_RAM_END; in ci_dpm_init()
5718 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5719 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5720 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5721 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5722 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5723 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5724 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5725 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5727 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; in ci_dpm_init()
5729 pi->sclk_dpm_key_disabled = 0; in ci_dpm_init()
5730 pi->mclk_dpm_key_disabled = 0; in ci_dpm_init()
5731 pi->pcie_dpm_key_disabled = 0; in ci_dpm_init()
5732 pi->thermal_sclk_dpm_enabled = 0; in ci_dpm_init()
5737 pi->mclk_dpm_key_disabled = 1; in ci_dpm_init()
5740 pi->caps_sclk_ds = true; in ci_dpm_init()
5742 pi->mclk_strobe_mode_threshold = 40000; in ci_dpm_init()
5743 pi->mclk_stutter_mode_threshold = 40000; in ci_dpm_init()
5744 pi->mclk_edc_enable_threshold = 40000; in ci_dpm_init()
5745 pi->mclk_edc_wr_enable_threshold = 40000; in ci_dpm_init()
5749 pi->caps_fps = false; in ci_dpm_init()
5751 pi->caps_sclk_throttle_low_notification = false; in ci_dpm_init()
5753 pi->caps_uvd_dpm = true; in ci_dpm_init()
5754 pi->caps_vce_dpm = true; in ci_dpm_init()
5788 pi->thermal_temp_setting.temperature_low = 94500; in ci_dpm_init()
5789 pi->thermal_temp_setting.temperature_high = 95000; in ci_dpm_init()
5790 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5792 pi->thermal_temp_setting.temperature_low = 99500; in ci_dpm_init()
5793 pi->thermal_temp_setting.temperature_high = 100000; in ci_dpm_init()
5794 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5797 pi->uvd_enabled = false; in ci_dpm_init()
5799 dpm_table = &pi->smc_state_table; in ci_dpm_init()
5848 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5849 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5850 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5852 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5854 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5858 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5860 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5867 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5869 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5874 pi->vddc_phase_shed_control = true; in ci_dpm_init()
5877 pi->pcie_performance_request = in ci_dpm_init()
5880 pi->pcie_performance_request = false; in ci_dpm_init()
5885 pi->caps_sclk_ss_support = true; in ci_dpm_init()
5886 pi->caps_mclk_ss_support = true; in ci_dpm_init()
5887 pi->dynamic_ss = true; in ci_dpm_init()
5889 pi->caps_sclk_ss_support = false; in ci_dpm_init()
5890 pi->caps_mclk_ss_support = false; in ci_dpm_init()
5891 pi->dynamic_ss = true; in ci_dpm_init()
5895 pi->thermal_protection = true; in ci_dpm_init()
5897 pi->thermal_protection = false; in ci_dpm_init()
5899 pi->caps_dynamic_ac_timing = true; in ci_dpm_init()
5901 pi->uvd_power_gated = false; in ci_dpm_init()
5909 pi->fan_ctrl_is_in_default_mode = true; in ci_dpm_init()
5917 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_debugfs_print_current_performance_level() local
5918 struct radeon_ps *rps = &pi->current_rps; in ci_dpm_debugfs_print_current_performance_level()
5922 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); in ci_dpm_debugfs_print_current_performance_level()
5962 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_sclk() local
5963 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_sclk()
5973 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_mclk() local
5974 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_mclk()