Lines Matching +full:post +full:- +full:pwm +full:- +full:on +full:- +full:delay +full:- +full:ms
2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
175 #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
422 UCHAR ucPostDiv; //return post div to be written to register
483 …ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register d…
487 …ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register d…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
526 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
679 // 1: setup and turn on encoder
702 // =1: turn on encoder
815 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
868 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
921 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
971 // =1: turn on encoder
1173 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1174 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1178 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1179 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1276 UCHAR ucLaneNum; // indicate lane number 1-8
1548 UCHAR ucPostDiv; // post divider
1568 UCHAR ucPostDiv; // post divider
1615 UCHAR ucPostDiv; // post divider
1626 …// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the sour…
1643 UCHAR ucPostDiv; // post divider.
1654 // =1: other external clock source, which is pre-defined
1655 // by VBIOS depend on the feature required.
1691 UCHAR ucPostDiv; // post divider.
1702 …// =1: other external clock source, which is pre-defined …
1703 // by VBIOS depend on the feature required.
1783 …UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other …
1784 …UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other …
1830 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
1923 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devi…
1938 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1939 // Bit[1]: 1-Ext. 0-Int.
1963 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1964 // Bit[1]: 1-Ext. 0-Int.
2023 // 1: setup and turn on encoder
2041 // 1: setup and turn on encoder
2149 // bit1=0: non-coherent mode
2333 // 1: setup and turn on encoder
2380 …SIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2416 …UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and vid…
2418 …UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on produ…
2567 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2604 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2642 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2681 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2779 /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
2781 … For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
2795 … Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one …
2796 … Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one …
2798 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value…
2799 …OfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If th…
2801 … Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one…
2802 … Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one …
2805 …ulator dependent PWM value. The value makes the voltage >=Min NB voltage but <=InterNBVoltageHigh.…
2806 …gulator dependent PWM value. The value makes the voltage >=InterNBVoltageLow but <=Max NB voltage.…
2857 … // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
2862 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
2863 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2864 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
2867 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
2868 … or user customized mode. In this case, driver will just stick to this boot-up mode. No other Pow…
2869 =0: system boots up at driver control state. Power state depends on PowerPlay table.
2870 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
2873 Bit[4]=1: CLMC is supported and enabled on current system.
2874 …=0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change …
2881 Bit[8]=1: CDLF is supported and enabled on current system.
2882 =0: CDLF is not supported or enabled on current system.
2883 Bit[9]=1: DLL Shut Down feature is enabled on current system.
2884 =0: DLL Shut Down feature is not enabled or supported on current system.
2886 …ord is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEV…
2888 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
2889 …[7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are suppor…
2891 ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connec…
2892 …[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lan…
2893 …[7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station…
2894 …When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or dockin…
2896 … connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on …
2898 [15:8] - Lane configuration attribute;
2899 [23:16]- Connector type, possible value:
2905 [31:24]- Reserved
2913 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offs…
2919 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
2921 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
2922 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
2924 …PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE…
2927 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
2955 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
3153 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3154 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3155 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3156 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3157 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3158 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3159 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3160 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3161 // Bit 8 = 0 - no CV support= 1- CV is supported
3162 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3163 // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported
3164 // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported
3172 // [7:0] - I2C LINE Associate ID
3173 // = 0 - no I2C
3174 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3176 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3178 // = 3-7 Reserved for future I2C engines
3179 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3284 // usModeMiscInfo-
3296 //usRefreshRate-
3463 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming …
3467 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set…
3478 // 0 0 0 - Color bit depth is undefined
3479 // 0 0 1 - 6 Bits per Primary Color
3480 // 0 1 0 - 8 Bits per Primary Color
3481 // 0 1 1 - 10 Bits per Primary Color
3482 // 1 0 0 - 12 Bits per Primary Color
3483 // 1 0 1 - 14 Bits per Primary Color
3484 // 1 1 0 - 16 Bits per Primary Color
3485 // 1 1 1 - Reserved
3520 … // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own
3523 // Bit7-3: Reserved
3525 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13
3561 // 0 0 0 - Color bit depth is undefined
3562 // 0 0 1 - 6 Bits per Primary Color
3563 // 0 1 0 - 8 Bits per Primary Color
3564 // 0 1 1 - 10 Bits per Primary Color
3565 // 1 0 0 - 12 Bits per Primary Color
3566 // 1 0 1 - 14 Bits per Primary Color
3567 // 1 1 0 - 16 Bits per Primary Color
3568 // 1 1 1 - Reserved
3572 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming …
3576 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set…
3585 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
3586 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip with…
3741 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
3754 …(ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
3812 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)…
3835 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
3839 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
3841 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
3885 //ucGPIO_ID pre-define id for multiple usage
3967 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
3984 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4068 //Two definitions below are for OPM on MXM module designs
4288 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4341 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4347 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4480 …UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /Vo…
4573 #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_V…
4574 …I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OB…
4575 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GP…
4576 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SV…
4578 …OST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4579 …AKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4580 …AKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4615 UCHAR ucPhaseDelay; // phase delay in unit of micro second
4864 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
4889 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
4890 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
4891 … VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
4892 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
4895 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
4897 … VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
4898 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
4903 Threshold on value to enter HTC_active state.
4905 …calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHys…
4906 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on W…
4909 Bit[1]=0: DDR-DLL shut-down feature disabled.
4910 1: DDR-DLL shut-down feature enabled.
4911 Bit[2]=0: DDR-PLL Power down feature disabled.
4912 … 1: DDR-PLL Power down feature enabled.
4914 usNBP0Voltage: VID for voltage on NB P0 State
4915 usNBP1Voltage: VID for voltage on NB P1 State
4931 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
4932 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5079 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5113 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5114 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5115 … VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
5116 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5119 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5121 … VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
5122 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5127 Threshold on value to enter HTC_active state.
5129 …calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHys…
5130 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on W…
5133 Bit[1]=0: DDR-DLL shut-down feature disabled.
5134 1: DDR-DLL shut-down feature enabled.
5135 Bit[2]=0: DDR-PLL Power down feature disabled.
5136 … 1: DDR-PLL Power down feature enabled.
5138 usNBP0Voltage: VID for voltage on NB P0 State
5139 usNBP1Voltage: VID for voltage on NB P1 State
5140 usNBP2Voltage: VID for voltage on NB P2 State
5141 usNBP3Voltage: VID for voltage on NB P3 State
5157 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
5158 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5178 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON…
5179 …=0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->…
5181 ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( …
5182 …0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON-…
5185 ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from dat…
5186 …=0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following:…
5189 ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from var…
5190 … mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON-…
5193 ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIG…
5194 =0 means to use VBIOS default delay which is 125 ( 500ms ).
5198 …LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal activ…
5199 =0 means to use VBIOS default delay which is 0 ( 0ms ).
5203 …LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal of…
5204 =0 means to use VBIOS default delay which is 0 ( 0ms ).
5207 ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specifi…
5280 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5283 sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4…
5314 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5315 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5316 … VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
5317 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5320 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5322 … VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
5323 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5327 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to en…
5329 …calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHys…
5333 Bit[1]=0: DDR-DLL shut-down feature disabled.
5334 1: DDR-DLL shut-down feature enabled.
5335 Bit[2]=0: DDR-PLL Power down feature disabled.
5336 1: DDR-PLL Power down feature enabled.
5357 … NCLK speed while memory runs in self-refresh state, used to calculate self-re…
5370 …ngine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV onl…
5384 …LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable sig…
5385 …=0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->…
5388 …LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brig…
5389 …0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON-…
5392 …LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCD…
5393 …=0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following:…
5396 …LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_…
5397 … mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON-…
5400 …LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal act…
5401 =0 means to use VBIOS default delay which is 125 ( 500ms ).
5404 …LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal activ…
5405 =0 means to use VBIOS default delay which is 0 ( 0ms ).
5409 …LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal of…
5410 =0 means to use VBIOS default delay which is 0 ( 0ms ).
5412 ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specifi…
5416 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
5417 ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State
5418 usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
5419 usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded
5433 // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a…
5480 //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a cloc…
5981 …char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<cha…
5983 …ADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevisio…
5984 …DER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevisi…
5988 …SION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevisio…
5989 …ION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevisi…
6008 UCHAR ucPostDiv; //Post div
6369 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
6407 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
6408 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
6416 …ULONG ulFlags; // To enable/disable functionalities based on memory ty…
6425 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
6434 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
6435 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
6557 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
6565 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms
6582 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
6583 …UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calcula…
6584 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6603 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6605 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6607 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6608 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
6610 …UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used …
6613 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6626 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6645 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6647 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6649 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6650 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
6652 …UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used …
6655 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6662 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6664 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6676 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6678 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6680 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6681 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
6683 …UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used …
6686 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6693 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6695 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6714 …AR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_R…
6716 …Size; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6723 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6725 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6941 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
6942 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
6996 #define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON.
7000 #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON …
7255 UCHAR ucReturnCode; // Output: Return value base on action was taken
7299 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
7300 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
7301 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
7308 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
7309 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
7310 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
7450 // [7:4] - connector type
7451 // = 1 - VGA connector
7452 // = 2 - DVI-I
7453 // = 3 - DVI-D
7454 // = 4 - DVI-A
7455 // = 5 - SVIDEO
7456 // = 6 - COMPOSITE
7457 // = 7 - LVDS
7458 // = 8 - DIGITAL LINK
7459 // = 9 - SCART
7460 // = 0xA - HDMI_type A
7461 // = 0xB - HDMI_type B
7462 // = 0xE - Special case1 (DVI+DIN)
7464 // [3:0] - DAC Associated
7465 // = 0 - no DAC
7466 // = 1 - DACA
7467 // = 2 - DACB
7468 // = 3 - External DAC
7533 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
7597 …ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control exte…
7608 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off
7643 …SCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-…
7653 …ETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-Hi…
7663 …O2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver …