Lines Matching defs:_ATOM_INTEGRATED_SYSTEM_INFO
2747 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO struct
2749 ATOM_COMMON_TABLE_HEADER sHeader;
2750 ULONG ulBootUpEngineClock; //in 10kHz unit
2751 ULONG ulBootUpMemoryClock; //in 10kHz unit
2752 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
2753 ULONG ulMinSystemMemoryClock; //in 10kHz unit
2754 UCHAR ucNumberOfCyclesInPeriodHi;
2755 … ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
2756 USHORT usReserved1;
2757 … usInterNBVoltageLow; //An intermidiate PMW value to set the voltage
2758 … usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage
2759 ULONG ulReserved[2];
2761 USHORT usFSBClock; //In MHz unit
2762 …ityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
2765 … usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
2766 USHORT usK8MemoryClock; //in MHz unit
2767 USHORT usK8SyncStartDelay; //in 0.01 us unit
2768 USHORT usK8DataReturnTime; //in 0.01 us unit
2769 UCHAR ucMaxNBVoltage;
2770 UCHAR ucMinNBVoltage;
2771 … ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
2772 … ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
2773 … ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
2774 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
2775 UCHAR ucMaxNBVoltageHigh;
2776 UCHAR ucMinNBVoltageHigh;