31 #include <nvrm/535.113.01/nvidia/generated/g_rpc-structures.h>
38 	ioread32_native(bar->flushBAR2);  in r535_bar_flush()
49 	rpc_update_bar_pde_v15_00 *rpc;  in r535_bar_bar2_update_pde()  local
51 	rpc = nvkm_gsp_rpc_get(gsp, NV_VGPU_MSG_FUNCTION_UPDATE_BAR_PDE, sizeof(*rpc));  in r535_bar_bar2_update_pde()
52 	if (WARN_ON(IS_ERR_OR_NULL(rpc)))  in r535_bar_bar2_update_pde()
53 		return -EIO;  in r535_bar_bar2_update_pde()
55 	rpc->info.barType = NV_RPC_UPDATE_PDE_BAR_2;  in r535_bar_bar2_update_pde()
56 	rpc->info.entryValue = addr ? ((addr >> 4) | 2) : 0; /* PD3 entry format! */  in r535_bar_bar2_update_pde()
57 	rpc->info.entryLevelShift = 47; //XXX: probably fetch this from mmu!  in r535_bar_bar2_update_pde()
59 	return nvkm_gsp_rpc_wr(gsp, rpc, true);  in r535_bar_bar2_update_pde()
65 	struct nvkm_gsp *gsp = bar->subdev.device->gsp;  in r535_bar_bar2_fini()
67 	bar->flushBAR2 = bar->flushBAR2PhysMode;  in r535_bar_bar2_fini()
68 	nvkm_done(bar->flushFBZero);  in r535_bar_bar2_fini()
76 	struct nvkm_device *device = bar->subdev.device;  in r535_bar_bar2_init()
77 	struct nvkm_vmm *vmm = gf100_bar(bar)->bar[0].vmm;  in r535_bar_bar2_init()
78 	struct nvkm_gsp *gsp = device->gsp;  in r535_bar_bar2_init()
80 	WARN_ON(r535_bar_bar2_update_pde(gsp, vmm->pd->pde[0]->pt[0]->addr));  in r535_bar_bar2_init()
81 	vmm->rm.bar2_pdb = gsp->bar.rm_bar2_pdb;  in r535_bar_bar2_init()
83 	if (!bar->flushFBZero) {  in r535_bar_bar2_init()
88 		if (ret == 0) {  in r535_bar_bar2_init()
89 			ret = nvkm_memory_kmap(fbZero, &bar->flushFBZero);  in r535_bar_bar2_init()
95 	bar->bar2 = true;  in r535_bar_bar2_init()
96 	bar->flushBAR2 = nvkm_kmap(bar->flushFBZero);  in r535_bar_bar2_init()
97 	WARN_ON(!bar->flushBAR2);  in r535_bar_bar2_init()
113 	struct nvkm_device *device = bar->subdev.device;  in r535_bar_bar1_init()
114 	struct nvkm_gsp *gsp = device->gsp;  in r535_bar_bar1_init()
115 	struct nvkm_vmm *vmm = gf100_bar(bar)->bar[1].vmm;  in r535_bar_bar1_init()
119 	ret = nvkm_ram_wrap(device, gsp->bar.rm_bar1_pdb, 0x1000, &pd3);  in r535_bar_bar1_init()
120 	if (WARN_ON(ret))  in r535_bar_bar1_init()
123 	nvkm_memory_unref(&vmm->pd->pt[0]->memory);  in r535_bar_bar1_init()
125 	ret = nvkm_memory_kmap(pd3, &vmm->pd->pt[0]->memory);  in r535_bar_bar1_init()
127 	if (WARN_ON(ret))  in r535_bar_bar1_init()
130 	vmm->pd->pt[0]->addr = nvkm_memory_addr(vmm->pd->pt[0]->memory);  in r535_bar_bar1_init()
138 	nvkm_memory_unref(&bar->flushFBZero);  in r535_bar_dtor()
140 	if (bar->flushBAR2PhysMode)  in r535_bar_dtor()
141 		iounmap(bar->flushBAR2PhysMode);  in r535_bar_dtor()
143 	kfree(bar->func);  in r535_bar_dtor()
155 	if (!(rm = kzalloc(sizeof(*rm), GFP_KERNEL)))  in r535_bar_new_()
156 		return -ENOMEM;  in r535_bar_new_()
158 	rm->dtor = r535_bar_dtor;  in r535_bar_new_()
159 	rm->oneinit = hw->oneinit;  in r535_bar_new_()
160 	rm->bar1.init = r535_bar_bar1_init;  in r535_bar_new_()
161 	rm->bar1.fini = r535_bar_bar1_fini;  in r535_bar_new_()
162 	rm->bar1.wait = r535_bar_bar1_wait;  in r535_bar_new_()
163 	rm->bar1.vmm = hw->bar1.vmm;  in r535_bar_new_()
164 	rm->bar2.init = r535_bar_bar2_init;  in r535_bar_new_()
165 	rm->bar2.fini = r535_bar_bar2_fini;  in r535_bar_new_()
166 	rm->bar2.wait = r535_bar_bar2_wait;  in r535_bar_new_()
167 	rm->bar2.vmm = hw->bar2.vmm;  in r535_bar_new_()
168 	rm->flush = r535_bar_flush;  in r535_bar_new_()
171 	if (ret) {  in r535_bar_new_()
177 	bar->flushBAR2PhysMode = ioremap(device->func->resource_addr(device, 3), PAGE_SIZE);  in r535_bar_new_()
178 	if (!bar->flushBAR2PhysMode)  in r535_bar_new_()
179 		return -ENOMEM;  in r535_bar_new_()
181 	bar->flushBAR2 = bar->flushBAR2PhysMode;  in r535_bar_new_()
183 	gf100_bar(*pbar)->bar2_halve = true;  in r535_bar_new_()