Lines Matching +full:vdd +full:- +full:s
27 #include <asm/dma-iommu.h>
35 if (tdev->vdd) { in nvkm_device_tegra_power_up()
36 ret = regulator_enable(tdev->vdd); in nvkm_device_tegra_power_up()
41 ret = clk_prepare_enable(tdev->clk); in nvkm_device_tegra_power_up()
44 ret = clk_prepare_enable(tdev->clk_ref); in nvkm_device_tegra_power_up()
47 ret = clk_prepare_enable(tdev->clk_pwr); in nvkm_device_tegra_power_up()
50 clk_set_rate(tdev->clk_pwr, 204000000); in nvkm_device_tegra_power_up()
53 if (!tdev->pdev->dev.pm_domain) { in nvkm_device_tegra_power_up()
54 reset_control_assert(tdev->rst); in nvkm_device_tegra_power_up()
62 reset_control_deassert(tdev->rst); in nvkm_device_tegra_power_up()
69 clk_disable_unprepare(tdev->clk_pwr); in nvkm_device_tegra_power_up()
71 clk_disable_unprepare(tdev->clk_ref); in nvkm_device_tegra_power_up()
73 clk_disable_unprepare(tdev->clk); in nvkm_device_tegra_power_up()
75 if (tdev->vdd) in nvkm_device_tegra_power_up()
76 regulator_disable(tdev->vdd); in nvkm_device_tegra_power_up()
86 clk_disable_unprepare(tdev->clk_pwr); in nvkm_device_tegra_power_down()
87 clk_disable_unprepare(tdev->clk_ref); in nvkm_device_tegra_power_down()
88 clk_disable_unprepare(tdev->clk); in nvkm_device_tegra_power_down()
91 if (tdev->vdd) { in nvkm_device_tegra_power_down()
92 ret = regulator_disable(tdev->vdd); in nvkm_device_tegra_power_down()
104 struct device *dev = &tdev->pdev->dev; in nvkm_device_tegra_probe_iommu()
109 if (dev->archdata.mapping) { in nvkm_device_tegra_probe_iommu()
117 if (!tdev->func->iommu_bit) in nvkm_device_tegra_probe_iommu()
120 mutex_init(&tdev->iommu.mutex); in nvkm_device_tegra_probe_iommu()
123 tdev->iommu.domain = iommu_domain_alloc(&platform_bus_type); in nvkm_device_tegra_probe_iommu()
124 if (!tdev->iommu.domain) in nvkm_device_tegra_probe_iommu()
129 * or equal to the system's PAGE_SIZE, with a preference if in nvkm_device_tegra_probe_iommu()
132 pgsize_bitmap = tdev->iommu.domain->pgsize_bitmap; in nvkm_device_tegra_probe_iommu()
134 tdev->iommu.pgshift = PAGE_SHIFT; in nvkm_device_tegra_probe_iommu()
136 tdev->iommu.pgshift = fls(pgsize_bitmap & ~PAGE_MASK); in nvkm_device_tegra_probe_iommu()
137 if (tdev->iommu.pgshift == 0) { in nvkm_device_tegra_probe_iommu()
141 tdev->iommu.pgshift -= 1; in nvkm_device_tegra_probe_iommu()
144 ret = iommu_attach_device(tdev->iommu.domain, dev); in nvkm_device_tegra_probe_iommu()
148 ret = nvkm_mm_init(&tdev->iommu.mm, 0, 0, in nvkm_device_tegra_probe_iommu()
149 (1ULL << tdev->func->iommu_bit) >> in nvkm_device_tegra_probe_iommu()
150 tdev->iommu.pgshift, 1); in nvkm_device_tegra_probe_iommu()
158 iommu_detach_device(tdev->iommu.domain, dev); in nvkm_device_tegra_probe_iommu()
161 iommu_domain_free(tdev->iommu.domain); in nvkm_device_tegra_probe_iommu()
164 tdev->iommu.domain = NULL; in nvkm_device_tegra_probe_iommu()
165 tdev->iommu.pgshift = 0; in nvkm_device_tegra_probe_iommu()
174 if (tdev->iommu.domain) { in nvkm_device_tegra_remove_iommu()
175 nvkm_mm_fini(&tdev->iommu.mm); in nvkm_device_tegra_remove_iommu()
176 iommu_detach_device(tdev->iommu.domain, tdev->device.dev); in nvkm_device_tegra_remove_iommu()
177 iommu_domain_free(tdev->iommu.domain); in nvkm_device_tegra_remove_iommu()
192 return platform_get_resource(tdev->pdev, IORESOURCE_MEM, bar); in nvkm_device_tegra_resource()
199 return res ? res->start : 0; in nvkm_device_tegra_resource_addr()
214 return platform_get_irq_byname(tdev->pdev, "stall"); in nvkm_device_tegra_irq()
248 return -ENOMEM; in nvkm_device_tegra_new()
250 tdev->func = func; in nvkm_device_tegra_new()
251 tdev->pdev = pdev; in nvkm_device_tegra_new()
253 if (func->require_vdd) { in nvkm_device_tegra_new()
254 tdev->vdd = devm_regulator_get(&pdev->dev, "vdd"); in nvkm_device_tegra_new()
255 if (IS_ERR(tdev->vdd)) { in nvkm_device_tegra_new()
256 ret = PTR_ERR(tdev->vdd); in nvkm_device_tegra_new()
261 tdev->rst = devm_reset_control_get(&pdev->dev, "gpu"); in nvkm_device_tegra_new()
262 if (IS_ERR(tdev->rst)) { in nvkm_device_tegra_new()
263 ret = PTR_ERR(tdev->rst); in nvkm_device_tegra_new()
267 tdev->clk = devm_clk_get(&pdev->dev, "gpu"); in nvkm_device_tegra_new()
268 if (IS_ERR(tdev->clk)) { in nvkm_device_tegra_new()
269 ret = PTR_ERR(tdev->clk); in nvkm_device_tegra_new()
273 rate = clk_get_rate(tdev->clk); in nvkm_device_tegra_new()
275 ret = clk_set_rate(tdev->clk, ULONG_MAX); in nvkm_device_tegra_new()
279 rate = clk_get_rate(tdev->clk); in nvkm_device_tegra_new()
281 dev_dbg(&pdev->dev, "GPU clock set to %lu\n", rate); in nvkm_device_tegra_new()
284 if (func->require_ref_clk) in nvkm_device_tegra_new()
285 tdev->clk_ref = devm_clk_get(&pdev->dev, "ref"); in nvkm_device_tegra_new()
286 if (IS_ERR(tdev->clk_ref)) { in nvkm_device_tegra_new()
287 ret = PTR_ERR(tdev->clk_ref); in nvkm_device_tegra_new()
291 tdev->clk_pwr = devm_clk_get(&pdev->dev, "pwr"); in nvkm_device_tegra_new()
292 if (IS_ERR(tdev->clk_pwr)) { in nvkm_device_tegra_new()
293 ret = PTR_ERR(tdev->clk_pwr); in nvkm_device_tegra_new()
298 * The IOMMU bit defines the upper limit of the GPU-addressable space. in nvkm_device_tegra_new()
300 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(tdev->func->iommu_bit)); in nvkm_device_tegra_new()
310 tdev->gpu_speedo = tegra_sku_info.gpu_speedo_value; in nvkm_device_tegra_new()
311 tdev->gpu_speedo_id = tegra_sku_info.gpu_speedo_id; in nvkm_device_tegra_new()
312 ret = nvkm_device_ctor(&nvkm_device_tegra_func, NULL, &pdev->dev, in nvkm_device_tegra_new()
313 NVKM_DEVICE_TEGRA, pdev->id, NULL, in nvkm_device_tegra_new()
315 &tdev->device); in nvkm_device_tegra_new()
319 *pdevice = &tdev->device; in nvkm_device_tegra_new()
339 return -ENOSYS; in nvkm_device_tegra_new()