75 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
96 static int nouveau_noaccel = 0;
100 		          "0 = disabled, 1 = enabled, 2 = headless)");
105 static int nouveau_atomic = 0;
108 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
270 	ret = nvif_device_ctor(&cli->base.object, "drmDevice", 0, NV_DEVICE,  in nouveau_cli_init()
272 					.device = ~0,  in nouveau_cli_init()
282 	if (ret < 0) {  in nouveau_cli_init()
295 	if (ret < 0) {  in nouveau_cli_init()
307 	if (ret < 0) {  in nouveau_cli_init()
328 	return 0;  in nouveau_cli_init()
348 	int ret = 0;  in nouveau_accel_ce_init()
401 				       NULL, 0, &drm->channel->nvsw);  in nouveau_accel_gr_init()
403 		if (ret == 0 && device->info.chipset >= 0x11) {  in nouveau_accel_gr_init()
405 					       0x005f, 0x009f,  in nouveau_accel_gr_init()
406 					       NULL, 0, &drm->channel->blit);  in nouveau_accel_gr_init()
409 		if (ret == 0) {  in nouveau_accel_gr_init()
412 			if (ret == 0) {  in nouveau_accel_gr_init()
413 				if (device->info.chipset >= 0x11) {  in nouveau_accel_gr_init()
414 					PUSH_NVSQ(push, NV05F, 0x0000, drm->channel->blit.handle);  in nouveau_accel_gr_init()
415 					PUSH_NVSQ(push, NV09F, 0x0120, 0,  in nouveau_accel_gr_init()
416 							       0x0124, 1,  in nouveau_accel_gr_init()
417 							       0x0128, 2);  in nouveau_accel_gr_init()
419 				PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle);  in nouveau_accel_gr_init()
435 		ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL,  in nouveau_accel_gr_init()
488 	if (ret < 0)  in nouveau_accel_init()
491 	for (ret = -ENOSYS, i = 0; i < n; i++) {  in nouveau_accel_init()
595 	drm->sched_wq = alloc_workqueue("nouveau_sched_wq_shared", 0,  in nouveau_drm_device_init()
621 	if (drm->client.device.info.chipset == 0xc1)  in nouveau_drm_device_init()
622 		nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);  in nouveau_drm_device_init()
661 	return 0;  in nouveau_drm_device_init()
752  * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not
753  * documented PCI config space register 0x248 of the Intel PCIe bridge
754  * controller (0x1901) in order to change the state of the PCIe link between
757  *  - 0xbc bit 0x20 (publicly available documentation claims 'reserved')
758  *  - 0xb0 bit 0x10 (link disable)
763  * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared.
785 	case 0x1901:  in quirk_broken_nv_runpm()
787 		pdev->pm_cap = 0;  in quirk_broken_nv_runpm()
807 				  true, false, 0, &device);  in nouveau_drm_probe()
819 				  true, true, ~0ULL, &device);  in nouveau_drm_probe()
854 	return 0;  in nouveau_drm_probe()
946 	return 0;  in nouveau_do_suspend()
963 	int ret = 0;  in nouveau_do_resume()
987 	return 0;  in nouveau_do_resume()
999 		return 0;  in nouveau_pmops_suspend()
1009 	return 0;  in nouveau_pmops_suspend()
1021 		return 0;  in nouveau_pmops_resume()
1112 	nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));  in nouveau_pmops_runtime_resume()
1145 	if (ret < 0 && ret != -EACCES) {  in nouveau_drm_open()
1245 	if (ret < 0 && ret != -EACCES) {  in nouveau_drm_ioctl()
1320 		.class_mask  = 0xff << 16,
1325 		.class_mask  = 0xff << 16,
1376 				    true, true, ~0ULL, pdevice);  in nouveau_platform_device_create()
1412 			nouveau_modeset = 0;  in nouveau_drm_init()
1416 		return 0;  in nouveau_drm_init()
1428 	return 0;  in nouveau_drm_init()