Lines Matching full:base
13 void __iomem *base = phy->base; in dsi_20nm_dphy_set_timing() local
15 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0, in dsi_20nm_dphy_set_timing()
17 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1, in dsi_20nm_dphy_set_timing()
19 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2, in dsi_20nm_dphy_set_timing()
22 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3, in dsi_20nm_dphy_set_timing()
24 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4, in dsi_20nm_dphy_set_timing()
26 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5, in dsi_20nm_dphy_set_timing()
28 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6, in dsi_20nm_dphy_set_timing()
30 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7, in dsi_20nm_dphy_set_timing()
32 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8, in dsi_20nm_dphy_set_timing()
34 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_9, in dsi_20nm_dphy_set_timing()
37 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_10, in dsi_20nm_dphy_set_timing()
39 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_11, in dsi_20nm_dphy_set_timing()
45 void __iomem *base = phy->reg_base; in dsi_20nm_phy_regulator_ctrl() local
48 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0); in dsi_20nm_phy_regulator_ctrl()
53 dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x1d); in dsi_20nm_phy_regulator_ctrl()
58 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1, 0x03); in dsi_20nm_phy_regulator_ctrl()
59 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2, 0x03); in dsi_20nm_phy_regulator_ctrl()
60 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3, 0x00); in dsi_20nm_phy_regulator_ctrl()
61 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4, 0x20); in dsi_20nm_phy_regulator_ctrl()
62 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0x01); in dsi_20nm_phy_regulator_ctrl()
63 dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x00); in dsi_20nm_phy_regulator_ctrl()
64 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03); in dsi_20nm_phy_regulator_ctrl()
72 void __iomem *base = phy->base; in dsi_20nm_phy_enable() local
86 dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff); in dsi_20nm_phy_enable()
88 val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL); in dsi_20nm_phy_enable()
93 dsi_phy_write(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL, val); in dsi_20nm_phy_enable()
96 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i), in dsi_20nm_phy_enable()
98 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i), 0x01); in dsi_20nm_phy_enable()
99 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i), 0x46); in dsi_20nm_phy_enable()
100 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_0(i), 0x02); in dsi_20nm_phy_enable()
101 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_1(i), 0xa0); in dsi_20nm_phy_enable()
102 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_4(i), cfg_4[i]); in dsi_20nm_phy_enable()
105 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_3, 0x80); in dsi_20nm_phy_enable()
106 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR0, 0x01); in dsi_20nm_phy_enable()
107 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR1, 0x46); in dsi_20nm_phy_enable()
108 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_0, 0x00); in dsi_20nm_phy_enable()
109 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_1, 0xa0); in dsi_20nm_phy_enable()
110 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_2, 0x00); in dsi_20nm_phy_enable()
111 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_4, 0x00); in dsi_20nm_phy_enable()
115 dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_1, 0x00); in dsi_20nm_phy_enable()
117 dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_1, 0x06); in dsi_20nm_phy_enable()
121 dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_0, 0x7f); in dsi_20nm_phy_enable()
128 dsi_phy_write(phy->base + REG_DSI_20nm_PHY_CTRL_0, 0); in dsi_20nm_phy_disable()