Lines Matching +full:0 +full:x0000003f
57 NON_BURST_SYNCH_PULSE = 0,
63 VID_DST_FORMAT_RGB565 = 0,
70 SWAP_RGB = 0,
79 TRIGGER_NONE = 0,
88 CMD_DST_FORMAT_RGB111 = 0,
97 LANE_SWAP_0123 = 0,
108 VIDEO_CONFIG_18BPP = 0,
113 VID_PRBS = 0,
120 CMD_MDP_PRBS = 0,
127 CMD_DMA_PRBS = 0,
133 #define DSI_IRQ_CMD_DMA_DONE 0x00000001
134 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
135 #define DSI_IRQ_CMD_MDP_DONE 0x00000100
136 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
137 #define DSI_IRQ_VIDEO_DONE 0x00010000
138 #define DSI_IRQ_MASK_VIDEO_DONE 0x00020000
139 #define DSI_IRQ_BTA_DONE 0x00100000
140 #define DSI_IRQ_MASK_BTA_DONE 0x00200000
141 #define DSI_IRQ_ERROR 0x01000000
142 #define DSI_IRQ_MASK_ERROR 0x02000000
143 #define REG_DSI_6G_HW_VERSION 0x00000000
144 #define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000
150 #define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000
156 #define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff
157 #define DSI_6G_HW_VERSION_STEP__SHIFT 0
163 #define REG_DSI_CTRL 0x00000000
164 #define DSI_CTRL_ENABLE 0x00000001
165 #define DSI_CTRL_VID_MODE_EN 0x00000002
166 #define DSI_CTRL_CMD_MODE_EN 0x00000004
167 #define DSI_CTRL_LANE0 0x00000010
168 #define DSI_CTRL_LANE1 0x00000020
169 #define DSI_CTRL_LANE2 0x00000040
170 #define DSI_CTRL_LANE3 0x00000080
171 #define DSI_CTRL_CLK_EN 0x00000100
172 #define DSI_CTRL_ECC_CHECK 0x00100000
173 #define DSI_CTRL_CRC_CHECK 0x01000000
175 #define REG_DSI_STATUS0 0x00000004
176 #define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001
177 #define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002
178 #define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004
179 #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008
180 #define DSI_STATUS0_DSI_BUSY 0x00000010
181 #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000
183 #define REG_DSI_FIFO_STATUS 0x00000008
184 #define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW 0x00000001
185 #define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW 0x00000008
186 #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080
187 #define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH 0x00000100
188 #define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH 0x00000200
189 #define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW 0x00000400
190 #define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY 0x00001000
191 #define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL 0x00002000
192 #define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW 0x00004000
193 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY 0x00010000
194 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL 0x00020000
195 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW 0x00040000
196 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW 0x00080000
197 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY 0x00100000
198 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL 0x00200000
199 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW 0x00400000
200 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW 0x00800000
201 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY 0x01000000
202 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL 0x02000000
203 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW 0x04000000
204 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW 0x08000000
205 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY 0x10000000
206 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL 0x20000000
207 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW 0x40000000
208 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW 0x80000000
210 #define REG_DSI_VID_CFG0 0x0000000c
211 #define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003
212 #define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0
217 #define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030
223 #define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300
229 #define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000
230 #define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000
231 #define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000
232 #define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000
233 #define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000
234 #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000
236 #define REG_DSI_VID_CFG1 0x0000001c
237 #define DSI_VID_CFG1_R_SEL 0x00000001
238 #define DSI_VID_CFG1_G_SEL 0x00000010
239 #define DSI_VID_CFG1_B_SEL 0x00000100
240 #define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000
247 #define REG_DSI_ACTIVE_H 0x00000020
248 #define DSI_ACTIVE_H_START__MASK 0x00000fff
249 #define DSI_ACTIVE_H_START__SHIFT 0
254 #define DSI_ACTIVE_H_END__MASK 0x0fff0000
261 #define REG_DSI_ACTIVE_V 0x00000024
262 #define DSI_ACTIVE_V_START__MASK 0x00000fff
263 #define DSI_ACTIVE_V_START__SHIFT 0
268 #define DSI_ACTIVE_V_END__MASK 0x0fff0000
275 #define REG_DSI_TOTAL 0x00000028
276 #define DSI_TOTAL_H_TOTAL__MASK 0x00000fff
277 #define DSI_TOTAL_H_TOTAL__SHIFT 0
282 #define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000
289 #define REG_DSI_ACTIVE_HSYNC 0x0000002c
290 #define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff
291 #define DSI_ACTIVE_HSYNC_START__SHIFT 0
296 #define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000
303 #define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030
304 #define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff
305 #define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0
310 #define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000
317 #define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034
318 #define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff
319 #define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0
324 #define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000
331 #define REG_DSI_CMD_DMA_CTRL 0x00000038
332 #define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000
333 #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000
334 #define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000
336 #define REG_DSI_CMD_CFG0 0x0000003c
337 #define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f
338 #define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0
343 #define DSI_CMD_CFG0_R_SEL 0x00000010
344 #define DSI_CMD_CFG0_G_SEL 0x00000100
345 #define DSI_CMD_CFG0_B_SEL 0x00001000
346 #define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000
352 #define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000
359 #define REG_DSI_CMD_CFG1 0x00000040
360 #define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff
361 #define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0
366 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00
372 #define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000
374 #define REG_DSI_DMA_BASE 0x00000044
376 #define REG_DSI_DMA_LEN 0x00000048
378 #define REG_DSI_CMD_MDP_STREAM0_CTRL 0x00000054
379 #define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK 0x0000003f
380 #define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT 0
385 #define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
391 #define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK 0xffff0000
398 #define REG_DSI_CMD_MDP_STREAM0_TOTAL 0x00000058
399 #define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK 0x00000fff
400 #define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT 0
405 #define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK 0x0fff0000
412 #define REG_DSI_CMD_MDP_STREAM1_CTRL 0x0000005c
413 #define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK 0x0000003f
414 #define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT 0
419 #define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
425 #define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK 0xffff0000
432 #define REG_DSI_CMD_MDP_STREAM1_TOTAL 0x00000060
433 #define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK 0x0000ffff
434 #define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT 0
439 #define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK 0xffff0000
446 #define REG_DSI_ACK_ERR_STATUS 0x00000064
448 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } in REG_DSI_RDBK()
450 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } in REG_DSI_RDBK_DATA()
452 #define REG_DSI_TRIG_CTRL 0x00000080
453 #define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007
454 #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0
459 #define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070
465 #define DSI_TRIG_CTRL_STREAM__MASK 0x00000300
471 #define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000
472 #define DSI_TRIG_CTRL_TE 0x80000000
474 #define REG_DSI_TRIG_DMA 0x0000008c
476 #define REG_DSI_DLN0_PHY_ERR 0x000000b0
477 #define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001
478 #define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010
479 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100
480 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000
481 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000
483 #define REG_DSI_LP_TIMER_CTRL 0x000000b4
484 #define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK 0x0000ffff
485 #define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT 0
490 #define DSI_LP_TIMER_CTRL_BTA_TO__MASK 0xffff0000
497 #define REG_DSI_HS_TIMER_CTRL 0x000000b8
498 #define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK 0x0000ffff
499 #define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT 0
504 #define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK 0x000f0000
510 #define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN 0x10000000
512 #define REG_DSI_TIMEOUT_STATUS 0x000000bc
514 #define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0
515 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f
516 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0
521 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00
528 #define REG_DSI_EOT_PACKET_CTRL 0x000000c8
529 #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001
530 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010
532 #define REG_DSI_LANE_STATUS 0x000000a4
533 #define DSI_LANE_STATUS_DLN0_STOPSTATE 0x00000001
534 #define DSI_LANE_STATUS_DLN1_STOPSTATE 0x00000002
535 #define DSI_LANE_STATUS_DLN2_STOPSTATE 0x00000004
536 #define DSI_LANE_STATUS_DLN3_STOPSTATE 0x00000008
537 #define DSI_LANE_STATUS_CLKLN_STOPSTATE 0x00000010
538 #define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT 0x00000100
539 #define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT 0x00000200
540 #define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT 0x00000400
541 #define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT 0x00000800
542 #define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT 0x00001000
543 #define DSI_LANE_STATUS_DLN0_DIRECTION 0x00010000
545 #define REG_DSI_LANE_CTRL 0x000000a8
546 #define DSI_LANE_CTRL_HS_REQ_SEL_PHY 0x01000000
547 #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000
549 #define REG_DSI_LANE_SWAP_CTRL 0x000000ac
550 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007
551 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0
557 #define REG_DSI_ERR_INT_MASK0 0x00000108
559 #define REG_DSI_INTR_CTRL 0x0000010c
561 #define REG_DSI_RESET 0x00000114
563 #define REG_DSI_CLK_CTRL 0x00000118
564 #define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001
565 #define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002
566 #define DSI_CLK_CTRL_PCLK_ON 0x00000004
567 #define DSI_CLK_CTRL_DSICLK_ON 0x00000008
568 #define DSI_CLK_CTRL_BYTECLK_ON 0x00000010
569 #define DSI_CLK_CTRL_ESCCLK_ON 0x00000020
570 #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200
572 #define REG_DSI_CLK_STATUS 0x0000011c
573 #define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE 0x00000001
574 #define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE 0x00000002
575 #define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE 0x00000004
576 #define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE 0x00000008
577 #define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE 0x00000010
578 #define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE 0x00000020
579 #define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE 0x00000040
580 #define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE 0x00000080
581 #define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE 0x00000100
582 #define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE 0x00000200
583 #define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE 0x00000400
584 #define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE 0x00001000
585 #define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE 0x00002000
586 #define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE 0x00004000
587 #define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT 0x00008000
588 #define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000
590 #define REG_DSI_PHY_RESET 0x00000128
591 #define DSI_PHY_RESET_RESET 0x00000001
593 #define REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL 0x00000160
595 #define REG_DSI_TPG_MAIN_CONTROL 0x00000198
596 #define DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN 0x00000100
598 #define REG_DSI_TPG_VIDEO_CONFIG 0x000001a0
599 #define DSI_TPG_VIDEO_CONFIG_BPP__MASK 0x00000003
600 #define DSI_TPG_VIDEO_CONFIG_BPP__SHIFT 0
605 #define DSI_TPG_VIDEO_CONFIG_RGB 0x00000004
607 #define REG_DSI_TEST_PATTERN_GEN_CTRL 0x00000158
608 #define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__MASK 0x00030000
614 #define DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__MASK 0x00000300
620 #define DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__MASK 0x00000030
626 #define DSI_TEST_PATTERN_GEN_CTRL_TPG_DMA_FIFO_MODE 0x00000004
627 #define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_TPG_EN 0x00000002
628 #define DSI_TEST_PATTERN_GEN_CTRL_EN 0x00000001
630 #define REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0 0x00000168
632 #define REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER 0x00000180
633 #define DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER 0x00000001
635 #define REG_DSI_TPG_MAIN_CONTROL2 0x0000019c
636 #define DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN 0x00000080
637 #define DSI_TPG_MAIN_CONTROL2_CMD_MDP1_CHECKERED_RECTANGLE_PATTERN 0x00010000
638 #define DSI_TPG_MAIN_CONTROL2_CMD_MDP2_CHECKERED_RECTANGLE_PATTERN 0x02000000
640 #define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c
641 #define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001
643 #define REG_DSI_CMD_MODE_MDP_CTRL2 0x000001b4
644 #define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK 0x0000000f
645 #define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT 0
650 #define DSI_CMD_MODE_MDP_CTRL2_R_SEL 0x00000010
651 #define DSI_CMD_MODE_MDP_CTRL2_G_SEL 0x00000020
652 #define DSI_CMD_MODE_MDP_CTRL2_B_SEL 0x00000040
653 #define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP 0x00000080
654 #define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK 0x00000700
660 #define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK 0x00007000
666 #define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000
667 #define DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN 0x00100000
669 #define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8
670 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f
671 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT 0
676 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
682 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK 0xffff0000
689 #define REG_DSI_RDBK_DATA_CTRL 0x000001d0
690 #define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000
696 #define DSI_RDBK_DATA_CTRL_CLR 0x00000001
698 #define REG_DSI_VERSION 0x000001f0
699 #define DSI_VERSION_MAJOR__MASK 0xff000000
706 #define REG_DSI_CPHY_MODE_CTRL 0x000002d4
708 #define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
709 #define DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__MASK 0xffff0000
715 #define DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__MASK 0x00003f00
721 #define DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__MASK 0x000000c0
727 #define DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__MASK 0x00000030
733 #define DSI_VIDEO_COMPRESSION_MODE_CTRL_EN 0x00000001
735 #define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
736 #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__MASK 0x3f000000
742 #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__MASK 0x00c00000
748 #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__MASK 0x00300000
754 #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EN 0x00010000
755 #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__MASK 0x00003f00
761 #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__MASK 0x000000c0
767 #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__MASK 0x00000030
773 #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EN 0x00000001
775 #define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
776 #define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__MASK 0xffff0000
782 #define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK 0x0000ffff
783 #define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__SHIFT 0