56 enum mdp5_intf_type {
66 enum mdp5_intfnum {
74 enum mdp5_pipe {
90 enum mdp5_format {
94 enum mdp5_ctl_mode {
103 enum mdp5_pack_3d {
110 enum mdp5_scale_filter {
117 enum mdp5_pipe_bwc {
123 enum mdp5_cursor_format {
129 enum mdp5_cursor_alpha {
134 enum mdp5_igc_type {
141 enum mdp5_data_format {
146 enum mdp5_block_size {
151 enum mdp5_rotate_mode {
156 enum mdp5_chroma_downsample_method {
238 static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)  in MDP5_DISP_INTF_SEL_INTF0()
244 static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)  in MDP5_DISP_INTF_SEL_INTF1()
250 static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)  in MDP5_DISP_INTF_SEL_INTF2()
256 static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)  in MDP5_DISP_INTF_SEL_INTF3()
320 static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)  in __offset_IGC()
330 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }  in REG_MDP5_IGC()
332 static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + _…  in REG_MDP5_IGC_LUT()
334 static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000…  in REG_MDP5_IGC_LUT_REG()
454 static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)  in MDP5_CTL_OP_MODE()
460 static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)  in MDP5_CTL_OP_INTF_NUM()
468 static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)  in MDP5_CTL_OP_PACK_3D()
535 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val)  in MDP5_CTL_LAYER_EXT_REG_CURSOR0()
541 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val)  in MDP5_CTL_LAYER_EXT_REG_CURSOR1()
546 static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)  in __offset_PIPE()
565 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }  in REG_MDP5_PIPE()
567 static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE…  in REG_MDP5_PIPE_OP_MODE()
570 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)  in MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT()
576 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)  in MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT()
582 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offse…  in REG_MDP5_PIPE_HIST_CTL_BASE()
584 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offse…  in REG_MDP5_PIPE_HIST_LUT_BASE()
586 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offse…  in REG_MDP5_PIPE_HIST_LUT_SWAP()
588 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0()
602 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1()
616 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2()
630 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3()
644 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4()
652 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP5_PIPE_CSC_1_PRE_CLAMP()
654 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0…  in REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG()
668 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00…  in REG_MDP5_PIPE_CSC_1_POST_CLAMP()
670 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return …  in REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG()
684 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000…  in REG_MDP5_PIPE_CSC_1_PRE_BIAS()
686 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x…  in REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG()
694 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP5_PIPE_CSC_1_POST_BIAS()
696 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0…  in REG_MDP5_PIPE_CSC_1_POST_BIAS_REG()
704 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIP…  in REG_MDP5_PIPE_SRC_SIZE()
718 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset…  in REG_MDP5_PIPE_SRC_IMG_SIZE()
732 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(…  in REG_MDP5_PIPE_SRC_XY()
746 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIP…  in REG_MDP5_PIPE_OUT_SIZE()
760 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(…  in REG_MDP5_PIPE_OUT_XY()
774 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PI…  in REG_MDP5_PIPE_SRC0_ADDR()
776 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PI…  in REG_MDP5_PIPE_SRC1_ADDR()
778 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PI…  in REG_MDP5_PIPE_SRC2_ADDR()
780 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PI…  in REG_MDP5_PIPE_SRC3_ADDR()
782 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset…  in REG_MDP5_PIPE_SRC_STRIDE_A()
796 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset…  in REG_MDP5_PIPE_SRC_STRIDE_B()
810 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __of…  in REG_MDP5_PIPE_STILE_FRAME_SIZE()
812 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_P…  in REG_MDP5_PIPE_SRC_FORMAT()
815 static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)  in MDP5_PIPE_SRC_FORMAT_G_BPC()
821 static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)  in MDP5_PIPE_SRC_FORMAT_B_BPC()
827 static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)  in MDP5_PIPE_SRC_FORMAT_R_BPC()
833 static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)  in MDP5_PIPE_SRC_FORMAT_A_BPC()
855 static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)  in MDP5_PIPE_SRC_FORMAT_FETCH_TYPE()
861 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)  in MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP()
866 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_P…  in REG_MDP5_PIPE_SRC_UNPACK()
892 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_…  in REG_MDP5_PIPE_SRC_OP_MODE()
896 static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)  in MDP5_PIPE_SRC_OP_MODE_BWC()
909 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __…  in REG_MDP5_PIPE_SRC_CONSTANT_COLOR()
911 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset…  in REG_MDP5_PIPE_FETCH_CONFIG()
913 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PI…  in REG_MDP5_PIPE_VC1_RANGE()
915 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_0()
917 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_1()
919 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_2()
921 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __…  in REG_MDP5_PIPE_SRC_ADDR_SW_STATUS()
923 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __o…  in REG_MDP5_PIPE_CURRENT_SRC0_ADDR()
925 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __o…  in REG_MDP5_PIPE_CURRENT_SRC1_ADDR()
927 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __o…  in REG_MDP5_PIPE_CURRENT_SRC2_ADDR()
929 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __o…  in REG_MDP5_PIPE_CURRENT_SRC3_ADDR()
931 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_P…  in REG_MDP5_PIPE_DECIMATION()
945 static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx)  in __offset_SW_PIX_EXT()
954 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { re…  in REG_MDP5_PIPE_SW_PIX_EXT()
956 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) {…  in REG_MDP5_PIPE_SW_PIX_EXT_LR()
982 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) {…  in REG_MDP5_PIPE_SW_PIX_EXT_TB()
1008 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_ty…  in REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS()
1022 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset…  in REG_MDP5_PIPE_SCALE_CONFIG()
1027 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0()
1033 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0()
1039 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2()
1045 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2()
1051 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3()
1057 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3()
1062 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __…  in REG_MDP5_PIPE_SCALE_PHASE_STEP_X()
1064 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __…  in REG_MDP5_PIPE_SCALE_PHASE_STEP_Y()
1066 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 +…  in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X()
1068 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c +…  in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y()
1070 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __…  in REG_MDP5_PIPE_SCALE_INIT_PHASE_X()
1072 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __…  in REG_MDP5_PIPE_SCALE_INIT_PHASE_Y()
1134 static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)  in MDP5_LM_BLEND_OP_MODE_FG_ALPHA()
1144 static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)  in MDP5_LM_BLEND_OP_MODE_BG_ALPHA()
1226 static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)  in MDP5_LM_CURSOR_FORMAT_FORMAT()
1251 static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)  in MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL()