56 enum mdp4_pipe {
66 enum mdp4_mixer {
72 enum mdp4_intf {
79 enum mdp4_cursor_format {
84 enum mdp4_frame_format {
90 enum mdp4_scale_unit {
96 enum mdp4_dma {
148 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_PRIM()
154 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_SEC()
160 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_EXT()
190 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE0()
197 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE1()
204 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE2()
211 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE3()
218 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE4()
225 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE5()
232 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE6()
239 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE7()
250 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE0()
257 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE1()
264 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE2()
271 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE3()
278 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE4()
285 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE5()
292 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE6()
299 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE7()
365 static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)  in MDP4_OVLP_STAGE_OP_FG_ALPHA()
373 static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)  in MDP4_OVLP_STAGE_OP_BG_ALPHA()
454 static inline uint32_t __offset_DMA(enum mdp4_dma idx)  in __offset_DMA()
463 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }  in REG_MDP4_DMA()
465 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0)…  in REG_MDP4_DMA_CONFIG()
468 static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_G_BPC()
474 static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_B_BPC()
480 static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_R_BPC()
494 static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i…  in REG_MDP4_DMA_SRC_SIZE()
508 static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i…  in REG_MDP4_DMA_SRC_BASE()
510 static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA…  in REG_MDP4_DMA_SRC_STRIDE()
512 static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i…  in REG_MDP4_DMA_DST_SIZE()
526 static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DM…  in REG_MDP4_DMA_CURSOR_SIZE()
540 static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DM…  in REG_MDP4_DMA_CURSOR_BASE()
542 static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA…  in REG_MDP4_DMA_CURSOR_POS()
556 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __o…  in REG_MDP4_DMA_CURSOR_BLEND_CONFIG()
560 static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)  in MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT()
566 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __of…  in REG_MDP4_DMA_CURSOR_BLEND_PARAM()
568 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offse…  in REG_MDP4_DMA_BLEND_TRANS_LOW()
570 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offs…  in REG_MDP4_DMA_BLEND_TRANS_HIGH()
572 static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_D…  in REG_MDP4_DMA_FETCH_CONFIG()
574 static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); }  in REG_MDP4_DMA_CSC()
577 static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __o…  in REG_MDP4_DMA_CSC_MV()
579 static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 +…  in REG_MDP4_DMA_CSC_MV_VAL()
581 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 +…  in REG_MDP4_DMA_CSC_PRE_BV()
583 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x000035…  in REG_MDP4_DMA_CSC_PRE_BV_VAL()
585 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 …  in REG_MDP4_DMA_CSC_POST_BV()
587 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003…  in REG_MDP4_DMA_CSC_POST_BV_VAL()
589 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 +…  in REG_MDP4_DMA_CSC_PRE_LV()
591 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x000036…  in REG_MDP4_DMA_CSC_PRE_LV_VAL()
593 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 …  in REG_MDP4_DMA_CSC_POST_LV()
595 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003…  in REG_MDP4_DMA_CSC_POST_LV_VAL()
597 static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }  in REG_MDP4_PIPE()
599 static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }  in REG_MDP4_PIPE_SRC_SIZE()
613 static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; }  in REG_MDP4_PIPE_SRC_XY()
627 static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; }  in REG_MDP4_PIPE_DST_SIZE()
641 static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; }  in REG_MDP4_PIPE_DST_XY()
655 static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0…  in REG_MDP4_PIPE_SRCP0_BASE()
657 static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0…  in REG_MDP4_PIPE_SRCP1_BASE()
659 static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0…  in REG_MDP4_PIPE_SRCP2_BASE()
661 static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0…  in REG_MDP4_PIPE_SRCP3_BASE()
663 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*…  in REG_MDP4_PIPE_SRC_STRIDE_A()
677 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*…  in REG_MDP4_PIPE_SRC_STRIDE_B()
691 static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x1…  in REG_MDP4_PIPE_SSTILE_FRAME_SIZE()
705 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0…  in REG_MDP4_PIPE_SRC_FORMAT()
708 static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_G_BPC()
714 static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_B_BPC()
720 static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_R_BPC()
726 static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)  in MDP4_PIPE_SRC_FORMAT_A_BPC()
755 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)  in MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP()
761 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val)  in MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT()
766 static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0…  in REG_MDP4_PIPE_SRC_UNPACK()
792 static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; }  in REG_MDP4_PIPE_OP_MODE()
797 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val)  in MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL()
803 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val)  in MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL()
817 static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i…  in REG_MDP4_PIPE_PHASEX_STEP()
819 static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i…  in REG_MDP4_PIPE_PHASEY_STEP()
821 static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*…  in REG_MDP4_PIPE_FETCH_CONFIG()
823 static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i…  in REG_MDP4_PIPE_SOLID_COLOR()
825 static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; }  in REG_MDP4_PIPE_CSC()
828 static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0…  in REG_MDP4_PIPE_CSC_MV()
830 static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400…  in REG_MDP4_PIPE_CSC_MV_VAL()
832 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500…  in REG_MDP4_PIPE_CSC_PRE_BV()
834 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x0002…  in REG_MDP4_PIPE_CSC_PRE_BV_VAL()
836 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x0002458…  in REG_MDP4_PIPE_CSC_POST_BV()
838 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP4_PIPE_CSC_POST_BV_VAL()
840 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600…  in REG_MDP4_PIPE_CSC_PRE_LV()
842 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x0002…  in REG_MDP4_PIPE_CSC_PRE_LV_VAL()
844 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x0002468…  in REG_MDP4_PIPE_CSC_POST_LV()
846 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP4_PIPE_CSC_POST_LV_VAL()