Lines Matching +full:sc7180 +full:- +full:dp
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
13 #include <linux/dma-buf.h>
62 struct dpu_kms *kms = s->private; in _dpu_danger_signal_status()
65 if (!kms->hw_mdp) { in _dpu_danger_signal_status()
72 pm_runtime_get_sync(&kms->pdev->dev); in _dpu_danger_signal_status()
75 if (kms->hw_mdp->ops.get_danger_status) in _dpu_danger_signal_status()
76 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, in _dpu_danger_signal_status()
80 if (kms->hw_mdp->ops.get_safe_status) in _dpu_danger_signal_status()
81 kms->hw_mdp->ops.get_safe_status(kms->hw_mdp, in _dpu_danger_signal_status()
84 pm_runtime_put_sync(&kms->pdev->dev); in _dpu_danger_signal_status()
89 seq_printf(s, "SSPP%d : 0x%x \n", i - SSPP_VIG0, in _dpu_danger_signal_status()
111 struct dpu_kms *kms = file->private_data; in _dpu_plane_danger_read()
115 len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); in _dpu_plane_danger_read()
124 drm_for_each_plane(plane, kms->dev) { in _dpu_plane_set_danger_state()
125 if (plane->fb && plane->state) { in _dpu_plane_set_danger_state()
128 plane->base.id, plane->fb->width, in _dpu_plane_set_danger_state()
129 plane->fb->height); in _dpu_plane_set_danger_state()
131 plane->state->src_x >> 16, in _dpu_plane_set_danger_state()
132 plane->state->src_y >> 16, in _dpu_plane_set_danger_state()
133 plane->state->src_w >> 16, in _dpu_plane_set_danger_state()
134 plane->state->src_h >> 16, in _dpu_plane_set_danger_state()
135 plane->state->crtc_x, plane->state->crtc_y, in _dpu_plane_set_danger_state()
136 plane->state->crtc_w, plane->state->crtc_h); in _dpu_plane_set_danger_state()
138 DPU_DEBUG("Inactive plane:%d\n", plane->base.id); in _dpu_plane_set_danger_state()
146 struct dpu_kms *kms = file->private_data; in _dpu_plane_danger_write()
158 kms->has_danger_ctrl = false; in _dpu_plane_danger_write()
162 kms->has_danger_ctrl = true; in _dpu_plane_danger_write()
200 struct dpu_debugfs_regset32 *regset = s->private; in dpu_regset32_show()
201 struct dpu_kms *dpu_kms = regset->dpu_kms; in dpu_regset32_show()
205 if (!dpu_kms->mmio) in dpu_regset32_show()
208 base = dpu_kms->mmio + regset->offset; in dpu_regset32_show()
211 if (regset->offset & 0xF) { in dpu_regset32_show()
212 seq_printf(s, "[%x]", regset->offset & ~0xF); in dpu_regset32_show()
213 for (i = 0; i < (regset->offset & 0xF); i += 4) in dpu_regset32_show()
217 pm_runtime_get_sync(&dpu_kms->pdev->dev); in dpu_regset32_show()
220 for (i = 0; i < regset->blk_len; i += 4) { in dpu_regset32_show()
221 addr = regset->offset + i; in dpu_regset32_show()
227 pm_runtime_put_sync(&dpu_kms->pdev->dev); in dpu_regset32_show()
242 regset = devm_kzalloc(&dpu_kms->pdev->dev, sizeof(*regset), GFP_KERNEL); in dpu_debugfs_create_regset32()
247 regset->offset = round_down(offset, 4); in dpu_debugfs_create_regset32()
248 regset->blk_len = length; in dpu_debugfs_create_regset32()
249 regset->dpu_kms = dpu_kms; in dpu_debugfs_create_regset32()
263 struct dpu_hw_sspp *hw = dpu_rm_get_sspp(&dpu_kms->rm, i); in dpu_debugfs_sspp_init()
279 return -EINVAL; in dpu_kms_debugfs_init()
282 if (minor->type != DRM_MINOR_PRIMARY) in dpu_kms_debugfs_init()
285 entry = debugfs_create_dir("debug", minor->debugfs_root); in dpu_kms_debugfs_init()
308 return to_dpu_global_state(dpu_kms->global_state.state); in dpu_kms_get_existing_global_state()
317 struct msm_drm_private *priv = s->dev->dev_private; in dpu_kms_get_global_state()
318 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); in dpu_kms_get_global_state()
322 ret = drm_modeset_lock(&dpu_kms->global_state_lock, s->acquire_ctx); in dpu_kms_get_global_state()
327 &dpu_kms->global_state); in dpu_kms_get_global_state()
339 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); in dpu_kms_global_duplicate_state()
343 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); in dpu_kms_global_duplicate_state()
345 return &state->base; in dpu_kms_global_duplicate_state()
365 drm_modeset_lock_init(&dpu_kms->global_state_lock); in dpu_kms_global_obj_init()
369 return -ENOMEM; in dpu_kms_global_obj_init()
371 drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state, in dpu_kms_global_obj_init()
372 &state->base, in dpu_kms_global_obj_init()
381 struct device *dpu_dev = &dpu_kms->pdev->dev; in dpu_kms_parse_data_bus_icc_path()
383 path0 = msm_icc_get(dpu_dev, "mdp0-mem"); in dpu_kms_parse_data_bus_icc_path()
384 path1 = msm_icc_get(dpu_dev, "mdp1-mem"); in dpu_kms_parse_data_bus_icc_path()
389 dpu_kms->path[0] = path0; in dpu_kms_parse_data_bus_icc_path()
390 dpu_kms->num_paths = 1; in dpu_kms_parse_data_bus_icc_path()
393 dpu_kms->path[1] = path1; in dpu_kms_parse_data_bus_icc_path()
394 dpu_kms->num_paths++; in dpu_kms_parse_data_bus_icc_path()
412 pm_runtime_get_sync(&dpu_kms->pdev->dev); in dpu_kms_enable_commit()
418 pm_runtime_put_sync(&dpu_kms->pdev->dev); in dpu_kms_disable_commit()
426 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) { in dpu_kms_flush_commit()
427 if (!crtc->state->active) in dpu_kms_flush_commit()
442 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) in dpu_kms_complete_commit()
455 if (!kms || !crtc || !crtc->state) { in dpu_kms_wait_for_commit_done()
460 dev = crtc->dev; in dpu_kms_wait_for_commit_done()
462 if (!crtc->state->enable) { in dpu_kms_wait_for_commit_done()
463 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id); in dpu_kms_wait_for_commit_done()
467 if (!drm_atomic_crtc_effectively_active(crtc->state)) { in dpu_kms_wait_for_commit_done()
468 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id); in dpu_kms_wait_for_commit_done()
472 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dpu_kms_wait_for_commit_done()
473 if (encoder->crtc != crtc) in dpu_kms_wait_for_commit_done()
476 * Wait for post-flush if necessary to delay before in dpu_kms_wait_for_commit_done()
478 * mode panels. This may be a no-op for command mode panels. in dpu_kms_wait_for_commit_done()
482 if (ret && ret != -EWOULDBLOCK) { in dpu_kms_wait_for_commit_done()
494 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) in dpu_kms_wait_flush()
506 if (!(priv->dsi[0] || priv->dsi[1])) in _dpu_kms_initialize_dsi()
511 * - Single DSI host (dsi0 or dsi1) in _dpu_kms_initialize_dsi()
512 * - Two independent DSI hosts in _dpu_kms_initialize_dsi()
513 * - Bonded DSI0 and DSI1 hosts in _dpu_kms_initialize_dsi()
517 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) { in _dpu_kms_initialize_dsi()
520 if (!priv->dsi[i]) in _dpu_kms_initialize_dsi()
523 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && in _dpu_kms_initialize_dsi()
524 !msm_dsi_is_master_dsi(priv->dsi[i])) in _dpu_kms_initialize_dsi()
531 if (msm_dsi_is_bonded_dsi(priv->dsi[i])) in _dpu_kms_initialize_dsi()
534 info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]); in _dpu_kms_initialize_dsi()
542 rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder); in _dpu_kms_initialize_dsi()
549 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) { in _dpu_kms_initialize_dsi()
550 rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder); in _dpu_kms_initialize_dsi()
571 for (i = 0; i < ARRAY_SIZE(priv->dp); i++) { in _dpu_kms_initialize_displayport()
572 if (!priv->dp[i]) in _dpu_kms_initialize_displayport()
586 rc = msm_dp_modeset_init(priv->dp[i], dev, encoder); in _dpu_kms_initialize_displayport()
588 DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc); in _dpu_kms_initialize_displayport()
604 if (!priv->hdmi) in _dpu_kms_initialize_hdmi()
618 rc = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); in _dpu_kms_initialize_hdmi()
620 DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc); in _dpu_kms_initialize_hdmi()
659 * _dpu_kms_setup_displays - create encoders, bridges and connectors
692 if (dpu_kms->catalog->wb_count) { in _dpu_kms_setup_displays()
693 for (i = 0; i < dpu_kms->catalog->wb_count; i++) { in _dpu_kms_setup_displays()
694 if (dpu_kms->catalog->wb[i].id == WB_2) { in _dpu_kms_setup_displays()
696 dpu_kms->catalog->wb[i].format_list, in _dpu_kms_setup_displays()
697 dpu_kms->catalog->wb[i].num_formats); in _dpu_kms_setup_displays()
724 dev = dpu_kms->dev; in _dpu_kms_drm_obj_init()
725 priv = dev->dev_private; in _dpu_kms_drm_obj_init()
726 catalog = dpu_kms->catalog; in _dpu_kms_drm_obj_init()
740 max_crtc_count = min(catalog->mixer_count, num_encoders); in _dpu_kms_drm_obj_init()
743 for (i = 0; i < catalog->sspp_count; i++) { in _dpu_kms_drm_obj_init()
746 if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) in _dpu_kms_drm_obj_init()
755 type, catalog->sspp[i].features, in _dpu_kms_drm_obj_init()
756 catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)); in _dpu_kms_drm_obj_init()
758 plane = dpu_plane_init(dev, catalog->sspp[i].id, type, in _dpu_kms_drm_obj_init()
759 (1UL << max_crtc_count) - 1); in _dpu_kms_drm_obj_init()
781 priv->num_crtcs++; in _dpu_kms_drm_obj_init()
786 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; in _dpu_kms_drm_obj_init()
795 dpu_kms->hw_intr = NULL; in _dpu_kms_hw_destroy()
800 for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) { in _dpu_kms_hw_destroy()
801 dpu_kms->hw_vbif[i] = NULL; in _dpu_kms_hw_destroy()
804 dpu_kms->catalog = NULL; in _dpu_kms_hw_destroy()
806 dpu_kms->hw_mdp = NULL; in _dpu_kms_hw_destroy()
822 msm_kms_destroy(&dpu_kms->base); in dpu_kms_destroy()
824 if (dpu_kms->rpm_enabled) in dpu_kms_destroy()
825 pm_runtime_disable(&dpu_kms->pdev->dev); in dpu_kms_destroy()
833 if (!dpu_kms || !dpu_kms->dev) in dpu_irq_postinstall()
834 return -EINVAL; in dpu_irq_postinstall()
836 priv = dpu_kms->dev->dev_private; in dpu_irq_postinstall()
838 return -EINVAL; in dpu_irq_postinstall()
852 cat = dpu_kms->catalog; in dpu_kms_mdp_snapshot()
854 pm_runtime_get_sync(&dpu_kms->pdev->dev); in dpu_kms_mdp_snapshot()
856 /* dump CTL sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
857 for (i = 0; i < cat->ctl_count; i++) in dpu_kms_mdp_snapshot()
858 msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len, in dpu_kms_mdp_snapshot()
859 dpu_kms->mmio + cat->ctl[i].base, cat->ctl[i].name); in dpu_kms_mdp_snapshot()
861 /* dump DSPP sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
862 for (i = 0; i < cat->dspp_count; i++) { in dpu_kms_mdp_snapshot()
863 base = dpu_kms->mmio + cat->dspp[i].base; in dpu_kms_mdp_snapshot()
864 msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, base, cat->dspp[i].name); in dpu_kms_mdp_snapshot()
866 if (cat->dspp[i].sblk && cat->dspp[i].sblk->pcc.len > 0) in dpu_kms_mdp_snapshot()
867 msm_disp_snapshot_add_block(disp_state, cat->dspp[i].sblk->pcc.len, in dpu_kms_mdp_snapshot()
868 base + cat->dspp[i].sblk->pcc.base, "%s_%s", in dpu_kms_mdp_snapshot()
869 cat->dspp[i].name, in dpu_kms_mdp_snapshot()
870 cat->dspp[i].sblk->pcc.name); in dpu_kms_mdp_snapshot()
873 /* dump INTF sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
874 for (i = 0; i < cat->intf_count; i++) in dpu_kms_mdp_snapshot()
875 msm_disp_snapshot_add_block(disp_state, cat->intf[i].len, in dpu_kms_mdp_snapshot()
876 dpu_kms->mmio + cat->intf[i].base, cat->intf[i].name); in dpu_kms_mdp_snapshot()
878 /* dump PP sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
879 for (i = 0; i < cat->pingpong_count; i++) { in dpu_kms_mdp_snapshot()
880 base = dpu_kms->mmio + cat->pingpong[i].base; in dpu_kms_mdp_snapshot()
881 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, base, in dpu_kms_mdp_snapshot()
882 cat->pingpong[i].name); in dpu_kms_mdp_snapshot()
884 /* TE2 sub-block has length of 0, so will not print it */ in dpu_kms_mdp_snapshot()
886 if (cat->pingpong[i].sblk && cat->pingpong[i].sblk->dither.len > 0) in dpu_kms_mdp_snapshot()
887 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].sblk->dither.len, in dpu_kms_mdp_snapshot()
888 base + cat->pingpong[i].sblk->dither.base, in dpu_kms_mdp_snapshot()
889 "%s_%s", cat->pingpong[i].name, in dpu_kms_mdp_snapshot()
890 cat->pingpong[i].sblk->dither.name); in dpu_kms_mdp_snapshot()
893 /* dump SSPP sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
894 for (i = 0; i < cat->sspp_count; i++) { in dpu_kms_mdp_snapshot()
895 base = dpu_kms->mmio + cat->sspp[i].base; in dpu_kms_mdp_snapshot()
896 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, base, cat->sspp[i].name); in dpu_kms_mdp_snapshot()
898 if (cat->sspp[i].sblk && cat->sspp[i].sblk->scaler_blk.len > 0) in dpu_kms_mdp_snapshot()
899 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->scaler_blk.len, in dpu_kms_mdp_snapshot()
900 base + cat->sspp[i].sblk->scaler_blk.base, in dpu_kms_mdp_snapshot()
901 "%s_%s", cat->sspp[i].name, in dpu_kms_mdp_snapshot()
902 cat->sspp[i].sblk->scaler_blk.name); in dpu_kms_mdp_snapshot()
904 if (cat->sspp[i].sblk && cat->sspp[i].sblk->csc_blk.len > 0) in dpu_kms_mdp_snapshot()
905 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->csc_blk.len, in dpu_kms_mdp_snapshot()
906 base + cat->sspp[i].sblk->csc_blk.base, in dpu_kms_mdp_snapshot()
907 "%s_%s", cat->sspp[i].name, in dpu_kms_mdp_snapshot()
908 cat->sspp[i].sblk->csc_blk.name); in dpu_kms_mdp_snapshot()
911 /* dump LM sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
912 for (i = 0; i < cat->mixer_count; i++) in dpu_kms_mdp_snapshot()
913 msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len, in dpu_kms_mdp_snapshot()
914 dpu_kms->mmio + cat->mixer[i].base, cat->mixer[i].name); in dpu_kms_mdp_snapshot()
916 /* dump WB sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
917 for (i = 0; i < cat->wb_count; i++) in dpu_kms_mdp_snapshot()
918 msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, in dpu_kms_mdp_snapshot()
919 dpu_kms->mmio + cat->wb[i].base, cat->wb[i].name); in dpu_kms_mdp_snapshot()
921 if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { in dpu_kms_mdp_snapshot()
923 dpu_kms->mmio + cat->mdp[0].base, "top"); in dpu_kms_mdp_snapshot()
924 msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - MDP_PERIPH_TOP0_END, in dpu_kms_mdp_snapshot()
925 dpu_kms->mmio + cat->mdp[0].base + MDP_PERIPH_TOP0_END, "top_2"); in dpu_kms_mdp_snapshot()
927 msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, in dpu_kms_mdp_snapshot()
928 dpu_kms->mmio + cat->mdp[0].base, "top"); in dpu_kms_mdp_snapshot()
931 /* dump DSC sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
932 for (i = 0; i < cat->dsc_count; i++) { in dpu_kms_mdp_snapshot()
933 base = dpu_kms->mmio + cat->dsc[i].base; in dpu_kms_mdp_snapshot()
934 msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base, cat->dsc[i].name); in dpu_kms_mdp_snapshot()
936 if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) { in dpu_kms_mdp_snapshot()
937 struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc; in dpu_kms_mdp_snapshot()
938 struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl; in dpu_kms_mdp_snapshot()
941 cat->dsc[i].name, enc.name); in dpu_kms_mdp_snapshot()
943 cat->dsc[i].name, ctl.name); in dpu_kms_mdp_snapshot()
947 if (cat->cdm) in dpu_kms_mdp_snapshot()
948 msm_disp_snapshot_add_block(disp_state, cat->cdm->len, in dpu_kms_mdp_snapshot()
949 dpu_kms->mmio + cat->cdm->base, cat->cdm->name); in dpu_kms_mdp_snapshot()
951 pm_runtime_put_sync(&dpu_kms->pdev->dev); in dpu_kms_mdp_snapshot()
980 if (!dpu_kms->base.aspace) in _dpu_kms_mmu_destroy()
983 mmu = dpu_kms->base.aspace->mmu; in _dpu_kms_mmu_destroy()
985 mmu->funcs->detach(mmu); in _dpu_kms_mmu_destroy()
986 msm_gem_address_space_put(dpu_kms->base.aspace); in _dpu_kms_mmu_destroy()
988 dpu_kms->base.aspace = NULL; in _dpu_kms_mmu_destroy()
995 aspace = msm_kms_init_aspace(dpu_kms->dev); in _dpu_kms_mmu_init()
999 dpu_kms->base.aspace = aspace; in _dpu_kms_mmu_init()
1008 clk = msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, clock_name); in dpu_kms_get_clk_rate()
1021 int i, rc = -EINVAL; in dpu_kms_hw_init()
1031 dev = dpu_kms->dev; in dpu_kms_hw_init()
1033 dev->mode_config.cursor_width = 512; in dpu_kms_hw_init()
1034 dev->mode_config.cursor_height = 512; in dpu_kms_hw_init()
1040 atomic_set(&dpu_kms->bandwidth_ref, 0); in dpu_kms_hw_init()
1042 rc = pm_runtime_resume_and_get(&dpu_kms->pdev->dev); in dpu_kms_hw_init()
1046 core_rev = readl_relaxed(dpu_kms->mmio + 0x0); in dpu_kms_hw_init()
1050 dpu_kms->catalog = of_device_get_match_data(dev->dev); in dpu_kms_hw_init()
1051 if (!dpu_kms->catalog) { in dpu_kms_hw_init()
1053 rc = -EINVAL; in dpu_kms_hw_init()
1067 dpu_kms->mdss = msm_mdss_get_mdss_data(dpu_kms->pdev->dev.parent); in dpu_kms_hw_init()
1068 if (IS_ERR(dpu_kms->mdss)) { in dpu_kms_hw_init()
1069 rc = PTR_ERR(dpu_kms->mdss); in dpu_kms_hw_init()
1074 if (!dpu_kms->mdss) { in dpu_kms_hw_init()
1075 rc = -EINVAL; in dpu_kms_hw_init()
1080 rc = dpu_rm_init(dev, &dpu_kms->rm, dpu_kms->catalog, dpu_kms->mdss, dpu_kms->mmio); in dpu_kms_hw_init()
1086 dpu_kms->hw_mdp = dpu_hw_mdptop_init(dev, in dpu_kms_hw_init()
1087 dpu_kms->catalog->mdp, in dpu_kms_hw_init()
1088 dpu_kms->mmio, in dpu_kms_hw_init()
1089 dpu_kms->catalog); in dpu_kms_hw_init()
1090 if (IS_ERR(dpu_kms->hw_mdp)) { in dpu_kms_hw_init()
1091 rc = PTR_ERR(dpu_kms->hw_mdp); in dpu_kms_hw_init()
1093 dpu_kms->hw_mdp = NULL; in dpu_kms_hw_init()
1097 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { in dpu_kms_hw_init()
1099 const struct dpu_vbif_cfg *vbif = &dpu_kms->catalog->vbif[i]; in dpu_kms_hw_init()
1101 hw = dpu_hw_vbif_init(dev, vbif, dpu_kms->vbif[vbif->id]); in dpu_kms_hw_init()
1104 DPU_ERROR("failed to init vbif %d: %d\n", vbif->id, rc); in dpu_kms_hw_init()
1108 dpu_kms->hw_vbif[vbif->id] = hw; in dpu_kms_hw_init()
1118 rc = dpu_core_perf_init(&dpu_kms->perf, dpu_kms->catalog->perf, max_core_clk_rate); in dpu_kms_hw_init()
1124 dpu_kms->hw_intr = dpu_hw_intr_init(dev, dpu_kms->mmio, dpu_kms->catalog); in dpu_kms_hw_init()
1125 if (IS_ERR(dpu_kms->hw_intr)) { in dpu_kms_hw_init()
1126 rc = PTR_ERR(dpu_kms->hw_intr); in dpu_kms_hw_init()
1128 dpu_kms->hw_intr = NULL; in dpu_kms_hw_init()
1132 dev->mode_config.min_width = 0; in dpu_kms_hw_init()
1133 dev->mode_config.min_height = 0; in dpu_kms_hw_init()
1139 dev->mode_config.max_width = in dpu_kms_hw_init()
1140 dpu_kms->catalog->caps->max_mixer_width * 2; in dpu_kms_hw_init()
1141 dev->mode_config.max_height = 4096; in dpu_kms_hw_init()
1143 dev->max_vblank_count = 0xffffffff; in dpu_kms_hw_init()
1144 /* Disable vblank irqs aggressively for power-saving */ in dpu_kms_hw_init()
1145 dev->vblank_disable_immediate = true; in dpu_kms_hw_init()
1159 pm_runtime_put_sync(&dpu_kms->pdev->dev); in dpu_kms_hw_init()
1164 pm_runtime_put_sync(&dpu_kms->pdev->dev); in dpu_kms_hw_init()
1173 struct msm_drm_private *priv = ddev->dev_private; in dpu_kms_init()
1174 struct device *dev = ddev->dev; in dpu_kms_init()
1176 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); in dpu_kms_init()
1187 ret = msm_kms_init(&dpu_kms->base, &kms_funcs); in dpu_kms_init()
1192 dpu_kms->dev = ddev; in dpu_kms_init()
1194 pm_runtime_enable(&pdev->dev); in dpu_kms_init()
1195 dpu_kms->rpm_enabled = true; in dpu_kms_init()
1202 struct device *dev = &pdev->dev; in dpu_dev_probe()
1209 return -ENOMEM; in dpu_dev_probe()
1211 dpu_kms->pdev = pdev; in dpu_dev_probe()
1218 if (ret && ret != -ENODEV) in dpu_dev_probe()
1221 ret = devm_clk_bulk_get_all(&pdev->dev, &dpu_kms->clocks); in dpu_dev_probe()
1225 dpu_kms->num_clocks = ret; in dpu_dev_probe()
1231 dpu_kms->base.irq = irq; in dpu_dev_probe()
1233 dpu_kms->mmio = msm_ioremap(pdev, "mdp"); in dpu_dev_probe()
1234 if (IS_ERR(dpu_kms->mmio)) { in dpu_dev_probe()
1235 ret = PTR_ERR(dpu_kms->mmio); in dpu_dev_probe()
1237 dpu_kms->mmio = NULL; in dpu_dev_probe()
1240 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); in dpu_dev_probe()
1242 dpu_kms->vbif[VBIF_RT] = msm_ioremap(pdev, "vbif"); in dpu_dev_probe()
1243 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { in dpu_dev_probe()
1244 ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]); in dpu_dev_probe()
1246 dpu_kms->vbif[VBIF_RT] = NULL; in dpu_dev_probe()
1250 dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(pdev, "vbif_nrt"); in dpu_dev_probe()
1251 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { in dpu_dev_probe()
1252 dpu_kms->vbif[VBIF_NRT] = NULL; in dpu_dev_probe()
1260 return msm_drv_probe(&pdev->dev, dpu_kms_init, &dpu_kms->base); in dpu_dev_probe()
1265 component_master_del(&pdev->dev, &msm_drm_ops); in dpu_dev_remove()
1273 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); in dpu_runtime_suspend()
1277 clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks); in dpu_runtime_suspend()
1279 for (i = 0; i < dpu_kms->num_paths; i++) in dpu_runtime_suspend()
1280 icc_set_bw(dpu_kms->path[i], 0, 0); in dpu_runtime_suspend()
1287 int rc = -1; in dpu_runtime_resume()
1290 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); in dpu_runtime_resume()
1294 ddev = dpu_kms->dev; in dpu_runtime_resume()
1296 rc = clk_bulk_prepare_enable(dpu_kms->num_clocks, dpu_kms->clocks); in dpu_runtime_resume()
1319 { .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, },
1320 { .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, },
1321 { .compatible = "qcom,sdm670-dpu", .data = &dpu_sdm670_cfg, },
1322 { .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, },
1323 { .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, },
1324 { .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, },
1325 { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
1326 { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
1327 { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
1328 { .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
1329 { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
1330 { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
1331 { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
1332 { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
1333 { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
1334 { .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
1335 { .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
1336 { .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, },