disp/dpu1/dpu_hw_wb.c

15 #define WB_DST_FORMAT                         0x000
16 #define WB_DST_OP_MODE                        0x004
17 #define WB_DST_PACK_PATTERN                   0x008
18 #define WB_DST0_ADDR                          0x00C
19 #define WB_DST1_ADDR                          0x010
20 #define WB_DST2_ADDR                          0x014
21 #define WB_DST3_ADDR                          0x018
22 #define WB_DST_YSTRIDE0                       0x01C
23 #define WB_DST_YSTRIDE1                       0x020
24 #define WB_DST_YSTRIDE1                       0x020
25 #define WB_DST_DITHER_BITDEPTH                0x024
26 #define WB_DST_MATRIX_ROW0                    0x030
27 #define WB_DST_MATRIX_ROW1                    0x034
28 #define WB_DST_MATRIX_ROW2                    0x038
29 #define WB_DST_MATRIX_ROW3                    0x03C
30 #define WB_DST_WRITE_CONFIG                   0x048
31 #define WB_ROTATION_DNSCALER                  0x050
32 #define WB_ROTATOR_PIPE_DOWNSCALER            0x054
33 #define WB_N16_INIT_PHASE_X_C03               0x060
34 #define WB_N16_INIT_PHASE_X_C12               0x064
35 #define WB_N16_INIT_PHASE_Y_C03               0x068
36 #define WB_N16_INIT_PHASE_Y_C12               0x06C
37 #define WB_OUT_SIZE                           0x074
38 #define WB_ALPHA_X_VALUE                      0x078
39 #define WB_DANGER_LUT                         0x084
40 #define WB_SAFE_LUT                           0x088
41 #define WB_QOS_CTRL                           0x090
42 #define WB_CREQ_LUT_0                         0x098
43 #define WB_CREQ_LUT_1                         0x09C
44 #define WB_UBWC_STATIC_CTRL                   0x144
45 #define WB_MUX                                0x150
46 #define WB_CROP_CTRL                          0x154
47 #define WB_CROP_OFFSET                        0x158
48 #define WB_CLK_CTRL                           0x178
49 #define WB_CSC_BASE                           0x260
50 #define WB_DST_ADDR_SW_STATUS                 0x2B0
51 #define WB_CDP_CNTL                           0x2B4
52 #define WB_OUT_IMAGE_SIZE                     0x2C0
53 #define WB_OUT_XY                             0x2C4
60 	DPU_REG_WRITE(c, WB_DST0_ADDR, data->dest.plane_addr[0]);  in dpu_hw_wb_setup_outaddress()
72 	u32 write_config = 0;  in dpu_hw_wb_setup_format()
73 	u32 opmode = 0;  in dpu_hw_wb_setup_format()
74 	u32 dst_addr_sw = 0;  in dpu_hw_wb_setup_format()
83 		(fmt->bits[C0_G_Y] << 0);  in dpu_hw_wb_setup_format()
98 		(fmt->element[0] << 0);  in dpu_hw_wb_setup_format()
105 	ystride0 = data->dest.plane_pitch[0] |  in dpu_hw_wb_setup_format()
115 	DPU_REG_WRITE(c, WB_ALPHA_X_VALUE, 0xFF);  in dpu_hw_wb_setup_format()
132 	out_xy = 0;  in dpu_hw_wb_roi()
174 	mux_cfg &= ~0xf;  in dpu_hw_wb_bind_pingpong_blk()
177 		mux_cfg |= (pp - PINGPONG_0) & 0x7;  in dpu_hw_wb_bind_pingpong_blk()
179 		mux_cfg |= 0xf;  in dpu_hw_wb_bind_pingpong_blk()
188 		.bit_off = 0  in dpu_hw_wb_setup_clk_force_ctrl()