2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
40 	struct dpu_hw_blk_reg_map *c;  in dpu_hw_clear_errors()  local
45 	c = &vbif->hw;  in dpu_hw_clear_errors()
46 	pnd = DPU_REG_READ(c, VBIF_XIN_PND_ERR);  in dpu_hw_clear_errors()
47 	src = DPU_REG_READ(c, VBIF_XIN_SRC_ERR);  in dpu_hw_clear_errors()
54 	DPU_REG_WRITE(c, VBIF_XIN_CLR_ERR, pnd | src);  in dpu_hw_clear_errors()
60 	struct dpu_hw_blk_reg_map *c;  in dpu_hw_set_mem_type()  local
66 	 * Assume 4 bits per bit field, 8 fields per 32-bit register so  in dpu_hw_set_mem_type()
72 	c = &vbif->hw;  in dpu_hw_set_mem_type()
80 	bit_off = (xin_id & 0x7) * 4;  in dpu_hw_set_mem_type()
81 	reg_val = DPU_REG_READ(c, reg_off);  in dpu_hw_set_mem_type()
84 	DPU_REG_WRITE(c, reg_off, reg_val);  in dpu_hw_set_mem_type()
90 	struct dpu_hw_blk_reg_map *c = &vbif->hw;  in dpu_hw_set_limit_conf()  local
100 	reg_off += (xin_id / 4) * 4;  in dpu_hw_set_limit_conf()
101 	bit_off = (xin_id % 4) * 8;  in dpu_hw_set_limit_conf()
102 	reg_val = DPU_REG_READ(c, reg_off);  in dpu_hw_set_limit_conf()
105 	DPU_REG_WRITE(c, reg_off, reg_val);  in dpu_hw_set_limit_conf()
111 	struct dpu_hw_blk_reg_map *c = &vbif->hw;  in dpu_hw_get_limit_conf()  local
122 	reg_off += (xin_id / 4) * 4;  in dpu_hw_get_limit_conf()
123 	bit_off = (xin_id % 4) * 8;  in dpu_hw_get_limit_conf()
124 	reg_val = DPU_REG_READ(c, reg_off);  in dpu_hw_get_limit_conf()
133 	struct dpu_hw_blk_reg_map *c = &vbif->hw;  in dpu_hw_set_halt_ctrl()  local
136 	reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL0);  in dpu_hw_set_halt_ctrl()
143 	DPU_REG_WRITE(c, VBIF_XIN_HALT_CTRL0, reg_val);  in dpu_hw_set_halt_ctrl()
149 	struct dpu_hw_blk_reg_map *c = &vbif->hw;  in dpu_hw_get_halt_ctrl()  local
152 	reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL1);  in dpu_hw_get_halt_ctrl()
160 	struct dpu_hw_blk_reg_map *c;  in dpu_hw_set_qos_remap()  local
166 	c = &vbif->hw;  in dpu_hw_set_qos_remap()
169 	reg_high = ((xin_id & 0x8) >> 3) * 4 + (level * 8);  in dpu_hw_set_qos_remap()
170 	reg_shift = (xin_id & 0x7) * 4;  in dpu_hw_set_qos_remap()
172 	reg_val = DPU_REG_READ(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high);  in dpu_hw_set_qos_remap()
173 	reg_val_lvl = DPU_REG_READ(c, reg_lvl + reg_high);  in dpu_hw_set_qos_remap()
183 	DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val);  in dpu_hw_set_qos_remap()
184 	DPU_REG_WRITE(c, reg_lvl + reg_high, reg_val_lvl);  in dpu_hw_set_qos_remap()
189 	struct dpu_hw_blk_reg_map *c;  in dpu_hw_set_write_gather_en()  local
195 	c = &vbif->hw;  in dpu_hw_set_write_gather_en()
197 	reg_val = DPU_REG_READ(c, VBIF_WRITE_GATHER_EN);  in dpu_hw_set_write_gather_en()
199 	DPU_REG_WRITE(c, VBIF_WRITE_GATHER_EN, reg_val);  in dpu_hw_set_write_gather_en()
220 	struct dpu_hw_vbif *c;  in dpu_hw_vbif_init()  local
222 	c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);  in dpu_hw_vbif_init()
223 	if (!c)  in dpu_hw_vbif_init()
226 	c->hw.blk_addr = addr + cfg->base;  in dpu_hw_vbif_init()
227 	c->hw.log_mask = DPU_DBG_MASK_VBIF;  in dpu_hw_vbif_init()
232 	c->idx = cfg->id;  in dpu_hw_vbif_init()
233 	c->cap = cfg;  in dpu_hw_vbif_init()
234 	_setup_vbif_ops(&c->ops, c->cap->features);  in dpu_hw_vbif_init()
238 	return c;  in dpu_hw_vbif_init()