Lines Matching +full:0 +full:x00000016
16 #define CDM_CSC_10_OPMODE 0x000
17 #define CDM_CSC_10_BASE 0x004
19 #define CDM_CDWN2_OP_MODE 0x100
20 #define CDM_CDWN2_CLAMP_OUT 0x104
21 #define CDM_CDWN2_PARAMS_3D_0 0x108
22 #define CDM_CDWN2_PARAMS_3D_1 0x10C
23 #define CDM_CDWN2_COEFF_COSITE_H_0 0x110
24 #define CDM_CDWN2_COEFF_COSITE_H_1 0x114
25 #define CDM_CDWN2_COEFF_COSITE_H_2 0x118
26 #define CDM_CDWN2_COEFF_OFFSITE_H_0 0x11C
27 #define CDM_CDWN2_COEFF_OFFSITE_H_1 0x120
28 #define CDM_CDWN2_COEFF_OFFSITE_H_2 0x124
29 #define CDM_CDWN2_COEFF_COSITE_V 0x128
30 #define CDM_CDWN2_COEFF_OFFSITE_V 0x12C
31 #define CDM_CDWN2_OUT_SIZE 0x130
33 #define CDM_HDMI_PACK_OP_MODE 0x200
34 #define CDM_CSC_10_MATRIX_COEFF_0 0x004
36 #define CDM_MUX 0x224
39 #define CDM_CDWN2_OP_MODE_EN BIT(0)
47 #define CDM_CSC10_OP_MODE_EN BIT(0)
52 #define CDM_HDMI_PACK_OP_MODE_EN BIT(0)
58 static u32 cosite_h_coeff[] = {0x00000016, 0x000001cc, 0x0100009e};
63 static u32 offsite_h_coeff[] = {0x000b0005, 0x01db01eb, 0x00e40046};
68 static u32 cosite_v_coeff[] = {0x00080004};
72 static u32 offsite_v_coeff[] = {0x00060002};
82 opmode = 0; in dpu_hw_cdm_setup_cdwn()
99 cosite_h_coeff[0]); in dpu_hw_cdm_setup_cdwn()
109 offsite_h_coeff[0]); in dpu_hw_cdm_setup_cdwn()
140 cosite_v_coeff[0]); in dpu_hw_cdm_setup_cdwn()
148 offsite_v_coeff[0]); in dpu_hw_cdm_setup_cdwn()
162 out_size = (cfg->output_width & 0xFFFF) | ((cfg->output_height & 0xFFFF) << 16); in dpu_hw_cdm_setup_cdwn()
165 DPU_REG_WRITE(c, CDM_CDWN2_CLAMP_OUT, ((0x3FF << 16) | 0x0)); in dpu_hw_cdm_setup_cdwn()
167 return 0; in dpu_hw_cdm_setup_cdwn()
174 u32 opmode = 0; in dpu_hw_cdm_enable()
175 u32 csc = 0; in dpu_hw_cdm_enable()
204 return 0; in dpu_hw_cdm_enable()
215 mux_cfg &= ~0xf; in dpu_hw_cdm_bind_pingpong_blk()
218 mux_cfg |= (pp - PINGPONG_0) & 0x7; in dpu_hw_cdm_bind_pingpong_blk()
220 mux_cfg |= 0xf; in dpu_hw_cdm_bind_pingpong_blk()