Lines Matching +full:gpu +full:- +full:id
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
99 list_add_tail(&obj->node, &a6xx_state->objs); in state_kcalloc()
100 return &obj->data; in state_kcalloc()
114 * Allocate 1MB for the crashdumper scratch region - 8k for the script and
118 #define A6XX_CD_DATA_SIZE (SZ_1M - 8192)
120 static int a6xx_crashdumper_init(struct msm_gpu *gpu, in a6xx_crashdumper_init() argument
123 dumper->ptr = msm_gem_kernel_new(gpu->dev, in a6xx_crashdumper_init()
124 SZ_1M, MSM_BO_WC, gpu->aspace, in a6xx_crashdumper_init()
125 &dumper->bo, &dumper->iova); in a6xx_crashdumper_init()
127 if (!IS_ERR(dumper->ptr)) in a6xx_crashdumper_init()
128 msm_gem_object_set_name(dumper->bo, "crashdump"); in a6xx_crashdumper_init()
130 return PTR_ERR_OR_ZERO(dumper->ptr); in a6xx_crashdumper_init()
133 static int a6xx_crashdumper_run(struct msm_gpu *gpu, in a6xx_crashdumper_run() argument
136 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_crashdumper_run()
141 if (IS_ERR_OR_NULL(dumper->ptr)) in a6xx_crashdumper_run()
142 return -EINVAL; in a6xx_crashdumper_run()
144 if (!a6xx_gmu_sptprac_is_on(&a6xx_gpu->gmu)) in a6xx_crashdumper_run()
145 return -EINVAL; in a6xx_crashdumper_run()
150 gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE, dumper->iova); in a6xx_crashdumper_run()
152 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); in a6xx_crashdumper_run()
154 ret = gpu_poll_timeout(gpu, REG_A6XX_CP_CRASH_DUMP_STATUS, val, in a6xx_crashdumper_run()
157 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run()
163 static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset, in debugbus_read() argument
169 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_A, reg); in debugbus_read()
170 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_B, reg); in debugbus_read()
171 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_C, reg); in debugbus_read()
172 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_D, reg); in debugbus_read()
177 data[0] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2); in debugbus_read()
178 data[1] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1); in debugbus_read()
211 static int vbif_debugbus_read(struct msm_gpu *gpu, u32 ctrl0, u32 ctrl1, in vbif_debugbus_read() argument
216 gpu_write(gpu, ctrl0, reg); in vbif_debugbus_read()
219 gpu_write(gpu, ctrl1, i); in vbif_debugbus_read()
220 data[i] = gpu_read(gpu, REG_A6XX_VBIF_TEST_BUS_OUT); in vbif_debugbus_read()
235 static void a6xx_get_vbif_debugbus_block(struct msm_gpu *gpu, in a6xx_get_vbif_debugbus_block() argument
242 obj->data = state_kcalloc(a6xx_state, VBIF_DEBUGBUS_BLOCK_SIZE, in a6xx_get_vbif_debugbus_block()
244 if (!obj->data) in a6xx_get_vbif_debugbus_block()
247 obj->handle = NULL; in a6xx_get_vbif_debugbus_block()
250 clk = gpu_read(gpu, REG_A6XX_VBIF_CLKON); in a6xx_get_vbif_debugbus_block()
253 gpu_write(gpu, REG_A6XX_VBIF_CLKON, in a6xx_get_vbif_debugbus_block()
257 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS1_CTRL0, 0); in a6xx_get_vbif_debugbus_block()
260 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS_OUT_CTRL, 1); in a6xx_get_vbif_debugbus_block()
262 ptr = obj->data; in a6xx_get_vbif_debugbus_block()
265 ptr += vbif_debugbus_read(gpu, in a6xx_get_vbif_debugbus_block()
271 ptr += vbif_debugbus_read(gpu, in a6xx_get_vbif_debugbus_block()
277 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS2_CTRL0, 0); in a6xx_get_vbif_debugbus_block()
280 ptr += vbif_debugbus_read(gpu, in a6xx_get_vbif_debugbus_block()
286 gpu_write(gpu, REG_A6XX_VBIF_CLKON, clk); in a6xx_get_vbif_debugbus_block()
289 static void a6xx_get_debugbus_block(struct msm_gpu *gpu, in a6xx_get_debugbus_block() argument
297 obj->data = state_kcalloc(a6xx_state, block->count, sizeof(u64)); in a6xx_get_debugbus_block()
298 if (!obj->data) in a6xx_get_debugbus_block()
301 obj->handle = block; in a6xx_get_debugbus_block()
303 for (ptr = obj->data, i = 0; i < block->count; i++) in a6xx_get_debugbus_block()
304 ptr += debugbus_read(gpu, block->id, i, ptr); in a6xx_get_debugbus_block()
315 obj->data = state_kcalloc(a6xx_state, block->count, sizeof(u64)); in a6xx_get_cx_debugbus_block()
316 if (!obj->data) in a6xx_get_cx_debugbus_block()
319 obj->handle = block; in a6xx_get_cx_debugbus_block()
321 for (ptr = obj->data, i = 0; i < block->count; i++) in a6xx_get_cx_debugbus_block()
322 ptr += cx_debugbus_read(cxdbg, block->id, i, ptr); in a6xx_get_cx_debugbus_block()
325 static void a6xx_get_debugbus(struct msm_gpu *gpu, in a6xx_get_debugbus() argument
334 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_CNTLT, in a6xx_get_debugbus()
337 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_CNTLM, in a6xx_get_debugbus()
340 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0, 0); in a6xx_get_debugbus()
341 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1, 0); in a6xx_get_debugbus()
342 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2, 0); in a6xx_get_debugbus()
343 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3, 0); in a6xx_get_debugbus()
345 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0, 0x76543210); in a6xx_get_debugbus()
346 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1, 0xFEDCBA98); in a6xx_get_debugbus()
348 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0, 0); in a6xx_get_debugbus()
349 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1, 0); in a6xx_get_debugbus()
350 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2, 0); in a6xx_get_debugbus()
351 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3, 0); in a6xx_get_debugbus()
353 /* Set up the CX debug bus - it lives elsewhere in the system so do a in a6xx_get_debugbus()
356 res = platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM, in a6xx_get_debugbus()
360 cxdbg = ioremap(res->start, resource_size(res)); in a6xx_get_debugbus()
386 (a6xx_has_gbif(to_adreno_gpu(gpu)) ? 1 : 0); in a6xx_get_debugbus()
388 if (adreno_is_a650_family(to_adreno_gpu(gpu))) in a6xx_get_debugbus()
391 a6xx_state->debugbus = state_kcalloc(a6xx_state, nr_debugbus_blocks, in a6xx_get_debugbus()
392 sizeof(*a6xx_state->debugbus)); in a6xx_get_debugbus()
394 if (a6xx_state->debugbus) { in a6xx_get_debugbus()
398 a6xx_get_debugbus_block(gpu, in a6xx_get_debugbus()
401 &a6xx_state->debugbus[i]); in a6xx_get_debugbus()
403 a6xx_state->nr_debugbus = ARRAY_SIZE(a6xx_debugbus_blocks); in a6xx_get_debugbus()
406 * GBIF has same debugbus as of other GPU blocks, fall back to in a6xx_get_debugbus()
407 * default path if GPU uses GBIF, also GBIF uses exactly same in a6xx_get_debugbus()
408 * ID as of VBIF. in a6xx_get_debugbus()
410 if (a6xx_has_gbif(to_adreno_gpu(gpu))) { in a6xx_get_debugbus()
411 a6xx_get_debugbus_block(gpu, a6xx_state, in a6xx_get_debugbus()
413 &a6xx_state->debugbus[i]); in a6xx_get_debugbus()
415 a6xx_state->nr_debugbus += 1; in a6xx_get_debugbus()
419 if (adreno_is_a650_family(to_adreno_gpu(gpu))) { in a6xx_get_debugbus()
421 a6xx_get_debugbus_block(gpu, in a6xx_get_debugbus()
424 &a6xx_state->debugbus[i]); in a6xx_get_debugbus()
429 if (!a6xx_has_gbif(to_adreno_gpu(gpu))) { in a6xx_get_debugbus()
430 a6xx_state->vbif_debugbus = in a6xx_get_debugbus()
432 sizeof(*a6xx_state->vbif_debugbus)); in a6xx_get_debugbus()
434 if (a6xx_state->vbif_debugbus) in a6xx_get_debugbus()
435 a6xx_get_vbif_debugbus_block(gpu, a6xx_state, in a6xx_get_debugbus()
436 a6xx_state->vbif_debugbus); in a6xx_get_debugbus()
440 a6xx_state->cx_debugbus = in a6xx_get_debugbus()
443 sizeof(*a6xx_state->cx_debugbus)); in a6xx_get_debugbus()
445 if (a6xx_state->cx_debugbus) { in a6xx_get_debugbus()
452 &a6xx_state->cx_debugbus[i]); in a6xx_get_debugbus()
454 a6xx_state->nr_cx_debugbus = in a6xx_get_debugbus()
462 #define RANGE(reg, a) ((reg)[(a) + 1] - (reg)[(a)] + 1)
465 static void a6xx_get_dbgahb_cluster(struct msm_gpu *gpu, in a6xx_get_dbgahb_cluster() argument
471 u64 *in = dumper->ptr; in a6xx_get_dbgahb_cluster()
472 u64 out = dumper->iova + A6XX_CD_DATA_OFFSET; in a6xx_get_dbgahb_cluster()
480 (dbgahb->statetype + i * 2) << 8); in a6xx_get_dbgahb_cluster()
482 for (j = 0; j < dbgahb->count; j += 2) { in a6xx_get_dbgahb_cluster()
483 int count = RANGE(dbgahb->registers, j); in a6xx_get_dbgahb_cluster()
485 dbgahb->registers[j] - (dbgahb->base >> 2); in a6xx_get_dbgahb_cluster()
503 if (a6xx_crashdumper_run(gpu, dumper)) in a6xx_get_dbgahb_cluster()
506 obj->handle = dbgahb; in a6xx_get_dbgahb_cluster()
507 obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET, in a6xx_get_dbgahb_cluster()
511 static void a6xx_get_dbgahb_clusters(struct msm_gpu *gpu, in a6xx_get_dbgahb_clusters() argument
517 a6xx_state->dbgahb_clusters = state_kcalloc(a6xx_state, in a6xx_get_dbgahb_clusters()
519 sizeof(*a6xx_state->dbgahb_clusters)); in a6xx_get_dbgahb_clusters()
521 if (!a6xx_state->dbgahb_clusters) in a6xx_get_dbgahb_clusters()
524 a6xx_state->nr_dbgahb_clusters = ARRAY_SIZE(a6xx_dbgahb_clusters); in a6xx_get_dbgahb_clusters()
527 a6xx_get_dbgahb_cluster(gpu, a6xx_state, in a6xx_get_dbgahb_clusters()
529 &a6xx_state->dbgahb_clusters[i], dumper); in a6xx_get_dbgahb_clusters()
533 static void a6xx_get_cluster(struct msm_gpu *gpu, in a6xx_get_cluster() argument
539 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_get_cluster()
540 u64 *in = dumper->ptr; in a6xx_get_cluster()
541 u64 out = dumper->iova + A6XX_CD_DATA_OFFSET; in a6xx_get_cluster()
544 u32 id = cluster->id; in a6xx_get_cluster() local
548 cluster->registers == a660_fe_cluster) in a6xx_get_cluster()
552 cluster->registers == a6xx_ps_cluster) in a6xx_get_cluster()
553 id = CLUSTER_VPC_PS; in a6xx_get_cluster()
556 if (cluster->sel_reg) in a6xx_get_cluster()
557 in += CRASHDUMP_WRITE(in, cluster->sel_reg, cluster->sel_val); in a6xx_get_cluster()
563 (id << 8) | (i << 4) | i); in a6xx_get_cluster()
565 for (j = 0; j < cluster->count; j += 2) { in a6xx_get_cluster()
566 int count = RANGE(cluster->registers, j); in a6xx_get_cluster()
568 in += CRASHDUMP_READ(in, cluster->registers[j], in a6xx_get_cluster()
585 if (a6xx_crashdumper_run(gpu, dumper)) in a6xx_get_cluster()
588 obj->handle = cluster; in a6xx_get_cluster()
589 obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET, in a6xx_get_cluster()
593 static void a6xx_get_clusters(struct msm_gpu *gpu, in a6xx_get_clusters() argument
599 a6xx_state->clusters = state_kcalloc(a6xx_state, in a6xx_get_clusters()
600 ARRAY_SIZE(a6xx_clusters), sizeof(*a6xx_state->clusters)); in a6xx_get_clusters()
602 if (!a6xx_state->clusters) in a6xx_get_clusters()
605 a6xx_state->nr_clusters = ARRAY_SIZE(a6xx_clusters); in a6xx_get_clusters()
608 a6xx_get_cluster(gpu, a6xx_state, &a6xx_clusters[i], in a6xx_get_clusters()
609 &a6xx_state->clusters[i], dumper); in a6xx_get_clusters()
613 static void a6xx_get_shader_block(struct msm_gpu *gpu, in a6xx_get_shader_block() argument
619 u64 *in = dumper->ptr; in a6xx_get_shader_block()
620 size_t datasize = block->size * A6XX_NUM_SHADER_BANKS * sizeof(u32); in a6xx_get_shader_block()
628 (block->type << 8) | i); in a6xx_get_shader_block()
631 block->size, dumper->iova + A6XX_CD_DATA_OFFSET); in a6xx_get_shader_block()
636 if (a6xx_crashdumper_run(gpu, dumper)) in a6xx_get_shader_block()
639 obj->handle = block; in a6xx_get_shader_block()
640 obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET, in a6xx_get_shader_block()
644 static void a6xx_get_shaders(struct msm_gpu *gpu, in a6xx_get_shaders() argument
650 a6xx_state->shaders = state_kcalloc(a6xx_state, in a6xx_get_shaders()
651 ARRAY_SIZE(a6xx_shader_blocks), sizeof(*a6xx_state->shaders)); in a6xx_get_shaders()
653 if (!a6xx_state->shaders) in a6xx_get_shaders()
656 a6xx_state->nr_shaders = ARRAY_SIZE(a6xx_shader_blocks); in a6xx_get_shaders()
659 a6xx_get_shader_block(gpu, a6xx_state, &a6xx_shader_blocks[i], in a6xx_get_shaders()
660 &a6xx_state->shaders[i], dumper); in a6xx_get_shaders()
664 static void a6xx_get_crashdumper_hlsq_registers(struct msm_gpu *gpu, in a6xx_get_crashdumper_hlsq_registers() argument
671 u64 *in = dumper->ptr; in a6xx_get_crashdumper_hlsq_registers()
672 u64 out = dumper->iova + A6XX_CD_DATA_OFFSET; in a6xx_get_crashdumper_hlsq_registers()
675 in += CRASHDUMP_WRITE(in, REG_A6XX_HLSQ_DBG_READ_SEL, regs->val1); in a6xx_get_crashdumper_hlsq_registers()
677 for (i = 0; i < regs->count; i += 2) { in a6xx_get_crashdumper_hlsq_registers()
678 u32 count = RANGE(regs->registers, i); in a6xx_get_crashdumper_hlsq_registers()
680 regs->registers[i] - (regs->val0 >> 2); in a6xx_get_crashdumper_hlsq_registers()
693 if (a6xx_crashdumper_run(gpu, dumper)) in a6xx_get_crashdumper_hlsq_registers()
696 obj->handle = regs; in a6xx_get_crashdumper_hlsq_registers()
697 obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET, in a6xx_get_crashdumper_hlsq_registers()
702 static void a6xx_get_crashdumper_registers(struct msm_gpu *gpu, in a6xx_get_crashdumper_registers() argument
709 u64 *in = dumper->ptr; in a6xx_get_crashdumper_registers()
710 u64 out = dumper->iova + A6XX_CD_DATA_OFFSET; in a6xx_get_crashdumper_registers()
714 if (!adreno_is_a660_family(to_adreno_gpu(gpu)) && in a6xx_get_crashdumper_registers()
715 (regs->registers == a660_registers)) in a6xx_get_crashdumper_registers()
719 if (regs->val0) in a6xx_get_crashdumper_registers()
720 in += CRASHDUMP_WRITE(in, regs->val0, regs->val1); in a6xx_get_crashdumper_registers()
722 for (i = 0; i < regs->count; i += 2) { in a6xx_get_crashdumper_registers()
723 u32 count = RANGE(regs->registers, i); in a6xx_get_crashdumper_registers()
725 in += CRASHDUMP_READ(in, regs->registers[i], count, out); in a6xx_get_crashdumper_registers()
736 if (a6xx_crashdumper_run(gpu, dumper)) in a6xx_get_crashdumper_registers()
739 obj->handle = regs; in a6xx_get_crashdumper_registers()
740 obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET, in a6xx_get_crashdumper_registers()
745 static void a6xx_get_ahb_gpu_registers(struct msm_gpu *gpu, in a6xx_get_ahb_gpu_registers() argument
753 if (!adreno_is_a660_family(to_adreno_gpu(gpu)) && in a6xx_get_ahb_gpu_registers()
754 (regs->registers == a660_registers)) in a6xx_get_ahb_gpu_registers()
757 for (i = 0; i < regs->count; i += 2) in a6xx_get_ahb_gpu_registers()
758 regcount += RANGE(regs->registers, i); in a6xx_get_ahb_gpu_registers()
760 obj->handle = (const void *) regs; in a6xx_get_ahb_gpu_registers()
761 obj->data = state_kcalloc(a6xx_state, regcount, sizeof(u32)); in a6xx_get_ahb_gpu_registers()
762 if (!obj->data) in a6xx_get_ahb_gpu_registers()
765 for (i = 0; i < regs->count; i += 2) { in a6xx_get_ahb_gpu_registers()
766 u32 count = RANGE(regs->registers, i); in a6xx_get_ahb_gpu_registers()
770 obj->data[index++] = gpu_read(gpu, in a6xx_get_ahb_gpu_registers()
771 regs->registers[i] + j); in a6xx_get_ahb_gpu_registers()
776 static void _a6xx_get_gmu_registers(struct msm_gpu *gpu, in _a6xx_get_gmu_registers() argument
782 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in _a6xx_get_gmu_registers()
784 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in _a6xx_get_gmu_registers()
787 for (i = 0; i < regs->count; i += 2) in _a6xx_get_gmu_registers()
788 regcount += RANGE(regs->registers, i); in _a6xx_get_gmu_registers()
790 obj->handle = (const void *) regs; in _a6xx_get_gmu_registers()
791 obj->data = state_kcalloc(a6xx_state, regcount, sizeof(u32)); in _a6xx_get_gmu_registers()
792 if (!obj->data) in _a6xx_get_gmu_registers()
795 for (i = 0; i < regs->count; i += 2) { in _a6xx_get_gmu_registers()
796 u32 count = RANGE(regs->registers, i); in _a6xx_get_gmu_registers()
800 u32 offset = regs->registers[i] + j; in _a6xx_get_gmu_registers()
808 obj->data[index++] = val; in _a6xx_get_gmu_registers()
813 static void a6xx_get_gmu_registers(struct msm_gpu *gpu, in a6xx_get_gmu_registers() argument
816 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_get_gmu_registers()
819 a6xx_state->gmu_registers = state_kcalloc(a6xx_state, in a6xx_get_gmu_registers()
820 3, sizeof(*a6xx_state->gmu_registers)); in a6xx_get_gmu_registers()
822 if (!a6xx_state->gmu_registers) in a6xx_get_gmu_registers()
825 a6xx_state->nr_gmu_registers = 3; in a6xx_get_gmu_registers()
828 _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[0], in a6xx_get_gmu_registers()
829 &a6xx_state->gmu_registers[0], false); in a6xx_get_gmu_registers()
830 _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1], in a6xx_get_gmu_registers()
831 &a6xx_state->gmu_registers[1], true); in a6xx_get_gmu_registers()
833 if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) in a6xx_get_gmu_registers()
837 gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); in a6xx_get_gmu_registers()
839 _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[2], in a6xx_get_gmu_registers()
840 &a6xx_state->gmu_registers[2], false); in a6xx_get_gmu_registers()
848 if (!bo->size) in a6xx_snapshot_gmu_bo()
855 snapshot->iova = bo->iova; in a6xx_snapshot_gmu_bo()
856 snapshot->size = bo->size; in a6xx_snapshot_gmu_bo()
857 snapshot->data = kvzalloc(snapshot->size, GFP_KERNEL); in a6xx_snapshot_gmu_bo()
858 if (!snapshot->data) in a6xx_snapshot_gmu_bo()
861 memcpy(snapshot->data, bo->virt, bo->size); in a6xx_snapshot_gmu_bo()
866 static void a6xx_snapshot_gmu_hfi_history(struct msm_gpu *gpu, in a6xx_snapshot_gmu_hfi_history() argument
869 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_snapshot_gmu_hfi_history()
871 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_snapshot_gmu_hfi_history()
874 BUILD_BUG_ON(ARRAY_SIZE(gmu->queues) != ARRAY_SIZE(a6xx_state->hfi_queue_history)); in a6xx_snapshot_gmu_hfi_history()
876 for (i = 0; i < ARRAY_SIZE(gmu->queues); i++) { in a6xx_snapshot_gmu_hfi_history()
877 struct a6xx_hfi_queue *queue = &gmu->queues[i]; in a6xx_snapshot_gmu_hfi_history()
879 unsigned idx = (j + queue->history_idx) % HFI_HISTORY_SZ; in a6xx_snapshot_gmu_hfi_history()
880 a6xx_state->hfi_queue_history[i][j] = queue->history[idx]; in a6xx_snapshot_gmu_hfi_history()
887 static void a6xx_get_registers(struct msm_gpu *gpu, in a6xx_get_registers() argument
895 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_get_registers()
897 a6xx_state->registers = state_kcalloc(a6xx_state, in a6xx_get_registers()
898 count, sizeof(*a6xx_state->registers)); in a6xx_get_registers()
900 if (!a6xx_state->registers) in a6xx_get_registers()
903 a6xx_state->nr_registers = count; in a6xx_get_registers()
906 a6xx_get_ahb_gpu_registers(gpu, in a6xx_get_registers()
908 &a6xx_state->registers[index++]); in a6xx_get_registers()
910 a6xx_get_ahb_gpu_registers(gpu, in a6xx_get_registers()
912 &a6xx_state->registers[index++]); in a6xx_get_registers()
915 a6xx_get_ahb_gpu_registers(gpu, in a6xx_get_registers()
917 &a6xx_state->registers[index++]); in a6xx_get_registers()
919 a6xx_get_ahb_gpu_registers(gpu, in a6xx_get_registers()
921 &a6xx_state->registers[index++]); in a6xx_get_registers()
923 a6xx_get_ahb_gpu_registers(gpu, in a6xx_get_registers()
925 &a6xx_state->registers[index++]); in a6xx_get_registers()
929 * because the GPU has no memory access until we resume in a6xx_get_registers()
931 * we have captured as much useful GPU state as possible). in a6xx_get_registers()
935 a6xx_get_ahb_gpu_registers(gpu, in a6xx_get_registers()
937 &a6xx_state->registers[index++]); in a6xx_get_registers()
942 a6xx_get_crashdumper_registers(gpu, in a6xx_get_registers()
944 &a6xx_state->registers[index++], in a6xx_get_registers()
948 a6xx_get_crashdumper_hlsq_registers(gpu, in a6xx_get_registers()
950 &a6xx_state->registers[index++], in a6xx_get_registers()
954 static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu) in a6xx_get_cp_roq_size() argument
957 return gpu_read(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2) >> 14; in a6xx_get_cp_roq_size()
960 static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu) in a7xx_get_cp_roq_size() argument
967 gpu_write(gpu, REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 0x70d3); in a7xx_get_cp_roq_size()
969 return 4 * (gpu_read(gpu, REG_A6XX_CP_SQE_UCODE_DBG_DATA) >> 20); in a7xx_get_cp_roq_size()
973 static void a6xx_get_indexed_regs(struct msm_gpu *gpu, in a6xx_get_indexed_regs() argument
980 obj->handle = (const void *) indexed; in a6xx_get_indexed_regs()
981 if (indexed->count_fn) in a6xx_get_indexed_regs()
982 indexed->count = indexed->count_fn(gpu); in a6xx_get_indexed_regs()
984 obj->data = state_kcalloc(a6xx_state, indexed->count, sizeof(u32)); in a6xx_get_indexed_regs()
985 if (!obj->data) in a6xx_get_indexed_regs()
989 gpu_write(gpu, indexed->addr, 0); in a6xx_get_indexed_regs()
991 /* Read the data - each read increments the internal address by 1 */ in a6xx_get_indexed_regs()
992 for (i = 0; i < indexed->count; i++) in a6xx_get_indexed_regs()
993 obj->data[i] = gpu_read(gpu, indexed->data); in a6xx_get_indexed_regs()
996 static void a6xx_get_indexed_registers(struct msm_gpu *gpu, in a6xx_get_indexed_registers() argument
1003 a6xx_state->indexed_regs = state_kcalloc(a6xx_state, count, in a6xx_get_indexed_registers()
1004 sizeof(*a6xx_state->indexed_regs)); in a6xx_get_indexed_registers()
1005 if (!a6xx_state->indexed_regs) in a6xx_get_indexed_registers()
1009 a6xx_get_indexed_regs(gpu, a6xx_state, &a6xx_indexed_reglist[i], in a6xx_get_indexed_registers()
1010 &a6xx_state->indexed_regs[i]); in a6xx_get_indexed_registers()
1012 if (adreno_is_a650_family(to_adreno_gpu(gpu))) { in a6xx_get_indexed_registers()
1015 val = gpu_read(gpu, REG_A6XX_CP_CHICKEN_DBG); in a6xx_get_indexed_registers()
1016 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, val | 4); in a6xx_get_indexed_registers()
1019 a6xx_get_indexed_regs(gpu, a6xx_state, &a6xx_cp_mempool_indexed, in a6xx_get_indexed_registers()
1020 &a6xx_state->indexed_regs[i]); in a6xx_get_indexed_registers()
1022 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, val); in a6xx_get_indexed_registers()
1023 a6xx_state->nr_indexed_regs = count; in a6xx_get_indexed_registers()
1028 mempool_size = gpu_read(gpu, REG_A6XX_CP_MEM_POOL_SIZE); in a6xx_get_indexed_registers()
1029 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 0); in a6xx_get_indexed_registers()
1032 a6xx_get_indexed_regs(gpu, a6xx_state, &a6xx_cp_mempool_indexed, in a6xx_get_indexed_registers()
1033 &a6xx_state->indexed_regs[i]); in a6xx_get_indexed_registers()
1036 * Offset 0x2000 in the mempool is the size - copy the saved size over in a6xx_get_indexed_registers()
1039 a6xx_state->indexed_regs[i].data[0x2000] = mempool_size; in a6xx_get_indexed_registers()
1042 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, mempool_size); in a6xx_get_indexed_registers()
1045 static void a7xx_get_indexed_registers(struct msm_gpu *gpu, in a7xx_get_indexed_registers() argument
1053 a6xx_state->indexed_regs = state_kcalloc(a6xx_state, in a7xx_get_indexed_registers()
1055 sizeof(*a6xx_state->indexed_regs)); in a7xx_get_indexed_registers()
1056 if (!a6xx_state->indexed_regs) in a7xx_get_indexed_registers()
1059 a6xx_state->nr_indexed_regs = indexed_count + mempool_count; in a7xx_get_indexed_registers()
1063 a6xx_get_indexed_regs(gpu, a6xx_state, &a7xx_indexed_reglist[i], in a7xx_get_indexed_registers()
1064 &a6xx_state->indexed_regs[i]); in a7xx_get_indexed_registers()
1066 gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, 0, BIT(2)); in a7xx_get_indexed_registers()
1067 gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, 0, BIT(2)); in a7xx_get_indexed_registers()
1071 a6xx_get_indexed_regs(gpu, a6xx_state, a7xx_cp_bv_mempool_indexed, in a7xx_get_indexed_registers()
1072 &a6xx_state->indexed_regs[indexed_count - 1 + i]); in a7xx_get_indexed_registers()
1074 gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(2), 0); in a7xx_get_indexed_registers()
1075 gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, BIT(2), 0); in a7xx_get_indexed_registers()
1079 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu) in a6xx_gpu_state_get() argument
1082 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_gpu_state_get()
1086 bool stalled = !!(gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & in a6xx_gpu_state_get()
1090 return ERR_PTR(-ENOMEM); in a6xx_gpu_state_get()
1092 INIT_LIST_HEAD(&a6xx_state->objs); in a6xx_gpu_state_get()
1095 adreno_gpu_state_get(gpu, &a6xx_state->base); in a6xx_gpu_state_get()
1098 a6xx_get_gmu_registers(gpu, a6xx_state); in a6xx_gpu_state_get()
1100 a6xx_state->gmu_log = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.log); in a6xx_gpu_state_get()
1101 a6xx_state->gmu_hfi = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.hfi); in a6xx_gpu_state_get()
1102 a6xx_state->gmu_debug = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.debug); in a6xx_gpu_state_get()
1104 a6xx_snapshot_gmu_hfi_history(gpu, a6xx_state); in a6xx_gpu_state_get()
1108 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) in a6xx_gpu_state_get()
1109 return &a6xx_state->base; in a6xx_gpu_state_get()
1113 a7xx_get_indexed_registers(gpu, a6xx_state); in a6xx_gpu_state_get()
1115 return &a6xx_state->base; in a6xx_gpu_state_get()
1118 a6xx_get_indexed_registers(gpu, a6xx_state); in a6xx_gpu_state_get()
1123 * write out GPU state, so we need to skip this when the SMMU is in a6xx_gpu_state_get()
1126 if (!stalled && !gpu->needs_hw_init && in a6xx_gpu_state_get()
1127 !a6xx_crashdumper_init(gpu, &_dumper)) { in a6xx_gpu_state_get()
1131 a6xx_get_registers(gpu, a6xx_state, dumper); in a6xx_gpu_state_get()
1134 a6xx_get_shaders(gpu, a6xx_state, dumper); in a6xx_gpu_state_get()
1135 a6xx_get_clusters(gpu, a6xx_state, dumper); in a6xx_gpu_state_get()
1136 a6xx_get_dbgahb_clusters(gpu, a6xx_state, dumper); in a6xx_gpu_state_get()
1138 msm_gem_kernel_put(dumper->bo, gpu->aspace); in a6xx_gpu_state_get()
1142 a6xx_get_debugbus(gpu, a6xx_state); in a6xx_gpu_state_get()
1144 a6xx_state->gpu_initialized = !gpu->needs_hw_init; in a6xx_gpu_state_get()
1146 return &a6xx_state->base; in a6xx_gpu_state_get()
1157 if (a6xx_state->gmu_log) in a6xx_gpu_state_destroy()
1158 kvfree(a6xx_state->gmu_log->data); in a6xx_gpu_state_destroy()
1160 if (a6xx_state->gmu_hfi) in a6xx_gpu_state_destroy()
1161 kvfree(a6xx_state->gmu_hfi->data); in a6xx_gpu_state_destroy()
1163 if (a6xx_state->gmu_debug) in a6xx_gpu_state_destroy()
1164 kvfree(a6xx_state->gmu_debug->data); in a6xx_gpu_state_destroy()
1166 list_for_each_entry_safe(obj, tmp, &a6xx_state->objs, node) { in a6xx_gpu_state_destroy()
1167 list_del(&obj->node); in a6xx_gpu_state_destroy()
1180 return kref_put(&state->ref, a6xx_gpu_state_destroy); in a6xx_gpu_state_put()
1200 drm_printf(p, " - { offset: 0x%06x, value: 0x%08x }\n", in a6xx_show_registers()
1241 const struct a6xx_shader_block *block = obj->handle; in a6xx_show_shader()
1244 if (!obj->handle) in a6xx_show_shader()
1247 print_name(p, " - type: ", block->name); in a6xx_show_shader()
1250 drm_printf(p, " - bank: %d\n", i); in a6xx_show_shader()
1251 drm_printf(p, " size: %d\n", block->size); in a6xx_show_shader()
1253 if (!obj->data) in a6xx_show_shader()
1256 print_ascii85(p, block->size << 2, in a6xx_show_shader()
1257 obj->data + (block->size * i)); in a6xx_show_shader()
1269 drm_printf(p, " - context: %d\n", ctx); in a6xx_show_cluster_data()
1280 drm_printf(p, " - { offset: 0x%06x, value: 0x%08x }\n", in a6xx_show_cluster_data()
1290 const struct a6xx_dbgahb_cluster *dbgahb = obj->handle; in a6xx_show_dbgahb_cluster()
1293 print_name(p, " - cluster-name: ", dbgahb->name); in a6xx_show_dbgahb_cluster()
1294 a6xx_show_cluster_data(dbgahb->registers, dbgahb->count, in a6xx_show_dbgahb_cluster()
1295 obj->data, p); in a6xx_show_dbgahb_cluster()
1302 const struct a6xx_cluster *cluster = obj->handle; in a6xx_show_cluster()
1305 print_name(p, " - cluster-name: ", cluster->name); in a6xx_show_cluster()
1306 a6xx_show_cluster_data(cluster->registers, cluster->count, in a6xx_show_cluster()
1307 obj->data, p); in a6xx_show_cluster()
1314 const struct a6xx_indexed_registers *indexed = obj->handle; in a6xx_show_indexed_regs()
1319 print_name(p, " - regs-name: ", indexed->name); in a6xx_show_indexed_regs()
1320 drm_printf(p, " dwords: %d\n", indexed->count); in a6xx_show_indexed_regs()
1322 print_ascii85(p, indexed->count << 2, obj->data); in a6xx_show_indexed_regs()
1329 print_name(p, " - debugbus-block: ", block->name); in a6xx_show_debugbus_block()
1335 drm_printf(p, " count: %d\n", block->count << 1); in a6xx_show_debugbus_block()
1337 print_ascii85(p, block->count << 3, data); in a6xx_show_debugbus_block()
1346 for (i = 0; i < a6xx_state->nr_debugbus; i++) { in a6xx_show_debugbus()
1347 struct a6xx_gpu_state_obj *obj = &a6xx_state->debugbus[i]; in a6xx_show_debugbus()
1349 a6xx_show_debugbus_block(obj->handle, obj->data, p); in a6xx_show_debugbus()
1352 if (a6xx_state->vbif_debugbus) { in a6xx_show_debugbus()
1353 struct a6xx_gpu_state_obj *obj = a6xx_state->vbif_debugbus; in a6xx_show_debugbus()
1355 drm_puts(p, " - debugbus-block: A6XX_DBGBUS_VBIF\n"); in a6xx_show_debugbus()
1359 print_ascii85(p, VBIF_DEBUGBUS_BLOCK_SIZE << 2, obj->data); in a6xx_show_debugbus()
1362 for (i = 0; i < a6xx_state->nr_cx_debugbus; i++) { in a6xx_show_debugbus()
1363 struct a6xx_gpu_state_obj *obj = &a6xx_state->cx_debugbus[i]; in a6xx_show_debugbus()
1365 a6xx_show_debugbus_block(obj->handle, obj->data, p); in a6xx_show_debugbus()
1369 void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, in a6xx_show() argument
1379 drm_printf(p, "gpu-initialized: %d\n", a6xx_state->gpu_initialized); in a6xx_show()
1381 adreno_show(gpu, state, p); in a6xx_show()
1383 drm_puts(p, "gmu-log:\n"); in a6xx_show()
1384 if (a6xx_state->gmu_log) { in a6xx_show()
1385 struct msm_gpu_state_bo *gmu_log = a6xx_state->gmu_log; in a6xx_show()
1387 drm_printf(p, " iova: 0x%016llx\n", gmu_log->iova); in a6xx_show()
1388 drm_printf(p, " size: %zu\n", gmu_log->size); in a6xx_show()
1389 adreno_show_object(p, &gmu_log->data, gmu_log->size, in a6xx_show()
1390 &gmu_log->encoded); in a6xx_show()
1393 drm_puts(p, "gmu-hfi:\n"); in a6xx_show()
1394 if (a6xx_state->gmu_hfi) { in a6xx_show()
1395 struct msm_gpu_state_bo *gmu_hfi = a6xx_state->gmu_hfi; in a6xx_show()
1398 drm_printf(p, " iova: 0x%016llx\n", gmu_hfi->iova); in a6xx_show()
1399 drm_printf(p, " size: %zu\n", gmu_hfi->size); in a6xx_show()
1400 for (i = 0; i < ARRAY_SIZE(a6xx_state->hfi_queue_history); i++) { in a6xx_show()
1401 drm_printf(p, " queue-history[%u]:", i); in a6xx_show()
1403 drm_printf(p, " %d", a6xx_state->hfi_queue_history[i][j]); in a6xx_show()
1407 adreno_show_object(p, &gmu_hfi->data, gmu_hfi->size, in a6xx_show()
1408 &gmu_hfi->encoded); in a6xx_show()
1411 drm_puts(p, "gmu-debug:\n"); in a6xx_show()
1412 if (a6xx_state->gmu_debug) { in a6xx_show()
1413 struct msm_gpu_state_bo *gmu_debug = a6xx_state->gmu_debug; in a6xx_show()
1415 drm_printf(p, " iova: 0x%016llx\n", gmu_debug->iova); in a6xx_show()
1416 drm_printf(p, " size: %zu\n", gmu_debug->size); in a6xx_show()
1417 adreno_show_object(p, &gmu_debug->data, gmu_debug->size, in a6xx_show()
1418 &gmu_debug->encoded); in a6xx_show()
1422 for (i = 0; i < a6xx_state->nr_registers; i++) { in a6xx_show()
1423 struct a6xx_gpu_state_obj *obj = &a6xx_state->registers[i]; in a6xx_show()
1424 const struct a6xx_registers *regs = obj->handle; in a6xx_show()
1426 if (!obj->handle) in a6xx_show()
1429 a6xx_show_registers(regs->registers, obj->data, regs->count, p); in a6xx_show()
1432 drm_puts(p, "registers-gmu:\n"); in a6xx_show()
1433 for (i = 0; i < a6xx_state->nr_gmu_registers; i++) { in a6xx_show()
1434 struct a6xx_gpu_state_obj *obj = &a6xx_state->gmu_registers[i]; in a6xx_show()
1435 const struct a6xx_registers *regs = obj->handle; in a6xx_show()
1437 if (!obj->handle) in a6xx_show()
1440 a6xx_show_registers(regs->registers, obj->data, regs->count, p); in a6xx_show()
1443 drm_puts(p, "indexed-registers:\n"); in a6xx_show()
1444 for (i = 0; i < a6xx_state->nr_indexed_regs; i++) in a6xx_show()
1445 a6xx_show_indexed_regs(&a6xx_state->indexed_regs[i], p); in a6xx_show()
1447 drm_puts(p, "shader-blocks:\n"); in a6xx_show()
1448 for (i = 0; i < a6xx_state->nr_shaders; i++) in a6xx_show()
1449 a6xx_show_shader(&a6xx_state->shaders[i], p); in a6xx_show()
1452 for (i = 0; i < a6xx_state->nr_clusters; i++) in a6xx_show()
1453 a6xx_show_cluster(&a6xx_state->clusters[i], p); in a6xx_show()
1455 for (i = 0; i < a6xx_state->nr_dbgahb_clusters; i++) in a6xx_show()
1456 a6xx_show_dbgahb_cluster(&a6xx_state->dbgahb_clusters[i], p); in a6xx_show()