Lines Matching full:gpu
18 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) in _a6xx_check_idle() argument
20 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in _a6xx_check_idle()
28 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
32 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
36 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_idle() argument
39 if (!adreno_idle(gpu, ring)) in a6xx_idle()
42 if (spin_until(_a6xx_check_idle(gpu))) { in a6xx_idle()
43 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", in a6xx_idle()
44 gpu->name, __builtin_return_address(0), in a6xx_idle()
45 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
46 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), in a6xx_idle()
47 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_idle()
48 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); in a6xx_idle()
55 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr() argument
57 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in update_shadow_rptr()
68 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_flush() argument
73 update_shadow_rptr(gpu, ring); in a6xx_flush()
88 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); in a6xx_flush()
159 * lingering in that part of the GPU in a6xx_set_pagetable()
187 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a6xx_submit() argument
190 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_submit()
202 * GPU registers so we need to add 0x1a800 to the register value on A630 in a6xx_submit()
221 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) in a6xx_submit()
241 update_shadow_rptr(gpu, ring); in a6xx_submit()
265 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER)); in a6xx_submit()
267 a6xx_flush(gpu, ring); in a6xx_submit()
270 static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a7xx_submit() argument
273 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a7xx_submit()
307 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) in a7xx_submit()
327 update_shadow_rptr(gpu, ring); in a7xx_submit()
392 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER)); in a7xx_submit()
394 a6xx_flush(gpu, ring); in a7xx_submit()
955 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) in a6xx_set_hwcg() argument
957 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_set_hwcg()
985 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); in a6xx_set_hwcg()
996 gpu_write(gpu, reg->offset, state ? reg->value : 0); in a6xx_set_hwcg()
1002 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); in a6xx_set_hwcg()
1221 static void a6xx_set_cp_protect(struct msm_gpu *gpu) in a6xx_set_cp_protect() argument
1223 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_set_cp_protect()
1259 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, in a6xx_set_cp_protect()
1267 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]); in a6xx_set_cp_protect()
1270 gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]); in a6xx_set_cp_protect()
1273 static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) in a6xx_calc_ubwc_config() argument
1276 gpu->ubwc_config.rgb565_predicator = 0; in a6xx_calc_ubwc_config()
1278 gpu->ubwc_config.uavflagprd_inv = 0; in a6xx_calc_ubwc_config()
1280 gpu->ubwc_config.min_acc_len = 0; in a6xx_calc_ubwc_config()
1281 /* Entirely magic, per-GPU-gen value */ in a6xx_calc_ubwc_config()
1282 gpu->ubwc_config.ubwc_mode = 0; in a6xx_calc_ubwc_config()
1287 gpu->ubwc_config.highest_bank_bit = 15; in a6xx_calc_ubwc_config()
1289 if (adreno_is_a610(gpu)) { in a6xx_calc_ubwc_config()
1290 gpu->ubwc_config.highest_bank_bit = 13; in a6xx_calc_ubwc_config()
1291 gpu->ubwc_config.min_acc_len = 1; in a6xx_calc_ubwc_config()
1292 gpu->ubwc_config.ubwc_mode = 1; in a6xx_calc_ubwc_config()
1296 if (adreno_is_a618(gpu)) in a6xx_calc_ubwc_config()
1299 if (adreno_is_a619_holi(gpu)) in a6xx_calc_ubwc_config()
1300 gpu->ubwc_config.highest_bank_bit = 13; in a6xx_calc_ubwc_config()
1302 if (adreno_is_a640_family(gpu)) in a6xx_calc_ubwc_config()
1303 gpu->ubwc_config.amsbc = 1; in a6xx_calc_ubwc_config()
1305 if (adreno_is_a650(gpu) || in a6xx_calc_ubwc_config()
1306 adreno_is_a660(gpu) || in a6xx_calc_ubwc_config()
1307 adreno_is_a690(gpu) || in a6xx_calc_ubwc_config()
1308 adreno_is_a730(gpu) || in a6xx_calc_ubwc_config()
1309 adreno_is_a740_family(gpu)) { in a6xx_calc_ubwc_config()
1311 gpu->ubwc_config.highest_bank_bit = 16; in a6xx_calc_ubwc_config()
1312 gpu->ubwc_config.amsbc = 1; in a6xx_calc_ubwc_config()
1313 gpu->ubwc_config.rgb565_predicator = 1; in a6xx_calc_ubwc_config()
1314 gpu->ubwc_config.uavflagprd_inv = 2; in a6xx_calc_ubwc_config()
1317 if (adreno_is_7c3(gpu)) { in a6xx_calc_ubwc_config()
1318 gpu->ubwc_config.highest_bank_bit = 14; in a6xx_calc_ubwc_config()
1319 gpu->ubwc_config.amsbc = 1; in a6xx_calc_ubwc_config()
1320 gpu->ubwc_config.rgb565_predicator = 1; in a6xx_calc_ubwc_config()
1321 gpu->ubwc_config.uavflagprd_inv = 2; in a6xx_calc_ubwc_config()
1325 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) in a6xx_set_ubwc_config() argument
1327 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_set_ubwc_config()
1338 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, in a6xx_set_ubwc_config()
1344 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 | in a6xx_set_ubwc_config()
1348 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 | in a6xx_set_ubwc_config()
1354 gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, in a6xx_set_ubwc_config()
1357 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, in a6xx_set_ubwc_config()
1361 static int a6xx_cp_init(struct msm_gpu *gpu) in a6xx_cp_init() argument
1363 struct msm_ringbuffer *ring = gpu->rb[0]; in a6xx_cp_init()
1386 a6xx_flush(gpu, ring); in a6xx_cp_init()
1387 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; in a6xx_cp_init()
1390 static int a7xx_cp_init(struct msm_gpu *gpu) in a7xx_cp_init() argument
1392 struct msm_ringbuffer *ring = gpu->rb[0]; in a7xx_cp_init()
1435 a6xx_flush(gpu, ring); in a7xx_cp_init()
1436 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; in a7xx_cp_init()
1447 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_ucode_check_version() local
1487 DRM_DEV_ERROR(&gpu->pdev->dev, in a6xx_ucode_check_version()
1496 DRM_DEV_ERROR(&gpu->pdev->dev, in a6xx_ucode_check_version()
1502 DRM_DEV_ERROR(&gpu->pdev->dev, in a6xx_ucode_check_version()
1503 "unknown GPU, add it to a6xx_ucode_check_version()!!\n"); in a6xx_ucode_check_version()
1510 static int a6xx_ucode_load(struct msm_gpu *gpu) in a6xx_ucode_load() argument
1512 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_ucode_load()
1516 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu, in a6xx_ucode_load()
1523 DRM_DEV_ERROR(&gpu->pdev->dev, in a6xx_ucode_load()
1531 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); in a6xx_ucode_load()
1545 a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev, in a6xx_ucode_load()
1546 sizeof(u32) * gpu->nr_rings, in a6xx_ucode_load()
1548 gpu->aspace, &a6xx_gpu->shadow_bo, in a6xx_ucode_load()
1560 static int a6xx_zap_shader_init(struct msm_gpu *gpu) in a6xx_zap_shader_init() argument
1568 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); in a6xx_zap_shader_init()
1609 static int hw_init(struct msm_gpu *gpu) in hw_init() argument
1611 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in hw_init()
1618 /* Make sure the GMU keeps the GPU on while we set it up */ in hw_init()
1626 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); in hw_init()
1627 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0); in hw_init()
1628 /* Let's make extra sure that the GPU can access the memory.. */ in hw_init()
1631 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); in hw_init()
1632 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); in hw_init()
1633 /* Let's make extra sure that the GPU can access the memory.. */ in hw_init()
1639 spin_until(!gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK)); in hw_init()
1641 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); in hw_init()
1651 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000); in hw_init()
1652 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); in hw_init()
1656 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); in hw_init()
1657 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); in hw_init()
1658 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); in hw_init()
1659 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); in hw_init()
1660 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); in hw_init()
1661 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); in hw_init()
1662 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); in hw_init()
1663 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); in hw_init()
1664 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); in hw_init()
1665 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); in hw_init()
1666 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); in hw_init()
1667 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); in hw_init()
1671 a6xx_set_hwcg(gpu, true); in hw_init()
1678 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); in hw_init()
1679 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); in hw_init()
1680 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); in hw_init()
1681 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); in hw_init()
1682 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, in hw_init()
1685 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); in hw_init()
1689 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); in hw_init()
1692 gpu_write(gpu, REG_A6XX_UCHE_GBIF_GX_CONFIG, 0x10240e0); in hw_init()
1694 /* Make all blocks contribute to the GPU BUSY perf counter */ in hw_init()
1695 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); in hw_init()
1699 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, 0x0001fffffffff000llu); in hw_init()
1700 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, 0x0001fffffffff000llu); in hw_init()
1702 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX, 0x0001ffffffffffc0llu); in hw_init()
1703 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, 0x0001fffffffff000llu); in hw_init()
1704 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, 0x0001fffffffff000llu); in hw_init()
1711 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ in hw_init()
1712 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, gmem_range_min); in hw_init()
1714 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX, in hw_init()
1719 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, BIT(23)); in hw_init()
1721 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); in hw_init()
1722 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); in hw_init()
1726 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); in hw_init()
1727 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); in hw_init()
1729 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); in hw_init()
1730 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); in hw_init()
1732 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); in hw_init()
1733 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); in hw_init()
1737 gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); in hw_init()
1741 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); in hw_init()
1742 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); in hw_init()
1744 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); in hw_init()
1750 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00800200); in hw_init()
1752 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); in hw_init()
1754 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); in hw_init()
1756 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); in hw_init()
1758 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000); in hw_init()
1760 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); in hw_init()
1762 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000); in hw_init()
1765 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); in hw_init()
1768 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); in hw_init()
1777 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT); in hw_init()
1779 a6xx_set_ubwc_config(gpu); in hw_init()
1784 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff); in hw_init()
1786 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff); in hw_init()
1788 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff); in hw_init()
1790 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); in hw_init()
1792 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); in hw_init()
1794 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1); in hw_init()
1798 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); in hw_init()
1799 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, in hw_init()
1801 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, in hw_init()
1803 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, in hw_init()
1805 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, in hw_init()
1817 a6xx_set_cp_protect(gpu); in hw_init()
1821 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x00028801); in hw_init()
1823 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); in hw_init()
1824 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); in hw_init()
1828 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x90); in hw_init()
1829 /* Set dualQ + disable afull for A660 GPU */ in hw_init()
1831 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906); in hw_init()
1833 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, in hw_init()
1841 if (gpu->hw_apriv) { in hw_init()
1843 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, in hw_init()
1845 gpu_write(gpu, REG_A7XX_CP_BV_APRIV_CNTL, in hw_init()
1847 gpu_write(gpu, REG_A7XX_CP_LPAC_APRIV_CNTL, in hw_init()
1850 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, in hw_init()
1855 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, in hw_init()
1858 ret = adreno_hw_init(gpu); in hw_init()
1862 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); in hw_init()
1865 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); in hw_init()
1872 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); in hw_init()
1874 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, in hw_init()
1879 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR, in hw_init()
1880 shadowptr(a6xx_gpu, gpu->rb[0])); in hw_init()
1885 gpu_write64(gpu, REG_A7XX_CP_BV_RB_RPTR_ADDR, in hw_init()
1886 rbmemptr(gpu->rb[0], bv_fence)); in hw_init()
1890 a6xx_gpu->cur_ring = gpu->rb[0]; in hw_init()
1892 gpu->cur_ctx_seqno = 0; in hw_init()
1895 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); in hw_init()
1897 ret = adreno_is_a7xx(adreno_gpu) ? a7xx_cp_init(gpu) : a6xx_cp_init(gpu); in hw_init()
1908 ret = a6xx_zap_shader_init(gpu); in hw_init()
1910 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); in hw_init()
1911 OUT_RING(gpu->rb[0], 0x00000000); in hw_init()
1913 a6xx_flush(gpu, gpu->rb[0]); in hw_init()
1914 if (!a6xx_idle(gpu, gpu->rb[0])) in hw_init()
1923 dev_warn_once(gpu->dev->dev, in hw_init()
1925 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); in hw_init()
1935 * Tell the GMU that we are done touching the GPU and it can start power in hw_init()
1948 static int a6xx_hw_init(struct msm_gpu *gpu) in a6xx_hw_init() argument
1950 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_hw_init()
1955 ret = hw_init(gpu); in a6xx_hw_init()
1961 static void a6xx_dump(struct msm_gpu *gpu) in a6xx_dump() argument
1963 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", in a6xx_dump()
1964 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); in a6xx_dump()
1965 adreno_dump(gpu); in a6xx_dump()
1968 static void a6xx_recover(struct msm_gpu *gpu) in a6xx_recover() argument
1970 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_recover()
1975 adreno_dump_info(gpu); in a6xx_recover()
1978 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, in a6xx_recover()
1979 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); in a6xx_recover()
1982 a6xx_dump(gpu); in a6xx_recover()
1991 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); in a6xx_recover()
1993 pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); in a6xx_recover()
1996 mutex_lock(&gpu->active_lock); in a6xx_recover()
1997 active_submits = gpu->active_submits; in a6xx_recover()
2003 gpu->active_submits = 0; in a6xx_recover()
2009 /* Reset the GPU to a clean state */ in a6xx_recover()
2010 a6xx_gpu_sw_reset(gpu, true); in a6xx_recover()
2011 a6xx_gpu_sw_reset(gpu, false); in a6xx_recover()
2020 pm_runtime_put(&gpu->pdev->dev); in a6xx_recover()
2023 pm_runtime_put_sync(&gpu->pdev->dev); in a6xx_recover()
2026 DRM_DEV_ERROR(&gpu->pdev->dev, "cx gdsc didn't collapse\n"); in a6xx_recover()
2030 pm_runtime_use_autosuspend(&gpu->pdev->dev); in a6xx_recover()
2033 pm_runtime_get(&gpu->pdev->dev); in a6xx_recover()
2035 pm_runtime_get_sync(&gpu->pdev->dev); in a6xx_recover()
2037 gpu->active_submits = active_submits; in a6xx_recover()
2038 mutex_unlock(&gpu->active_lock); in a6xx_recover()
2040 msm_gpu_hw_init(gpu); in a6xx_recover()
2044 static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) in a6xx_uche_fault_block() argument
2058 val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF); in a6xx_uche_fault_block()
2072 static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id) in a6xx_fault_block() argument
2081 return a6xx_uche_fault_block(gpu, id); in a6xx_fault_block()
2086 struct msm_gpu *gpu = arg; in a6xx_fault_handler() local
2091 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), in a6xx_fault_handler()
2092 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), in a6xx_fault_handler()
2093 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), in a6xx_fault_handler()
2094 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)), in a6xx_fault_handler()
2098 block = a6xx_fault_block(gpu, info->fsynr1 & 0xff); in a6xx_fault_handler()
2100 return adreno_fault_handler(gpu, iova, flags, info, block, scratch); in a6xx_fault_handler()
2103 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) in a6xx_cp_hw_err_irq() argument
2105 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS); in a6xx_cp_hw_err_irq()
2110 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1); in a6xx_cp_hw_err_irq()
2111 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA); in a6xx_cp_hw_err_irq()
2112 dev_err_ratelimited(&gpu->pdev->dev, in a6xx_cp_hw_err_irq()
2118 dev_err_ratelimited(&gpu->pdev->dev, in a6xx_cp_hw_err_irq()
2122 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n", in a6xx_cp_hw_err_irq()
2123 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); in a6xx_cp_hw_err_irq()
2126 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS); in a6xx_cp_hw_err_irq()
2128 dev_err_ratelimited(&gpu->pdev->dev, in a6xx_cp_hw_err_irq()
2134 if (status & A6XX_CP_INT_CP_AHB_ERROR && !adreno_is_a7xx(to_adreno_gpu(gpu))) in a6xx_cp_hw_err_irq()
2135 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n"); in a6xx_cp_hw_err_irq()
2138 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n"); in a6xx_cp_hw_err_irq()
2141 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n"); in a6xx_cp_hw_err_irq()
2145 static void a6xx_fault_detect_irq(struct msm_gpu *gpu) in a6xx_fault_detect_irq() argument
2147 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_fault_detect_irq()
2149 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); in a6xx_fault_detect_irq()
2152 * If stalled on SMMU fault, we could trip the GPU's hang detection, in a6xx_fault_detect_irq()
2157 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT) in a6xx_fault_detect_irq()
2161 * Force the GPU to stay on until after we finish in a6xx_fault_detect_irq()
2167 DRM_DEV_ERROR(&gpu->pdev->dev, in a6xx_fault_detect_irq()
2168 …"gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", in a6xx_fault_detect_irq()
2170 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_fault_detect_irq()
2171 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_fault_detect_irq()
2172 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), in a6xx_fault_detect_irq()
2173 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), in a6xx_fault_detect_irq()
2174 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), in a6xx_fault_detect_irq()
2175 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), in a6xx_fault_detect_irq()
2176 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE)); in a6xx_fault_detect_irq()
2179 del_timer(&gpu->hangcheck_timer); in a6xx_fault_detect_irq()
2181 kthread_queue_work(gpu->worker, &gpu->recover_work); in a6xx_fault_detect_irq()
2184 static irqreturn_t a6xx_irq(struct msm_gpu *gpu) in a6xx_irq() argument
2186 struct msm_drm_private *priv = gpu->dev->dev_private; in a6xx_irq()
2187 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS); in a6xx_irq()
2189 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); in a6xx_irq()
2195 a6xx_fault_detect_irq(gpu); in a6xx_irq()
2198 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n"); in a6xx_irq()
2201 a6xx_cp_hw_err_irq(gpu); in a6xx_irq()
2204 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); in a6xx_irq()
2207 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); in a6xx_irq()
2210 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); in a6xx_irq()
2213 msm_gpu_retire(gpu); in a6xx_irq()
2227 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_llc_activate() local
2244 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) | in a6xx_llc_activate()
2265 * Program the slice IDs for the various GPU blocks and GPU MMU in a6xx_llc_activate()
2281 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval); in a6xx_llc_activate()
2287 struct msm_gpu *gpu = &adreno_gpu->base; in a7xx_llc_activate() local
2297 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, in a7xx_llc_activate()
2305 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, in a7xx_llc_activate()
2361 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_bus_clear_pending_transactions() local
2364 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, GPR0_GBIF_HALT_REQUEST); in a6xx_bus_clear_pending_transactions()
2365 spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & in a6xx_bus_clear_pending_transactions()
2368 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, VBIF_XIN_HALT_CTRL0_MASK); in a6xx_bus_clear_pending_transactions()
2369 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & in a6xx_bus_clear_pending_transactions()
2371 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); in a6xx_bus_clear_pending_transactions()
2378 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1); in a6xx_bus_clear_pending_transactions()
2379 spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1); in a6xx_bus_clear_pending_transactions()
2383 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); in a6xx_bus_clear_pending_transactions()
2384 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & in a6xx_bus_clear_pending_transactions()
2388 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); in a6xx_bus_clear_pending_transactions()
2389 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & in a6xx_bus_clear_pending_transactions()
2393 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); in a6xx_bus_clear_pending_transactions()
2396 void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert) in a6xx_gpu_sw_reset() argument
2399 if (adreno_is_a610(to_adreno_gpu(gpu))) in a6xx_gpu_sw_reset()
2402 gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert); in a6xx_gpu_sw_reset()
2404 gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD); in a6xx_gpu_sw_reset()
2412 static int a6xx_gmu_pm_resume(struct msm_gpu *gpu) in a6xx_gmu_pm_resume() argument
2414 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_gmu_pm_resume()
2418 gpu->needs_hw_init = true; in a6xx_gmu_pm_resume()
2428 msm_devfreq_resume(gpu); in a6xx_gmu_pm_resume()
2435 static int a6xx_pm_resume(struct msm_gpu *gpu) in a6xx_pm_resume() argument
2437 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_pm_resume()
2440 unsigned long freq = gpu->fast_rate; in a6xx_pm_resume()
2444 gpu->needs_hw_init = true; in a6xx_pm_resume()
2450 opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); in a6xx_pm_resume()
2458 dev_pm_opp_set_opp(&gpu->pdev->dev, opp); in a6xx_pm_resume()
2463 ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); in a6xx_pm_resume()
2470 /* If anything goes south, tear the GPU down piece by piece.. */ in a6xx_pm_resume()
2475 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); in a6xx_pm_resume()
2481 msm_devfreq_resume(gpu); in a6xx_pm_resume()
2486 static int a6xx_gmu_pm_suspend(struct msm_gpu *gpu) in a6xx_gmu_pm_suspend() argument
2488 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_gmu_pm_suspend()
2496 msm_devfreq_suspend(gpu); in a6xx_gmu_pm_suspend()
2505 for (i = 0; i < gpu->nr_rings; i++) in a6xx_gmu_pm_suspend()
2508 gpu->suspend_count++; in a6xx_gmu_pm_suspend()
2513 static int a6xx_pm_suspend(struct msm_gpu *gpu) in a6xx_pm_suspend() argument
2515 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_pm_suspend()
2522 msm_devfreq_suspend(gpu); in a6xx_pm_suspend()
2532 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); in a6xx_pm_suspend()
2535 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); in a6xx_pm_suspend()
2541 for (i = 0; i < gpu->nr_rings; i++) in a6xx_pm_suspend()
2544 gpu->suspend_count++; in a6xx_pm_suspend()
2549 static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value) in a6xx_gmu_get_timestamp() argument
2551 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_gmu_get_timestamp()
2556 /* Force the GPU power on so we can read this register */ in a6xx_gmu_get_timestamp()
2559 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); in a6xx_gmu_get_timestamp()
2568 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) in a6xx_get_timestamp() argument
2570 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); in a6xx_get_timestamp()
2574 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) in a6xx_active_ring() argument
2576 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_active_ring()
2582 static void a6xx_destroy(struct msm_gpu *gpu) in a6xx_destroy() argument
2584 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_destroy()
2588 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); in a6xx_destroy()
2593 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace); in a6xx_destroy()
2606 static u64 a6xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) in a6xx_gpu_busy() argument
2608 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_gpu_busy()
2622 static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, in a6xx_gpu_set_freq() argument
2625 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_gpu_set_freq()
2629 a6xx_gmu_set_freq(gpu, opp, suspended); in a6xx_gpu_set_freq()
2634 a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) in a6xx_create_address_space() argument
2636 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_create_address_space()
2641 * This allows GPU to set the bus attributes required to use system in a6xx_create_address_space()
2648 return adreno_iommu_create_address_space(gpu, pdev, quirks); in a6xx_create_address_space()
2652 a6xx_create_private_address_space(struct msm_gpu *gpu) in a6xx_create_private_address_space() argument
2656 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); in a6xx_create_private_address_space()
2662 "gpu", 0x100000000ULL, in a6xx_create_private_address_space()
2663 adreno_private_address_space_size(gpu)); in a6xx_create_private_address_space()
2666 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_get_rptr() argument
2668 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_get_rptr()
2674 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); in a6xx_get_rptr()
2677 static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_progress() argument
2680 .ib1_base = gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), in a6xx_progress()
2681 .ib2_base = gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), in a6xx_progress()
2682 .ib1_rem = gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), in a6xx_progress()
2683 .ib2_rem = gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE), in a6xx_progress()
2700 cp_state.ib1_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB1) >> 16; in a6xx_progress()
2701 cp_state.ib2_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB2) >> 16; in a6xx_progress()
2856 struct msm_gpu *gpu; in a6xx_gpu_init() local
2865 gpu = &adreno_gpu->base; in a6xx_gpu_init()
2881 /* gpu->info only gets assigned in adreno_gpu_init() */ in a6xx_gpu_init()
2921 if (gpu->aspace) in a6xx_gpu_init()
2922 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, in a6xx_gpu_init()
2927 return gpu; in a6xx_gpu_init()