23 	/* Check that the GMU is idle */  in _a6xx_check_idle()
24 	if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu))  in _a6xx_check_idle()
201 	 * For PM4 the GMU register offsets are calculated from the base of the  in a6xx_submit()
959 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;  in a6xx_set_hwcg()  local
977 		gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,  in a6xx_set_hwcg()
979 		gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,  in a6xx_set_hwcg()
981 		gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,  in a6xx_set_hwcg()
993 		gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);  in a6xx_set_hwcg()
1000 		gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);  in a6xx_set_hwcg()
1613 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;  in hw_init()  local
1618 		/* Make sure the GMU keeps the GPU on while we set it up */  in hw_init()
1619 		ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);  in hw_init()
1644 		a6xx_sptprac_enable(gmu);  in hw_init()
1772 		gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1,  in hw_init()
1809 	/* Set up the CX GMU counter 0 to count busy ticks */  in hw_init()
1810 	gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);  in hw_init()
1813 	gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5));  in hw_init()
1814 	gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);  in hw_init()
1935 	 * Tell the GMU that we are done touching the GPU and it can start power  in hw_init()
1938 	a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);  in hw_init()
1940 	if (a6xx_gpu->gmu.legacy) {  in hw_init()
1941 		/* Take the GMU out of its special boot mode */  in hw_init()
1942 		a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);  in hw_init()
1954 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_hw_init()
1956 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_hw_init()
1972 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;  in a6xx_recover()  local
2014 	reinit_completion(&gmu->pd_gate);  in a6xx_recover()
2015 	dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb);  in a6xx_recover()
2016 	dev_pm_genpd_synced_poweroff(gmu->cxpd);  in a6xx_recover()
2025 	if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000)))  in a6xx_recover()
2028 	dev_pm_genpd_remove_notifier(gmu->cxpd);  in a6xx_recover()
2165 		gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);  in a6xx_fault_detect_irq()
2315 	/* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */  in a6xx_llc_slices_destroy()
2328 	/* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */  in a6xx_llc_slices_init()
2422 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_pm_resume()
2424 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_pm_resume()
2439 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;  in a6xx_pm_resume()  local
2448 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_pm_resume()
2460 	pm_runtime_resume_and_get(gmu->dev);  in a6xx_pm_resume()
2461 	pm_runtime_resume_and_get(gmu->gxpd);  in a6xx_pm_resume()
2468 		a6xx_sptprac_enable(gmu);  in a6xx_pm_resume()
2473 		pm_runtime_put(gmu->gxpd);  in a6xx_pm_resume()
2474 		pm_runtime_put(gmu->dev);  in a6xx_pm_resume()
2478 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_pm_resume()
2498 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_pm_suspend()
2500 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_pm_suspend()
2517 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;  in a6xx_pm_suspend()  local
2524 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_pm_suspend()
2530 		a6xx_sptprac_disable(gmu);  in a6xx_pm_suspend()
2534 	pm_runtime_put_sync(gmu->gxpd);  in a6xx_pm_suspend()
2536 	pm_runtime_put_sync(gmu->dev);  in a6xx_pm_suspend()
2538 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_pm_suspend()
2554 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_get_timestamp()
2557 	a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);  in a6xx_gmu_get_timestamp()
2561 	a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);  in a6xx_gmu_get_timestamp()
2563 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_gmu_get_timestamp()
2615 	busy_cycles = gmu_read64(&a6xx_gpu->gmu,  in a6xx_gpu_busy()
2628 	mutex_lock(&a6xx_gpu->gmu.lock);  in a6xx_gpu_set_freq()
2630 	mutex_unlock(&a6xx_gpu->gmu.lock);  in a6xx_gpu_set_freq()
2867 	mutex_init(&a6xx_gpu->gmu.lock);  in a6xx_gpu_init()
2871 	/* Check if there is a GMU phandle and set it up */  in a6xx_gpu_init()
2872 	node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);  in a6xx_gpu_init()
2876 	adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper");  in a6xx_gpu_init()