Lines Matching +full:0 +full:x18454
44 gpu->name, __builtin_return_address(0), in a6xx_idle()
121 OUT_RING(ring, 0); in a6xx_set_pagetable()
135 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); in a6xx_set_pagetable()
136 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0)); in a6xx_set_pagetable()
174 OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0)); in a6xx_set_pagetable()
175 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1)); in a6xx_set_pagetable()
176 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1)); in a6xx_set_pagetable()
177 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0)); in a6xx_set_pagetable()
193 unsigned int i, ibs = 0; in a6xx_submit()
197 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), in a6xx_submit()
202 * GPU registers so we need to add 0x1a800 to the register value on A630 in a6xx_submit()
216 for (i = 0; i < submit->nr_cmds; i++) { in a6xx_submit()
240 if ((ibs % 32) == 0) in a6xx_submit()
244 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), in a6xx_submit()
276 unsigned int i, ibs = 0; in a7xx_submit()
287 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), in a7xx_submit()
296 OUT_RING(ring, 0x101); /* IFPC disable */ in a7xx_submit()
299 OUT_RING(ring, 0x00d); /* IB1LIST start */ in a7xx_submit()
302 for (i = 0; i < submit->nr_cmds; i++) { in a7xx_submit()
326 if ((ibs % 32) == 0) in a7xx_submit()
331 OUT_RING(ring, 0x00e); /* IB1LIST end */ in a7xx_submit()
333 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), in a7xx_submit()
373 OUT_RING(ring, 0); in a7xx_submit()
389 OUT_RING(ring, 0x100); /* IFPC enable */ in a7xx_submit()
398 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
399 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
400 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081},
401 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
402 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
403 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
404 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
405 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
406 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
407 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
408 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
409 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
410 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
411 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
412 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
413 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
414 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
415 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222},
416 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
417 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
418 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},
419 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
420 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
421 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
422 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
423 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
424 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
425 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
426 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
427 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
428 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
429 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
430 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
431 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
432 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
433 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
434 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
435 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
436 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
437 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
438 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
439 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
440 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
441 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
442 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
443 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
449 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
450 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
451 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
452 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
453 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
454 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
455 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
456 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
457 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
458 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
459 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
460 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
461 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
462 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
463 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
464 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
465 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
466 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
467 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
468 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
469 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
470 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
471 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
472 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
473 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
474 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
475 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
476 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
477 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
478 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
479 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
480 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
481 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
482 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
483 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
484 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
485 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020},
486 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
487 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
488 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
489 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
490 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
491 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
492 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
493 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
494 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
495 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
496 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
497 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
498 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
499 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
500 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
501 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
502 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
503 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
504 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
505 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
506 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
507 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
508 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
509 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
510 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
511 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
516 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
517 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
518 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
519 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
520 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
521 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
522 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
523 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
524 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
525 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
526 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
527 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
528 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
529 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
530 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
531 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
532 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
533 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
534 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
535 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
536 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
537 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
538 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
539 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
540 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
541 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
542 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
543 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
544 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
545 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
546 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
547 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
548 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
549 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
550 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
551 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
552 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
553 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
554 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
555 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
556 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
557 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
558 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
559 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
560 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
561 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
562 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
563 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
564 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
565 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
566 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
567 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
568 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
569 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
570 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
571 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
572 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
573 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
574 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
575 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
576 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
577 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
578 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
579 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
580 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
581 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
582 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
583 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
584 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
585 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
586 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
587 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
588 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
589 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
590 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
591 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
592 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
593 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
594 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
595 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
596 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
597 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
598 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
599 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
600 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
601 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
602 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
603 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
604 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
605 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
606 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
607 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
608 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
609 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
610 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
611 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
612 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
613 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
614 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
615 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
616 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
617 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
618 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
619 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
620 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
625 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
626 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
627 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
628 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
629 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
630 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
631 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
632 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
633 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
634 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
635 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
636 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
637 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
638 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
639 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
640 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
641 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
642 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
643 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
644 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
645 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
646 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
647 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
648 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
649 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
650 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
651 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
652 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
653 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
654 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
655 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
656 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
657 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
658 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
659 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
660 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
661 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
662 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
663 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
664 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
665 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
666 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
667 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
668 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
669 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
670 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
671 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
672 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
673 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
678 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
679 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
680 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
681 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
682 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
683 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
684 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
685 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
686 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
687 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
688 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
689 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
690 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
691 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
692 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
693 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
694 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
695 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
696 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
697 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
698 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
699 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
700 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
701 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
702 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
703 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
704 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
705 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
706 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
707 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
708 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
709 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
710 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
711 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
712 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
713 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
714 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
715 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
716 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
717 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
718 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
719 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
720 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
721 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
722 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
723 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
724 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
725 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
726 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
731 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
732 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
733 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
734 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
735 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
736 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
737 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
738 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
739 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
740 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
741 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
742 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
743 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
744 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
745 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
746 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
747 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
748 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
749 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
750 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
751 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
752 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
753 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
754 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
755 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
756 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
757 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
758 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
759 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
760 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
761 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
762 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
763 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
764 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
765 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
766 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
767 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
768 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
769 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
770 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
771 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
772 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
773 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
774 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
775 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
776 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
777 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
778 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
779 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
784 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
785 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
786 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
787 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
788 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
789 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
790 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
791 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
792 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
793 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
794 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
795 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
796 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
797 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
798 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
799 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
800 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
801 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
802 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
803 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
804 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
805 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
806 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
807 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
808 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
809 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
810 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
811 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
812 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
813 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
814 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
815 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
816 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
817 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
818 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
819 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
820 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
821 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
822 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
823 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
824 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
825 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
826 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
827 {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
828 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
829 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
830 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
831 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
832 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
833 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
834 {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
835 {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
836 {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
841 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
842 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 },
843 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
844 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
845 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
846 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
847 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
848 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
849 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
850 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
851 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
852 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
853 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
854 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
855 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
856 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
857 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
858 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
859 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
860 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
861 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
862 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
863 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
864 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
865 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
866 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
867 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
868 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
869 { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
870 { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
871 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
872 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
873 { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
874 { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
875 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
876 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
877 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
878 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
879 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
880 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
881 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
882 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
883 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
884 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
885 { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
886 { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000223 },
887 { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
888 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
889 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
890 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
891 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
892 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
893 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
898 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
899 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x22022222 },
900 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x003cf3cf },
901 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
902 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
903 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
904 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
905 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
906 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
907 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
908 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
909 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
910 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
911 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
912 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
913 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
914 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
915 { REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 },
916 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000444 },
917 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000222 },
918 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
919 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
920 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
921 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
922 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
923 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
924 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
925 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
926 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
927 { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
928 { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
929 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
930 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00222222 },
931 { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
932 { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
933 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
934 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
935 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
936 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 },
937 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
938 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00000000 },
939 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
940 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
941 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
942 { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
943 { REG_A7XX_RBBM_CLOCK_HYST2_VFD, 0x00000000 },
944 { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000222 },
945 { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
946 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
947 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
948 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
949 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
950 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
951 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
968 clock_cntl_on = 0x8aa8aa02; in a6xx_set_hwcg()
970 clock_cntl_on = 0xaaa8aa82; in a6xx_set_hwcg()
972 clock_cntl_on = 0x8aa8aa82; in a6xx_set_hwcg()
975 cgc_mode = adreno_is_a740_family(adreno_gpu) ? 0x20222 : 0x20000; in a6xx_set_hwcg()
978 state ? cgc_mode : 0); in a6xx_set_hwcg()
980 state ? 0x10111 : 0); in a6xx_set_hwcg()
982 state ? 0x5555 : 0); in a6xx_set_hwcg()
993 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); in a6xx_set_hwcg()
995 for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) in a6xx_set_hwcg()
996 gpu_write(gpu, reg->offset, state ? reg->value : 0); in a6xx_set_hwcg()
1000 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); in a6xx_set_hwcg()
1002 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); in a6xx_set_hwcg()
1007 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
1008 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
1009 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
1010 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
1011 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
1012 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
1013 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
1014 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
1015 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
1016 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
1017 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
1018 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
1019 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
1020 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
1021 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
1022 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
1023 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
1024 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
1025 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
1026 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
1027 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
1028 A6XX_PROTECT_NORDWR(0x09e70, 0x0001),
1029 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
1030 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
1031 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
1032 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
1033 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
1034 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
1035 A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
1036 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
1037 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1038 A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */
1043 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
1044 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
1045 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
1046 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
1047 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
1048 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
1049 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
1050 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
1051 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
1052 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
1053 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
1054 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
1055 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
1056 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
1057 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
1058 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
1059 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
1060 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
1061 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
1062 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
1063 A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
1064 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
1065 A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
1066 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
1067 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
1068 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
1069 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
1070 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
1071 A6XX_PROTECT_NORDWR(0x0b608, 0x0007),
1072 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
1073 A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
1074 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
1075 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1076 A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
1077 A6XX_PROTECT_NORDWR(0x1a800, 0x1fff),
1078 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
1079 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
1080 A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
1081 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
1086 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
1087 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
1088 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
1089 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
1090 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
1091 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
1092 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
1093 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
1094 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
1095 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
1096 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
1097 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
1098 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
1099 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
1100 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
1101 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
1102 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
1103 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
1104 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
1105 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
1106 A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
1107 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
1108 A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
1109 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
1110 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
1111 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
1112 A6XX_PROTECT_NORDWR(0x0ae50, 0x012f),
1113 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
1114 A6XX_PROTECT_NORDWR(0x0b608, 0x0006),
1115 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
1116 A6XX_PROTECT_NORDWR(0x0be20, 0x015f),
1117 A6XX_PROTECT_NORDWR(0x0d000, 0x05ff),
1118 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
1119 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1120 A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
1121 A6XX_PROTECT_NORDWR(0x1a400, 0x1fff),
1122 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
1123 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
1124 A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
1125 A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
1126 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
1131 A6XX_PROTECT_RDONLY(0x00000, 0x004ff),
1132 A6XX_PROTECT_RDONLY(0x00501, 0x00001),
1133 A6XX_PROTECT_RDONLY(0x0050b, 0x002f4),
1134 A6XX_PROTECT_NORDWR(0x0050e, 0x00000),
1135 A6XX_PROTECT_NORDWR(0x00510, 0x00000),
1136 A6XX_PROTECT_NORDWR(0x00534, 0x00000),
1137 A6XX_PROTECT_NORDWR(0x00800, 0x00082),
1138 A6XX_PROTECT_NORDWR(0x008a0, 0x00008),
1139 A6XX_PROTECT_NORDWR(0x008ab, 0x00024),
1140 A6XX_PROTECT_RDONLY(0x008de, 0x000ae),
1141 A6XX_PROTECT_NORDWR(0x00900, 0x0004d),
1142 A6XX_PROTECT_NORDWR(0x0098d, 0x00272),
1143 A6XX_PROTECT_NORDWR(0x00e00, 0x00001),
1144 A6XX_PROTECT_NORDWR(0x00e03, 0x0000c),
1145 A6XX_PROTECT_NORDWR(0x03c00, 0x000c3),
1146 A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff),
1147 A6XX_PROTECT_NORDWR(0x08630, 0x001cf),
1148 A6XX_PROTECT_NORDWR(0x08e00, 0x00000),
1149 A6XX_PROTECT_NORDWR(0x08e08, 0x00007),
1150 A6XX_PROTECT_NORDWR(0x08e50, 0x0001f),
1151 A6XX_PROTECT_NORDWR(0x08e80, 0x0027f),
1152 A6XX_PROTECT_NORDWR(0x09624, 0x001db),
1153 A6XX_PROTECT_NORDWR(0x09e60, 0x00011),
1154 A6XX_PROTECT_NORDWR(0x09e78, 0x00187),
1155 A6XX_PROTECT_NORDWR(0x0a630, 0x001cf),
1156 A6XX_PROTECT_NORDWR(0x0ae02, 0x00000),
1157 A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f),
1158 A6XX_PROTECT_NORDWR(0x0b604, 0x00000),
1159 A6XX_PROTECT_NORDWR(0x0b608, 0x00006),
1160 A6XX_PROTECT_NORDWR(0x0be02, 0x00001),
1161 A6XX_PROTECT_NORDWR(0x0be20, 0x0015f),
1162 A6XX_PROTECT_NORDWR(0x0d000, 0x005ff),
1163 A6XX_PROTECT_NORDWR(0x0f000, 0x00bff),
1164 A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff),
1165 A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */
1169 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
1170 A6XX_PROTECT_RDONLY(0x0050b, 0x0058),
1171 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
1172 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
1173 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
1174 A6XX_PROTECT_RDONLY(0x005fb, 0x009d),
1175 A6XX_PROTECT_NORDWR(0x00699, 0x01e9),
1176 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
1177 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
1178 /* 0x008d0-0x008dd are unprotected on purpose for tools like perfetto */
1179 A6XX_PROTECT_RDONLY(0x008de, 0x0154),
1180 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
1181 A6XX_PROTECT_NORDWR(0x0098d, 0x00b2),
1182 A6XX_PROTECT_NORDWR(0x00a41, 0x01be),
1183 A6XX_PROTECT_NORDWR(0x00df0, 0x0001),
1184 A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
1185 A6XX_PROTECT_NORDWR(0x00e07, 0x0008),
1186 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
1187 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
1188 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
1189 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
1190 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
1191 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
1192 A6XX_PROTECT_NORDWR(0x08e80, 0x0280),
1193 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
1194 A6XX_PROTECT_NORDWR(0x09e40, 0x0000),
1195 A6XX_PROTECT_NORDWR(0x09e64, 0x000d),
1196 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
1197 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
1198 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
1199 A6XX_PROTECT_NORDWR(0x0ae50, 0x000f),
1200 A6XX_PROTECT_NORDWR(0x0ae66, 0x0003),
1201 A6XX_PROTECT_NORDWR(0x0ae6f, 0x0003),
1202 A6XX_PROTECT_NORDWR(0x0b604, 0x0003),
1203 A6XX_PROTECT_NORDWR(0x0ec00, 0x0fff),
1204 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1205 A6XX_PROTECT_NORDWR(0x18400, 0x0053),
1206 A6XX_PROTECT_RDONLY(0x18454, 0x0004),
1207 A6XX_PROTECT_NORDWR(0x18459, 0x1fff),
1208 A6XX_PROTECT_NORDWR(0x1a459, 0x1fff),
1209 A6XX_PROTECT_NORDWR(0x1c459, 0x1fff),
1210 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
1211 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
1212 A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
1213 A6XX_PROTECT_NORDWR(0x1f878, 0x002a),
1215 0,
1216 0,
1217 0,
1218 A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000),
1264 for (i = 0; i < count - 1; i++) { in a6xx_set_cp_protect()
1276 gpu->ubwc_config.rgb565_predicator = 0; in a6xx_calc_ubwc_config()
1278 gpu->ubwc_config.uavflagprd_inv = 0; in a6xx_calc_ubwc_config()
1280 gpu->ubwc_config.min_acc_len = 0; in a6xx_calc_ubwc_config()
1282 gpu->ubwc_config.ubwc_mode = 0; in a6xx_calc_ubwc_config()
1363 struct msm_ringbuffer *ring = gpu->rb[0]; in a6xx_cp_init()
1367 OUT_RING(ring, 0x0000002f); in a6xx_cp_init()
1370 OUT_RING(ring, 0x00000003); in a6xx_cp_init()
1373 OUT_RING(ring, 0x20000000); in a6xx_cp_init()
1376 OUT_RING(ring, 0x00000000); in a6xx_cp_init()
1377 OUT_RING(ring, 0x00000000); in a6xx_cp_init()
1380 OUT_RING(ring, 0x00000000); in a6xx_cp_init()
1382 /* Pad rest of the cmds with 0's */ in a6xx_cp_init()
1383 OUT_RING(ring, 0x00000000); in a6xx_cp_init()
1384 OUT_RING(ring, 0x00000000); in a6xx_cp_init()
1387 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; in a6xx_cp_init()
1392 struct msm_ringbuffer *ring = gpu->rb[0]; in a7xx_cp_init()
1402 mask = BIT(0); in a7xx_cp_init()
1419 OUT_RING(ring, 0x00000003); in a7xx_cp_init()
1422 OUT_RING(ring, 0x20000000); in a7xx_cp_init()
1425 OUT_RING(ring, 0x00000002); in a7xx_cp_init()
1429 OUT_RING(ring, 0x00000000); in a7xx_cp_init()
1431 OUT_RING(ring, 0x00000000); in a7xx_cp_init()
1433 OUT_RING(ring, 0x00000000); in a7xx_cp_init()
1436 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; in a7xx_cp_init()
1471 * If the lowest nibble is 0xa that is an indication that this in a6xx_ucode_check_version()
1480 if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) || in a6xx_ucode_check_version()
1481 (buf[0] & 0xfff) >= 0x190) { in a6xx_ucode_check_version()
1489 buf[0] & 0xfff, 0x190); in a6xx_ucode_check_version()
1491 if ((buf[0] & 0xfff) >= 0x095) { in a6xx_ucode_check_version()
1498 buf[0] & 0xfff, 0x095); in a6xx_ucode_check_version()
1557 return 0; in a6xx_ucode_load()
1566 return 0; in a6xx_zap_shader_init()
1626 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); in hw_init()
1627 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0); in hw_init()
1631 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); in hw_init()
1632 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); in hw_init()
1641 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); in hw_init()
1651 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000); in hw_init()
1652 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); in hw_init()
1656 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); in hw_init()
1657 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); in hw_init()
1658 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); in hw_init()
1659 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); in hw_init()
1660 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); in hw_init()
1661 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); in hw_init()
1662 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); in hw_init()
1663 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); in hw_init()
1664 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); in hw_init()
1665 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); in hw_init()
1666 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); in hw_init()
1667 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); in hw_init()
1678 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); in hw_init()
1679 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); in hw_init()
1680 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); in hw_init()
1681 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); in hw_init()
1683 adreno_is_a7xx(adreno_gpu) ? 0x2120212 : 0x3); in hw_init()
1685 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); in hw_init()
1689 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); in hw_init()
1692 gpu_write(gpu, REG_A6XX_UCHE_GBIF_GX_CONFIG, 0x10240e0); in hw_init()
1695 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); in hw_init()
1699 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, 0x0001fffffffff000llu); in hw_init()
1700 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, 0x0001fffffffff000llu); in hw_init()
1702 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX, 0x0001ffffffffffc0llu); in hw_init()
1703 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, 0x0001fffffffff000llu); in hw_init()
1704 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, 0x0001fffffffff000llu); in hw_init()
1711 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ in hw_init()
1721 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); in hw_init()
1722 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); in hw_init()
1726 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); in hw_init()
1727 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); in hw_init()
1729 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); in hw_init()
1730 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); in hw_init()
1732 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); in hw_init()
1733 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); in hw_init()
1737 gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); in hw_init()
1747 * and vccCacheSkipDis=1 bit (0x200) for A640 and newer in hw_init()
1750 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00800200); in hw_init()
1752 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); in hw_init()
1754 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); in hw_init()
1756 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); in hw_init()
1758 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000); in hw_init()
1760 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); in hw_init()
1762 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000); in hw_init()
1765 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); in hw_init()
1768 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); in hw_init()
1773 FIELD_PREP(GENMASK(7, 0), 0x4)); in hw_init()
1777 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT); in hw_init()
1784 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff); in hw_init()
1786 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff); in hw_init()
1788 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff); in hw_init()
1790 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); in hw_init()
1792 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); in hw_init()
1794 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1); in hw_init()
1798 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); in hw_init()
1800 0x3fe05ff4); in hw_init()
1802 0x3fa0ebee); in hw_init()
1804 0x3f5193ed); in hw_init()
1806 0x3f0243f0); in hw_init()
1809 /* Set up the CX GMU counter 0 to count busy ticks */ in hw_init()
1810 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); in hw_init()
1813 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); in hw_init()
1821 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x00028801); in hw_init()
1823 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); in hw_init()
1824 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); in hw_init()
1828 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x90); in hw_init()
1831 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906); in hw_init()
1838 FIELD_PREP(GENMASK(1, 0), 2)); in hw_init()
1865 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); in hw_init()
1880 shadowptr(a6xx_gpu, gpu->rb[0])); in hw_init()
1886 rbmemptr(gpu->rb[0], bv_fence)); in hw_init()
1889 /* Always come up on rb 0 */ in hw_init()
1890 a6xx_gpu->cur_ring = gpu->rb[0]; in hw_init()
1892 gpu->cur_ctx_seqno = 0; in hw_init()
1910 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); in hw_init()
1911 OUT_RING(gpu->rb[0], 0x00000000); in hw_init()
1913 a6xx_flush(gpu, gpu->rb[0]); in hw_init()
1914 if (!a6xx_idle(gpu, gpu->rb[0])) in hw_init()
1925 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); in hw_init()
1926 ret = 0; in hw_init()
1977 for (i = 0; i < 8; i++) in a6xx_recover()
2003 gpu->active_submits = 0; in a6xx_recover()
2064 /* For mid=2 the source is TP or VFD except when the client id is 0 */ in a6xx_uche_fault_block()
2066 return ((val & 7) == 0) ? "TP" : "TP|VFD"; in a6xx_uche_fault_block()
2074 if (id == 0) in a6xx_fault_block()
2098 block = a6xx_fault_block(gpu, info->fsynr1 & 0xff); in a6xx_fault_handler()
2113 "CP | opcode error | possible opcode=0x%8.8X\n", in a6xx_cp_hw_err_irq()
2122 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n", in a6xx_cp_hw_err_irq()
2129 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n", in a6xx_cp_hw_err_irq()
2131 (val & 0x3ffff), val); in a6xx_cp_hw_err_irq()
2169 ring ? ring->id : -1, ring ? ring->fctx->last_fence : 0, in a6xx_fault_detect_irq()
2228 u32 cntl1_regval = 0; in a6xx_llc_activate()
2236 gpu_scid &= 0x1f; in a6xx_llc_activate()
2237 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) | in a6xx_llc_activate()
2244 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) | in a6xx_llc_activate()
2256 gpuhtw_scid &= 0x1f; in a6xx_llc_activate()
2277 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03); in a6xx_llc_activate()
2281 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval); in a6xx_llc_activate()
2295 gpu_scid &= GENMASK(4, 0); in a7xx_llc_activate()
2303 FIELD_PREP(GENMASK(4, 0), gpu_scid)); in a7xx_llc_activate()
2336 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0); in a6xx_llc_slices_init()
2353 #define GBIF_CLIENT_HALT_MASK BIT(0)
2355 #define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0)
2356 #define VBIF_RESET_ACK_MASK 0xF0
2357 #define GPR0_GBIF_HALT_REQUEST 0x1E0
2371 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); in a6xx_bus_clear_pending_transactions()
2393 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); in a6xx_bus_clear_pending_transactions()
2420 trace_msm_gpu_resume(0); in a6xx_gmu_pm_resume()
2446 trace_msm_gpu_resume(0); in a6xx_pm_resume()
2492 trace_msm_gpu_suspend(0); in a6xx_gmu_pm_suspend()
2505 for (i = 0; i < gpu->nr_rings; i++) in a6xx_gmu_pm_suspend()
2506 a6xx_gpu->shadow[i] = 0; in a6xx_gmu_pm_suspend()
2510 return 0; in a6xx_gmu_pm_suspend()
2520 trace_msm_gpu_suspend(0); in a6xx_pm_suspend()
2541 for (i = 0; i < gpu->nr_rings; i++) in a6xx_pm_suspend()
2542 a6xx_gpu->shadow[i] = 0; in a6xx_pm_suspend()
2546 return 0; in a6xx_pm_suspend()
2565 return 0; in a6xx_gmu_get_timestamp()
2571 return 0; in a6xx_get_timestamp()
2638 unsigned long quirks = 0; in a6xx_create_address_space()
2662 "gpu", 0x100000000ULL, in a6xx_create_private_address_space()
2715 for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) in fuse_to_supp_hw()
2734 return 0; in a6xx_set_supported_hw()
2747 supp_hw = BIT(0); /* Default */ in a6xx_set_supported_hw()
2754 return 0; in a6xx_set_supported_hw()
2872 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); in a6xx_gpu_init()