Lines Matching +full:0 +full:x00800000

51 #define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__MASK		0x00800000
57 #define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__MASK 0x40000000
63 #define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__MASK 0x00400000
69 #define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__MASK 0x40000000
75 #define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__MASK 0x40000000
81 #define A6XX_GMU_OOB_DCVS_SET_MASK__MASK 0x00800000
87 #define A6XX_GMU_OOB_DCVS_CHECK_MASK__MASK 0x80000000
93 #define A6XX_GMU_OOB_DCVS_CLEAR_MASK__MASK 0x80000000
99 #define A6XX_GMU_OOB_GPU_SET_MASK__MASK 0x00040000
105 #define A6XX_GMU_OOB_GPU_CHECK_MASK__MASK 0x04000000
111 #define A6XX_GMU_OOB_GPU_CLEAR_MASK__MASK 0x04000000
117 #define A6XX_GMU_OOB_PERFCNTR_SET_MASK__MASK 0x00020000
123 #define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__MASK 0x02000000
129 #define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__MASK 0x02000000
135 #define A6XX_HFI_IRQ_MSGQ_MASK 0x00000001
136 #define A6XX_HFI_IRQ_DSGQ_MASK__MASK 0x00000002
142 #define A6XX_HFI_IRQ_BLOCKED_MSG_MASK__MASK 0x00000004
148 #define A6XX_HFI_IRQ_CM3_FAULT_MASK__MASK 0x00800000
154 #define A6XX_HFI_IRQ_GMU_ERR_MASK__MASK 0x007f0000
160 #define A6XX_HFI_IRQ_OOB_MASK__MASK 0xff000000
166 #define A6XX_HFI_H2F_IRQ_MASK_BIT 0x00000001
167 #define REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL 0x00000080
169 #define REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL 0x00000081
171 #define REG_A6XX_GMU_CM3_ITCM_START 0x00000c00
173 #define REG_A6XX_GMU_CM3_DTCM_START 0x00001c00
175 #define REG_A6XX_GMU_NMI_CONTROL_STATUS 0x000023f0
177 #define REG_A6XX_GMU_BOOT_SLUMBER_OPTION 0x000023f8
179 #define REG_A6XX_GMU_GX_VOTE_IDX 0x000023f9
181 #define REG_A6XX_GMU_MX_VOTE_IDX 0x000023fa
183 #define REG_A6XX_GMU_DCVS_ACK_OPTION 0x000023fc
185 #define REG_A6XX_GMU_DCVS_PERF_SETTING 0x000023fd
187 #define REG_A6XX_GMU_DCVS_BW_SETTING 0x000023fe
189 #define REG_A6XX_GMU_DCVS_RETURN 0x000023ff
191 #define REG_A6XX_GMU_ICACHE_CONFIG 0x00004c00
193 #define REG_A6XX_GMU_DCACHE_CONFIG 0x00004c01
195 #define REG_A6XX_GMU_SYS_BUS_CONFIG 0x00004c0f
197 #define REG_A6XX_GMU_CM3_SYSRESET 0x00005000
199 #define REG_A6XX_GMU_CM3_BOOT_CONFIG 0x00005001
201 #define REG_A6XX_GMU_CM3_FW_BUSY 0x0000501a
203 #define REG_A6XX_GMU_CM3_FW_INIT_RESULT 0x0000501c
205 #define REG_A6XX_GMU_CM3_CFG 0x0000502d
207 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE 0x00005040
209 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0 0x00005041
211 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1 0x00005042
213 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L 0x00005044
215 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H 0x00005045
217 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L 0x00005046
219 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H 0x00005047
221 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L 0x00005048
223 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H 0x00005049
225 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L 0x0000504a
227 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H 0x0000504b
229 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L 0x0000504c
231 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H 0x0000504d
233 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L 0x0000504e
235 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H 0x0000504f
237 #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL 0x000050c0
238 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE 0x00000001
239 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE 0x00000002
240 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE 0x00000004
241 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK 0x00003c00
247 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK 0xffffc000
254 #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST 0x000050c1
256 #define REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST 0x000050c2
258 #define REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS 0x000050d0
259 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF 0x00000001
260 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON 0x00000002
261 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF 0x00000004
262 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON 0x00000008
263 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF 0x00000010
264 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE 0x00000020
265 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF 0x00000040
266 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF 0x00000080
268 #define REG_A6XX_GMU_GPU_NAP_CTRL 0x000050e4
269 #define A6XX_GMU_GPU_NAP_CTRL_HW_NAP_ENABLE 0x00000001
270 #define A6XX_GMU_GPU_NAP_CTRL_SID__MASK 0x000001f0
277 #define REG_A6XX_GMU_RPMH_CTRL 0x000050e8
278 #define A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE 0x00000001
279 #define A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE 0x00000010
280 #define A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE 0x00000100
281 #define A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE 0x00000200
282 #define A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE 0x00000400
283 #define A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE 0x00000800
284 #define A6XX_GMU_RPMH_CTRL_DDR_MIN_VOTE_ENABLE 0x00001000
285 #define A6XX_GMU_RPMH_CTRL_MX_MIN_VOTE_ENABLE 0x00002000
286 #define A6XX_GMU_RPMH_CTRL_CX_MIN_VOTE_ENABLE 0x00004000
287 #define A6XX_GMU_RPMH_CTRL_GFX_MIN_VOTE_ENABLE 0x00008000
289 #define REG_A6XX_GMU_RPMH_HYST_CTRL 0x000050e9
291 #define REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE 0x000050ec
293 #define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x000050f0
295 #define REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF 0x000050f1
297 #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG 0x00005100
299 #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP 0x00005101
301 #define REG_A6XX_GMU_BOOT_KMD_LM_HANDSHAKE 0x000051f0
303 #define REG_A6XX_GMU_LLM_GLM_SLEEP_CTRL 0x00005157
305 #define REG_A6XX_GMU_LLM_GLM_SLEEP_STATUS 0x00005158
307 #define REG_A6XX_GMU_ALWAYS_ON_COUNTER_L 0x00005088
309 #define REG_A6XX_GMU_ALWAYS_ON_COUNTER_H 0x00005089
311 #define REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE 0x000050c3
313 #define REG_A6XX_GMU_HFI_CTRL_STATUS 0x00005180
315 #define REG_A6XX_GMU_HFI_VERSION_INFO 0x00005181
317 #define REG_A6XX_GMU_HFI_SFR_ADDR 0x00005182
319 #define REG_A6XX_GMU_HFI_MMAP_ADDR 0x00005183
321 #define REG_A6XX_GMU_HFI_QTBL_INFO 0x00005184
323 #define REG_A6XX_GMU_HFI_QTBL_ADDR 0x00005185
325 #define REG_A6XX_GMU_HFI_CTRL_INIT 0x00005186
327 #define REG_A6XX_GMU_GMU2HOST_INTR_SET 0x00005190
329 #define REG_A6XX_GMU_GMU2HOST_INTR_CLR 0x00005191
331 #define REG_A6XX_GMU_GMU2HOST_INTR_INFO 0x00005192
332 #define A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ 0x00000001
333 #define A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT 0x00800000
335 #define REG_A6XX_GMU_GMU2HOST_INTR_MASK 0x00005193
337 #define REG_A6XX_GMU_HOST2GMU_INTR_SET 0x00005194
339 #define REG_A6XX_GMU_HOST2GMU_INTR_CLR 0x00005195
341 #define REG_A6XX_GMU_HOST2GMU_INTR_RAW_INFO 0x00005196
343 #define REG_A6XX_GMU_HOST2GMU_INTR_EN_0 0x00005197
345 #define REG_A6XX_GMU_HOST2GMU_INTR_EN_1 0x00005198
347 #define REG_A6XX_GMU_HOST2GMU_INTR_EN_2 0x00005199
349 #define REG_A6XX_GMU_HOST2GMU_INTR_EN_3 0x0000519a
351 #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_0 0x0000519b
353 #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_1 0x0000519c
355 #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_2 0x0000519d
357 #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_3 0x0000519e
359 #define REG_A6XX_GMU_GENERAL_1 0x000051c6
361 #define REG_A6XX_GMU_GENERAL_7 0x000051cc
363 #define REG_A6XX_GMU_GENERAL_8 0x000051cd
365 #define REG_A6XX_GMU_GENERAL_9 0x000051ce
367 #define REG_A6XX_GMU_GENERAL_10 0x000051cf
369 #define REG_A6XX_GMU_ISENSE_CTRL 0x0000515d
371 #define REG_A6XX_GPU_CS_ENABLE_REG 0x00008920
373 #define REG_A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL 0x0000515d
375 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL3 0x00008578
377 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL2 0x00008558
379 #define REG_A6XX_GPU_CS_A_SENSOR_CTRL_0 0x00008580
381 #define REG_A6XX_GPU_CS_A_SENSOR_CTRL_2 0x00027ada
383 #define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a
385 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x00008957
387 #define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a
389 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000881d
391 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000881f
393 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x00008821
395 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965
397 #define REG_A6XX_GPU_CS_AMP_PERIOD_CTRL 0x0000896d
399 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965
401 #define REG_A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD 0x0000514d
403 #define REG_A6XX_GMU_AO_INTERRUPT_EN 0x00009303
405 #define REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR 0x00009304
407 #define REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS 0x00009305
408 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE 0x00000001
409 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_RSCC_COMP 0x00000002
410 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_VDROOP 0x00000004
411 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR 0x00000008
412 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_DBD_WAKEUP 0x00000010
413 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR 0x00000020
415 #define REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK 0x00009306
417 #define REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL 0x00009309
419 #define REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL 0x0000930a
421 #define REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL 0x0000930b
423 #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS 0x0000930c
424 #define A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB 0x00800000
426 #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2 0x0000930d
428 #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK 0x0000930e
430 #define REG_A6XX_GMU_AO_AHB_FENCE_CTRL 0x00009310
432 #define REG_A6XX_GMU_AHB_FENCE_STATUS 0x00009313
434 #define REG_A6XX_GMU_AHB_FENCE_STATUS_CLR 0x00009314
436 #define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x00009315
438 #define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316
440 #define REG_A6XX_GMU_RSCC_CONTROL_REQ 0x00009307
442 #define REG_A6XX_GMU_RSCC_CONTROL_ACK 0x00009308
444 #define REG_A6XX_GMU_AHB_FENCE_RANGE_0 0x00009311
446 #define REG_A6XX_GMU_AHB_FENCE_RANGE_1 0x00009312
448 #define REG_A6XX_GPU_CC_GX_GDSCR 0x00009c03
450 #define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42
452 #define REG_A6XX_GPU_CPR_FSM_CTL 0x0000c001
454 #define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00000004
456 #define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00000008
458 #define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO 0x00000009
460 #define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI 0x0000000a
462 #define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0 0x0000000b
464 #define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR 0x0000000d
466 #define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA 0x0000000e
468 #define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0 0x00000082
470 #define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0 0x00000083
472 #define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0 0x00000089
474 #define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0 0x0000008c
476 #define REG_A6XX_RSCC_OVERRIDE_START_ADDR 0x00000100
478 #define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00000101
480 #define REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740 0x00000154
482 #define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00000180
484 #define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00000346
486 #define REG_A6XX_RSCC_TCS1_DRV0_STATUS 0x000003ee
488 #define REG_A6XX_RSCC_TCS2_DRV0_STATUS 0x00000496
490 #define REG_A6XX_RSCC_TCS3_DRV0_STATUS 0x0000053e