36 	for (i = 0; i < submit->nr_cmds; i++) {  in a3xx_submit()
67 	OUT_RING(ring, 0x00000000);  in a3xx_submit()
75 #if 0  in a3xx_submit()
79 	OUT_RING(ring, 0x00000000);  in a3xx_submit()
87 	struct msm_ringbuffer *ring = gpu->rb[0];  in a3xx_me_init()
90 	OUT_RING(ring, 0x000003f7);  in a3xx_me_init()
91 	OUT_RING(ring, 0x00000000);  in a3xx_me_init()
92 	OUT_RING(ring, 0x00000000);  in a3xx_me_init()
93 	OUT_RING(ring, 0x00000000);  in a3xx_me_init()
94 	OUT_RING(ring, 0x00000080);  in a3xx_me_init()
95 	OUT_RING(ring, 0x00000100);  in a3xx_me_init()
96 	OUT_RING(ring, 0x00000180);  in a3xx_me_init()
97 	OUT_RING(ring, 0x00006600);  in a3xx_me_init()
98 	OUT_RING(ring, 0x00000150);  in a3xx_me_init()
99 	OUT_RING(ring, 0x0000014e);  in a3xx_me_init()
100 	OUT_RING(ring, 0x00000154);  in a3xx_me_init()
101 	OUT_RING(ring, 0x00000001);  in a3xx_me_init()
102 	OUT_RING(ring, 0x00000000);  in a3xx_me_init()
103 	OUT_RING(ring, 0x00000000);  in a3xx_me_init()
104 	OUT_RING(ring, 0x00000000);  in a3xx_me_init()
105 	OUT_RING(ring, 0x00000000);  in a3xx_me_init()
106 	OUT_RING(ring, 0x00000000);  in a3xx_me_init()
123 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);  in a3xx_hw_init()
124 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010);  in a3xx_hw_init()
125 		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010);  in a3xx_hw_init()
126 		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010);  in a3xx_hw_init()
127 		gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);  in a3xx_hw_init()
128 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010);  in a3xx_hw_init()
129 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010);  in a3xx_hw_init()
131 		gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff);  in a3xx_hw_init()
133 		gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);  in a3xx_hw_init()
135 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);  in a3xx_hw_init()
136 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);  in a3xx_hw_init()
138 		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);  in a3xx_hw_init()
139 		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a);  in a3xx_hw_init()
140 		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000a);  in a3xx_hw_init()
143 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);  in a3xx_hw_init()
144 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010);  in a3xx_hw_init()
145 		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010);  in a3xx_hw_init()
146 		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010);  in a3xx_hw_init()
147 		gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);  in a3xx_hw_init()
148 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010);  in a3xx_hw_init()
149 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010);  in a3xx_hw_init()
151 		gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff);  in a3xx_hw_init()
153 		gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);  in a3xx_hw_init()
155 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);  in a3xx_hw_init()
156 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);  in a3xx_hw_init()
158 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x000000ff);  in a3xx_hw_init()
159 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);  in a3xx_hw_init()
168 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f);  in a3xx_hw_init()
169 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);  in a3xx_hw_init()
171 		gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f);  in a3xx_hw_init()
172 		gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);  in a3xx_hw_init()
174 		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);  in a3xx_hw_init()
178 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);  in a3xx_hw_init()
179 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x18181818);  in a3xx_hw_init()
180 		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x18181818);  in a3xx_hw_init()
181 		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x18181818);  in a3xx_hw_init()
182 		gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);  in a3xx_hw_init()
183 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x18181818);  in a3xx_hw_init()
184 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x18181818);  in a3xx_hw_init()
186 		gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f);  in a3xx_hw_init()
188 		gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);  in a3xx_hw_init()
190 		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0001);  in a3xx_hw_init()
192 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003f);  in a3xx_hw_init()
193 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003f003f);  in a3xx_hw_init()
195 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f);  in a3xx_hw_init()
196 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);  in a3xx_hw_init()
200 		gpu_write(gpu, REG_A3XX_VBIF_CLKON, 0x00000001);  in a3xx_hw_init()
207 	gpu_write(gpu, REG_A3XX_RBBM_GPU_BUSY_MASKED, 0xffffffff);  in a3xx_hw_init()
210 	gpu_write(gpu, REG_A3XX_RBBM_SP_HYST_CNT, 0x10);  in a3xx_hw_init()
211 	gpu_write(gpu, REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10);  in a3xx_hw_init()
216 	gpu_write(gpu, REG_A3XX_RBBM_AHB_CTL0, 0x00000001);  in a3xx_hw_init()
219 	gpu_write(gpu, REG_A3XX_RBBM_AHB_CTL1, 0xa6ffffff);  in a3xx_hw_init()
222 	gpu_write(gpu, REG_A3XX_RBBM_RBBM_CTL, 0x00030000);  in a3xx_hw_init()
227 	gpu_write(gpu, REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL, 0x00010fff);  in a3xx_hw_init()
229 	/* Enable 64-byte cacheline size. HW Default is 32-byte (0x000000E0): */  in a3xx_hw_init()
230 	gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);  in a3xx_hw_init()
234 		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);  in a3xx_hw_init()
236 		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);  in a3xx_hw_init()
238 		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);  in a3xx_hw_init()
240 		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbffcffff);  in a3xx_hw_init()
243 		gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x05515455);  in a3xx_hw_init()
245 		gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x00000000);  in a3xx_hw_init()
254 	gpu_write(gpu, REG_A3XX_RBBM_PERFCTR_CTL, 0x01);  in a3xx_hw_init()
257 	for (i = 0; i < gpu->num_perfcntrs; i++) {  in a3xx_hw_init()
276 	gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));  in a3xx_hw_init()
279 	gpu_write(gpu, REG_A3XX_CP_PROTECT_CTRL, 0x00000007);  in a3xx_hw_init()
282 	gpu_write(gpu, REG_A3XX_CP_PROTECT(0), 0x63000040);  in a3xx_hw_init()
283 	gpu_write(gpu, REG_A3XX_CP_PROTECT(1), 0x62000080);  in a3xx_hw_init()
284 	gpu_write(gpu, REG_A3XX_CP_PROTECT(2), 0x600000cc);  in a3xx_hw_init()
285 	gpu_write(gpu, REG_A3XX_CP_PROTECT(3), 0x60000108);  in a3xx_hw_init()
286 	gpu_write(gpu, REG_A3XX_CP_PROTECT(4), 0x64000140);  in a3xx_hw_init()
287 	gpu_write(gpu, REG_A3XX_CP_PROTECT(5), 0x66000400);  in a3xx_hw_init()
290 	gpu_write(gpu, REG_A3XX_CP_PROTECT(6), 0x65000700);  in a3xx_hw_init()
291 	gpu_write(gpu, REG_A3XX_CP_PROTECT(7), 0x610007d8);  in a3xx_hw_init()
292 	gpu_write(gpu, REG_A3XX_CP_PROTECT(8), 0x620007e0);  in a3xx_hw_init()
293 	gpu_write(gpu, REG_A3XX_CP_PROTECT(9), 0x61001178);  in a3xx_hw_init()
294 	gpu_write(gpu, REG_A3XX_CP_PROTECT(10), 0x64001180);  in a3xx_hw_init()
297 	gpu_write(gpu, REG_A3XX_CP_PROTECT(11), 0x60003300);  in a3xx_hw_init()
300 	gpu_write(gpu, REG_A3XX_CP_PROTECT(12), 0x6b00c000);  in a3xx_hw_init()
316 	gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0);  in a3xx_hw_init()
325 	gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_ADDR, 0);  in a3xx_hw_init()
342 		gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x003e2008);  in a3xx_hw_init()
346 	gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0);  in a3xx_hw_init()
348 	return a3xx_me_init(gpu) ? 0 : -EINVAL;  in a3xx_hw_init()
357 	for (i = 0; i < 8; i++) {  in a3xx_recover()
368 	gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 0);  in a3xx_recover()
389 	if (!adreno_idle(gpu, gpu->rb[0]))  in a3xx_idle()
421 	0x0000, 0x0002, 0x0010, 0x0012, 0x0018, 0x0018, 0x0020, 0x0027,
422 	0x0029, 0x002b, 0x002e, 0x0033, 0x0040, 0x0042, 0x0050, 0x005c,
423 	0x0060, 0x006c, 0x0080, 0x0082, 0x0084, 0x0088, 0x0090, 0x00e5,
424 	0x00ea, 0x00ed, 0x0100, 0x0100, 0x0110, 0x0123, 0x01c0, 0x01c1,
425 	0x01c3, 0x01c5, 0x01c7, 0x01c7, 0x01d5, 0x01d9, 0x01dc, 0x01dd,
426 	0x01ea, 0x01ea, 0x01ee, 0x01f1, 0x01f5, 0x01f5, 0x01fc, 0x01ff,
427 	0x0440, 0x0440, 0x0443, 0x0443, 0x0445, 0x0445, 0x044d, 0x044f,
428 	0x0452, 0x0452, 0x0454, 0x046f, 0x047c, 0x047c, 0x047f, 0x047f,
429 	0x0578, 0x057f, 0x0600, 0x0602, 0x0605, 0x0607, 0x060a, 0x060e,
430 	0x0612, 0x0614, 0x0c01, 0x0c02, 0x0c06, 0x0c1d, 0x0c3d, 0x0c3f,
431 	0x0c48, 0x0c4b, 0x0c80, 0x0c80, 0x0c88, 0x0c8b, 0x0ca0, 0x0cb7,
432 	0x0cc0, 0x0cc1, 0x0cc6, 0x0cc7, 0x0ce4, 0x0ce5, 0x0e00, 0x0e05,
433 	0x0e0c, 0x0e0c, 0x0e22, 0x0e23, 0x0e41, 0x0e45, 0x0e64, 0x0e65,
434 	0x0e80, 0x0e82, 0x0e84, 0x0e89, 0x0ea0, 0x0ea1, 0x0ea4, 0x0ea7,
435 	0x0ec4, 0x0ecb, 0x0ee0, 0x0ee0, 0x0f00, 0x0f01, 0x0f03, 0x0f09,
436 	0x2040, 0x2040, 0x2044, 0x2044, 0x2048, 0x204d, 0x2068, 0x2069,
437 	0x206c, 0x206d, 0x2070, 0x2070, 0x2072, 0x2072, 0x2074, 0x2075,
438 	0x2079, 0x207a, 0x20c0, 0x20d3, 0x20e4, 0x20ef, 0x2100, 0x2109,
439 	0x210c, 0x210c, 0x210e, 0x210e, 0x2110, 0x2111, 0x2114, 0x2115,
440 	0x21e4, 0x21e4, 0x21ea, 0x21ea, 0x21ec, 0x21ed, 0x21f0, 0x21f0,
441 	0x2200, 0x2212, 0x2214, 0x2217, 0x221a, 0x221a, 0x2240, 0x227e,
442 	0x2280, 0x228b, 0x22c0, 0x22c0, 0x22c4, 0x22ce, 0x22d0, 0x22d8,
443 	0x22df, 0x22e6, 0x22e8, 0x22e9, 0x22ec, 0x22ec, 0x22f0, 0x22f7,
444 	0x22ff, 0x22ff, 0x2340, 0x2343, 0x2440, 0x2440, 0x2444, 0x2444,
445 	0x2448, 0x244d, 0x2468, 0x2469, 0x246c, 0x246d, 0x2470, 0x2470,
446 	0x2472, 0x2472, 0x2474, 0x2475, 0x2479, 0x247a, 0x24c0, 0x24d3,
447 	0x24e4, 0x24ef, 0x2500, 0x2509, 0x250c, 0x250c, 0x250e, 0x250e,
448 	0x2510, 0x2511, 0x2514, 0x2515, 0x25e4, 0x25e4, 0x25ea, 0x25ea,
449 	0x25ec, 0x25ed, 0x25f0, 0x25f0, 0x2600, 0x2612, 0x2614, 0x2617,
450 	0x261a, 0x261a, 0x2640, 0x267e, 0x2680, 0x268b, 0x26c0, 0x26c0,
451 	0x26c4, 0x26ce, 0x26d0, 0x26d8, 0x26df, 0x26e6, 0x26e8, 0x26e9,
452 	0x26ec, 0x26ec, 0x26f0, 0x26f7, 0x26ff, 0x26ff, 0x2740, 0x2743,
453 	0x300c, 0x300e, 0x301c, 0x301d, 0x302a, 0x302a, 0x302c, 0x302d,
454 	0x3030, 0x3031, 0x3034, 0x3036, 0x303c, 0x303c, 0x305e, 0x305f,
455 	~0   /* sentinel */
605 	icc_set_bw(icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);  in a3xx_gpu_init()
606 	icc_set_bw(ocmem_icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);  in a3xx_gpu_init()