Lines Matching +full:gce +full:- +full:events
1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <linux/soc/mediatek/mtk-cmdq.h>
46 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n))
47 #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04)
48 #define DISP_REG_OVL_HDR_PITCH(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x08)
61 #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
63 #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
117 * struct mtk_disp_ovl - DISP_OVL driver structure
118 * @crtc: associated crtc to report vblank events to
136 writel(0x0, priv->regs + DISP_REG_OVL_INTSTA); in mtk_disp_ovl_irq_handler()
138 if (!priv->vblank_cb) in mtk_disp_ovl_irq_handler()
141 priv->vblank_cb(priv->vblank_cb_data); in mtk_disp_ovl_irq_handler()
152 ovl->vblank_cb = vblank_cb; in mtk_ovl_register_vblank_cb()
153 ovl->vblank_cb_data = vblank_cb_data; in mtk_ovl_register_vblank_cb()
160 ovl->vblank_cb = NULL; in mtk_ovl_unregister_vblank_cb()
161 ovl->vblank_cb_data = NULL; in mtk_ovl_unregister_vblank_cb()
168 writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA); in mtk_ovl_enable_vblank()
169 writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN); in mtk_ovl_enable_vblank()
176 writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN); in mtk_ovl_disable_vblank()
183 return ovl->data->formats; in mtk_ovl_get_formats()
190 return ovl->data->num_formats; in mtk_ovl_get_num_formats()
197 return clk_prepare_enable(ovl->clk); in mtk_ovl_clk_enable()
204 clk_disable_unprepare(ovl->clk); in mtk_ovl_clk_disable()
211 if (ovl->data->smi_id_en) { in mtk_ovl_start()
214 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); in mtk_ovl_start()
216 writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); in mtk_ovl_start()
218 writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN); in mtk_ovl_start()
225 writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN); in mtk_ovl_stop()
226 if (ovl->data->smi_id_en) { in mtk_ovl_stop()
229 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); in mtk_ovl_stop()
231 writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); in mtk_ovl_stop()
239 &ovl->cmdq_reg, ovl->regs, in mtk_ovl_set_afbc()
250 if (!ovl->data->supports_clrfmt_ext) in mtk_ovl_set_bit_depth()
253 reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); in mtk_ovl_set_bit_depth()
263 mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg, in mtk_ovl_set_bit_depth()
264 ovl->regs, DISP_REG_OVL_CLRFMT_EXT); in mtk_ovl_set_bit_depth()
274 mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_config()
276 mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR); in mtk_ovl_config()
278 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); in mtk_ovl_config()
279 mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); in mtk_ovl_config()
286 return ovl->data->layer_nr; in mtk_ovl_layer_nr()
298 struct drm_plane_state *state = &mtk_state->base; in mtk_ovl_layer_check()
301 rotation = drm_rotation_simplify(state->rotation, in mtk_ovl_layer_check()
309 return -EINVAL; in mtk_ovl_layer_check()
315 if (state->fb->format->is_yuv && rotation != 0) in mtk_ovl_layer_check()
316 return -EINVAL; in mtk_ovl_layer_check()
318 state->rotation = rotation; in mtk_ovl_layer_check()
331 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_on()
334 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); in mtk_ovl_layer_on()
336 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); in mtk_ovl_layer_on()
337 if (ovl->data->gmc_bits == 10) in mtk_ovl_layer_on()
343 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx)); in mtk_ovl_layer_on()
344 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_on()
353 mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_off()
355 mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_off()
402 struct mtk_plane_pending_state *pending = &state->pending; in mtk_ovl_layer_config()
403 unsigned int addr = pending->addr; in mtk_ovl_layer_config()
404 unsigned int hdr_addr = pending->hdr_addr; in mtk_ovl_layer_config()
405 unsigned int pitch = pending->pitch; in mtk_ovl_layer_config()
406 unsigned int hdr_pitch = pending->hdr_pitch; in mtk_ovl_layer_config()
407 unsigned int fmt = pending->format; in mtk_ovl_layer_config()
408 unsigned int offset = (pending->y << 16) | pending->x; in mtk_ovl_layer_config()
409 unsigned int src_size = (pending->height << 16) | pending->width; in mtk_ovl_layer_config()
411 bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR; in mtk_ovl_layer_config()
422 if (!pending->enable) { in mtk_ovl_layer_config()
428 if (state->base.fb && state->base.fb->format->has_alpha) in mtk_ovl_layer_config()
431 if (pending->rotation & DRM_MODE_REFLECT_Y) { in mtk_ovl_layer_config()
433 addr += (pending->height - 1) * pending->pitch; in mtk_ovl_layer_config()
436 if (pending->rotation & DRM_MODE_REFLECT_X) { in mtk_ovl_layer_config()
438 addr += pending->pitch - 1; in mtk_ovl_layer_config()
441 if (ovl->data->supports_afbc) in mtk_ovl_layer_config()
444 mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_config()
446 mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_config()
448 mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_config()
450 mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_config()
452 mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_config()
456 mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_config()
460 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx)); in mtk_ovl_layer_config()
461 mtk_ddp_write_relaxed(cmdq_pkt, hdr_pitch, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_config()
466 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx)); in mtk_ovl_layer_config()
478 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); in mtk_ovl_bgclr_in_on()
480 writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); in mtk_ovl_bgclr_in_on()
488 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); in mtk_ovl_bgclr_in_off()
490 writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); in mtk_ovl_bgclr_in_off()
511 struct device *dev = &pdev->dev; in mtk_disp_ovl_probe()
519 return -ENOMEM; in mtk_disp_ovl_probe()
525 priv->clk = devm_clk_get(dev, NULL); in mtk_disp_ovl_probe()
526 if (IS_ERR(priv->clk)) { in mtk_disp_ovl_probe()
528 return PTR_ERR(priv->clk); in mtk_disp_ovl_probe()
532 priv->regs = devm_ioremap_resource(dev, res); in mtk_disp_ovl_probe()
533 if (IS_ERR(priv->regs)) { in mtk_disp_ovl_probe()
535 return PTR_ERR(priv->regs); in mtk_disp_ovl_probe()
538 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); in mtk_disp_ovl_probe()
540 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); in mtk_disp_ovl_probe()
543 priv->data = of_device_get_match_data(dev); in mtk_disp_ovl_probe()
566 component_del(&pdev->dev, &mtk_disp_ovl_component_ops); in mtk_disp_ovl_remove()
567 pm_runtime_disable(&pdev->dev); in mtk_disp_ovl_remove()
639 { .compatible = "mediatek,mt2701-disp-ovl",
641 { .compatible = "mediatek,mt8173-disp-ovl",
643 { .compatible = "mediatek,mt8183-disp-ovl",
645 { .compatible = "mediatek,mt8183-disp-ovl-2l",
647 { .compatible = "mediatek,mt8192-disp-ovl",
649 { .compatible = "mediatek,mt8192-disp-ovl-2l",
651 { .compatible = "mediatek,mt8195-disp-ovl",
661 .name = "mediatek-disp-ovl",