drm/loongson/lsdc_drv.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
26 /* Currently, all Loongson display controllers have two display pipes. */
31  * Loongson 3 series processors, they are equipped with on-board video RAM
37  * display pipe 0 = crtc0 + dvo0 + encoder0 + connector0 + cursor0 + primary0
38  * display pipe 1 = crtc1 + dvo1 + encoder1 + connectro1 + cursor1 + primary1
69 /* GFX related resources wrangler */
82 	/* Pixel PLL, per display pipe */
103 /* crtc hardware related ops */
135 /* primary plane hardware related ops */
152 /* cursor plane hardware related ops */
296 	/* @num_output: count the number of active display pipe */
348 	return readl(ldev->reg_base + offset);  in lsdc_rreg32()
353 	writel(val, ldev->reg_base + offset);  in lsdc_wreg32()
360 	void __iomem *addr = ldev->reg_base + offset;  in lsdc_ureg32_set()
370 	void __iomem *addr = ldev->reg_base + offset;  in lsdc_ureg32_clr()
379 	return readl(ldev->reg_base + offset + pipe * CRTC_PIPE_OFFSET);  in lsdc_pipe_rreg32()
385 	writel(val, ldev->reg_base + offset + pipe * CRTC_PIPE_OFFSET);  in lsdc_pipe_wreg32()