Lines Matching defs:rogue_fwif_sysinit
1840 struct rogue_fwif_sysinit { struct
1842 aligned_u64 fault_phys_addr;
1845 aligned_u64 pds_exec_base;
1847 aligned_u64 usc_exec_base;
1849 aligned_u64 fbcdc_state_table_base;
1850 aligned_u64 fbcdc_large_state_table_base;
1852 aligned_u64 texture_heap_base;
1855 u64 hw_perf_filter;
1857 aligned_u64 slc3_fence_dev_addr;
1859 u32 tpu_trilinear_frac_mask[ROGUE_FWIF_TPU_DM_LAST] __aligned(8);
1862 struct rogue_fwif_sigbuf_ctl sigbuf_ctl[PVR_FWIF_DM_MAX];
1864 struct rogue_fwif_pdvfs_opp pdvfs_opp_info;
1866 struct rogue_fwif_dma_addr coremem_data_store;
1868 struct rogue_fwif_counter_dump_ctl counter_dump_ctl;
1870 u32 filter_flags;
1872 u32 runtime_cfg_fw_addr;
1874 u32 trace_buf_ctl_fw_addr;
1875 u32 fw_sys_data_fw_addr;
1877 u32 gpu_util_fw_cb_ctl_fw_addr;
1878 u32 reg_cfg_fw_addr;
1879 u32 hwperf_ctl_fw_addr;
1881 u32 align_checks;
1884 u32 initial_core_clock_speed;
1887 u32 active_pm_latency_ms;
1893 u32 marker_val;
1896 u32 firmware_started_timestamp;
1898 u32 jones_disable_mask;
1901 enum fw_perf_conf firmware_perf;
1908 u32 core_clock_rate_fw_addr;
1910 enum rogue_fwif_gpio_val_mode gpio_validation_mode;
1913 struct rogue_hwperf_bvnc bvnc_km_feature_flags;
1916 u32 tfbc_compression_control;