140 static void chv_detect_mem_freq(struct drm_i915_private *i915)  in chv_detect_mem_freq()  argument
144 	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));  in chv_detect_mem_freq()
145 	val = vlv_cck_read(i915, CCK_FUSE_REG);  in chv_detect_mem_freq()
146 	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));  in chv_detect_mem_freq()
150 		i915->mem_freq = 2000;  in chv_detect_mem_freq()
153 		i915->mem_freq = 1600;  in chv_detect_mem_freq()
158 static void vlv_detect_mem_freq(struct drm_i915_private *i915)  in vlv_detect_mem_freq()  argument
162 	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));  in vlv_detect_mem_freq()
163 	val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);  in vlv_detect_mem_freq()
164 	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));  in vlv_detect_mem_freq()
169 		i915->mem_freq = 800;  in vlv_detect_mem_freq()
172 		i915->mem_freq = 1066;  in vlv_detect_mem_freq()
175 		i915->mem_freq = 1333;  in vlv_detect_mem_freq()
180 static void detect_mem_freq(struct drm_i915_private *i915)  in detect_mem_freq()  argument
182 	if (IS_PINEVIEW(i915))  in detect_mem_freq()
183 		pnv_detect_mem_freq(i915);  in detect_mem_freq()
184 	else if (GRAPHICS_VER(i915) == 5)  in detect_mem_freq()
185 		ilk_detect_mem_freq(i915);  in detect_mem_freq()
186 	else if (IS_CHERRYVIEW(i915))  in detect_mem_freq()
187 		chv_detect_mem_freq(i915);  in detect_mem_freq()
188 	else if (IS_VALLEYVIEW(i915))  in detect_mem_freq()
189 		vlv_detect_mem_freq(i915);  in detect_mem_freq()
191 	if (i915->mem_freq)  in detect_mem_freq()
192 		drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);  in detect_mem_freq()
274 skl_dram_get_dimm_info(struct drm_i915_private *i915,  in skl_dram_get_dimm_info()  argument
278 	if (GRAPHICS_VER(i915) >= 11) {  in skl_dram_get_dimm_info()
288 	drm_dbg_kms(&i915->drm,  in skl_dram_get_dimm_info()
295 skl_dram_get_channel_info(struct drm_i915_private *i915,  in skl_dram_get_channel_info()  argument
299 	skl_dram_get_dimm_info(i915, &ch->dimm_l,  in skl_dram_get_channel_info()
301 	skl_dram_get_dimm_info(i915, &ch->dimm_s,  in skl_dram_get_channel_info()
305 		drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel);  in skl_dram_get_channel_info()
319 	drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb DIMMs: %s\n",  in skl_dram_get_channel_info()
335 skl_dram_get_channels_info(struct drm_i915_private *i915)  in skl_dram_get_channels_info()  argument
337 	struct dram_info *dram_info = &i915->dram_info;  in skl_dram_get_channels_info()
342 	val = intel_uncore_read(&i915->uncore,  in skl_dram_get_channels_info()
344 	ret = skl_dram_get_channel_info(i915, &ch0, 0, val);  in skl_dram_get_channels_info()
348 	val = intel_uncore_read(&i915->uncore,  in skl_dram_get_channels_info()
350 	ret = skl_dram_get_channel_info(i915, &ch1, 1, val);  in skl_dram_get_channels_info()
355 		drm_info(&i915->drm, "Number of memory channels is zero\n");  in skl_dram_get_channels_info()
360 		drm_info(&i915->drm, "couldn't get memory rank information\n");  in skl_dram_get_channels_info()
368 	drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n",  in skl_dram_get_channels_info()
375 skl_get_dram_type(struct drm_i915_private *i915)  in skl_get_dram_type()  argument
379 	val = intel_uncore_read(&i915->uncore,  in skl_get_dram_type()
398 skl_get_dram_info(struct drm_i915_private *i915)  in skl_get_dram_info()  argument
400 	struct dram_info *dram_info = &i915->dram_info;  in skl_get_dram_info()
403 	dram_info->type = skl_get_dram_type(i915);  in skl_get_dram_info()
404 	drm_dbg_kms(&i915->drm, "DRAM type: %s\n",  in skl_get_dram_info()
407 	ret = skl_dram_get_channels_info(i915);  in skl_get_dram_info()
492 static int bxt_get_dram_info(struct drm_i915_private *i915)  in bxt_get_dram_info()  argument
494 	struct dram_info *dram_info = &i915->dram_info;  in bxt_get_dram_info()
506 		val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i));  in bxt_get_dram_info()
515 		drm_WARN_ON(&i915->drm, type != INTEL_DRAM_UNKNOWN &&  in bxt_get_dram_info()
519 		drm_dbg_kms(&i915->drm,  in bxt_get_dram_info()
533 		drm_info(&i915->drm, "couldn't get memory information\n");  in bxt_get_dram_info()
602 static int gen11_get_dram_info(struct drm_i915_private *i915)  in gen11_get_dram_info()  argument
604 	int ret = skl_get_dram_info(i915);  in gen11_get_dram_info()
609 	return icl_pcode_read_mem_global_info(i915);  in gen11_get_dram_info()
612 static int gen12_get_dram_info(struct drm_i915_private *i915)  in gen12_get_dram_info()  argument
614 	i915->dram_info.wm_lv_0_adjust_needed = false;  in gen12_get_dram_info()
616 	return icl_pcode_read_mem_global_info(i915);  in gen12_get_dram_info()
619 static int xelpdp_get_dram_info(struct drm_i915_private *i915)  in xelpdp_get_dram_info()  argument
621 	u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);  in xelpdp_get_dram_info()
622 	struct dram_info *dram_info = &i915->dram_info;  in xelpdp_get_dram_info()
655 void intel_dram_detect(struct drm_i915_private *i915)  in intel_dram_detect()  argument
657 	struct dram_info *dram_info = &i915->dram_info;  in intel_dram_detect()
660 	detect_mem_freq(i915);  in intel_dram_detect()
662 	if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915))  in intel_dram_detect()
669 	dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);  in intel_dram_detect()
671 	if (DISPLAY_VER(i915) >= 14)  in intel_dram_detect()
672 		ret = xelpdp_get_dram_info(i915);  in intel_dram_detect()
673 	else if (GRAPHICS_VER(i915) >= 12)  in intel_dram_detect()
674 		ret = gen12_get_dram_info(i915);  in intel_dram_detect()
675 	else if (GRAPHICS_VER(i915) >= 11)  in intel_dram_detect()
676 		ret = gen11_get_dram_info(i915);  in intel_dram_detect()
677 	else if (IS_GEN9_LP(i915))  in intel_dram_detect()
678 		ret = bxt_get_dram_info(i915);  in intel_dram_detect()
680 		ret = skl_get_dram_info(i915);  in intel_dram_detect()
684 	drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels);  in intel_dram_detect()
686 	drm_dbg_kms(&i915->drm, "Watermark level 0 adjustment needed: %s\n",  in intel_dram_detect()
690 static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)  in gen9_edram_size_mb()  argument
700 void intel_dram_edram_detect(struct drm_i915_private *i915)  in intel_dram_edram_detect()  argument
704 	if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9))  in intel_dram_edram_detect()
707 	edram_cap = intel_uncore_read_fw(&i915->uncore, HSW_EDRAM_CAP);  in intel_dram_edram_detect()
718 	if (GRAPHICS_VER(i915) < 9)  in intel_dram_edram_detect()
719 		i915->edram_size_mb = 128;  in intel_dram_edram_detect()
721 		i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap);  in intel_dram_edram_detect()
723 	drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb);  in intel_dram_edram_detect()