Lines Matching full:i915
45 void (*init_clock_gating)(struct drm_i915_private *i915);
48 static void gen9_init_clock_gating(struct drm_i915_private *i915) in gen9_init_clock_gating() argument
50 if (HAS_LLC(i915)) { in gen9_init_clock_gating()
58 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE); in gen9_init_clock_gating()
62 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP); in gen9_init_clock_gating()
65 intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM); in gen9_init_clock_gating()
71 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE); in gen9_init_clock_gating()
74 static void bxt_init_clock_gating(struct drm_i915_private *i915) in bxt_init_clock_gating() argument
76 gen9_init_clock_gating(i915); in bxt_init_clock_gating()
79 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); in bxt_init_clock_gating()
85 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); in bxt_init_clock_gating()
91 intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0, in bxt_init_clock_gating()
92 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | in bxt_init_clock_gating()
101 intel_uncore_write(&i915->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950)); in bxt_init_clock_gating()
107 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); in bxt_init_clock_gating()
113 intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0, DPFC_DISABLE_DUMMY0); in bxt_init_clock_gating()
116 static void glk_init_clock_gating(struct drm_i915_private *i915) in glk_init_clock_gating() argument
118 gen9_init_clock_gating(i915); in glk_init_clock_gating()
125 intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0, in glk_init_clock_gating()
126 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | in glk_init_clock_gating()
130 static void ibx_init_clock_gating(struct drm_i915_private *i915) in ibx_init_clock_gating() argument
137 intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); in ibx_init_clock_gating()
152 static void ilk_init_clock_gating(struct drm_i915_private *i915) in ilk_init_clock_gating() argument
164 intel_uncore_write(&i915->uncore, PCH_3DCGDIS0, in ilk_init_clock_gating()
167 intel_uncore_write(&i915->uncore, PCH_3DCGDIS1, in ilk_init_clock_gating()
177 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2, in ilk_init_clock_gating()
178 (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) | in ilk_init_clock_gating()
181 intel_uncore_write(&i915->uncore, DISP_ARB_CTL, in ilk_init_clock_gating()
182 (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) | in ilk_init_clock_gating()
192 if (IS_IRONLAKE_M(i915)) { in ilk_init_clock_gating()
194 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); in ilk_init_clock_gating()
195 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE); in ilk_init_clock_gating()
198 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate); in ilk_init_clock_gating()
200 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT); in ilk_init_clock_gating()
202 g4x_disable_trickle_feed(i915); in ilk_init_clock_gating()
204 ibx_init_clock_gating(i915); in ilk_init_clock_gating()
207 static void cpt_init_clock_gating(struct drm_i915_private *i915) in cpt_init_clock_gating() argument
217 intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | in cpt_init_clock_gating()
220 intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS); in cpt_init_clock_gating()
224 for_each_pipe(i915, pipe) { in cpt_init_clock_gating()
225 val = intel_uncore_read(&i915->uncore, TRANS_CHICKEN2(pipe)); in cpt_init_clock_gating()
228 if (i915->display.vbt.fdi_rx_polarity_inverted) in cpt_init_clock_gating()
232 intel_uncore_write(&i915->uncore, TRANS_CHICKEN2(pipe), val); in cpt_init_clock_gating()
235 for_each_pipe(i915, pipe) { in cpt_init_clock_gating()
236 intel_uncore_write(&i915->uncore, TRANS_CHICKEN1(pipe), in cpt_init_clock_gating()
241 static void gen6_check_mch_setup(struct drm_i915_private *i915) in gen6_check_mch_setup() argument
245 tmp = intel_uncore_read(&i915->uncore, MCH_SSKPD); in gen6_check_mch_setup()
247 drm_dbg_kms(&i915->drm, in gen6_check_mch_setup()
252 static void gen6_init_clock_gating(struct drm_i915_private *i915) in gen6_init_clock_gating() argument
256 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate); in gen6_init_clock_gating()
258 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT); in gen6_init_clock_gating()
260 intel_uncore_write(&i915->uncore, GEN6_UCGCTL1, in gen6_init_clock_gating()
261 intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) | in gen6_init_clock_gating()
278 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, in gen6_init_clock_gating()
293 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1, in gen6_init_clock_gating()
294 intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) | in gen6_init_clock_gating()
296 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2, in gen6_init_clock_gating()
297 intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) | in gen6_init_clock_gating()
299 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, in gen6_init_clock_gating()
300 intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) | in gen6_init_clock_gating()
304 g4x_disable_trickle_feed(i915); in gen6_init_clock_gating()
306 cpt_init_clock_gating(i915); in gen6_init_clock_gating()
308 gen6_check_mch_setup(i915); in gen6_init_clock_gating()
311 static void lpt_init_clock_gating(struct drm_i915_private *i915) in lpt_init_clock_gating() argument
317 if (HAS_PCH_LPT_LP(i915)) in lpt_init_clock_gating()
318 intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, in lpt_init_clock_gating()
322 intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A), in lpt_init_clock_gating()
326 static void gen8_set_l3sqc_credits(struct drm_i915_private *i915, in gen8_set_l3sqc_credits() argument
334 misccpctl = intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL, in gen8_set_l3sqc_credits()
337 val = intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1); in gen8_set_l3sqc_credits()
341 intel_gt_mcr_multicast_write(to_gt(i915), GEN8_L3SQCREG1, val); in gen8_set_l3sqc_credits()
347 intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1); in gen8_set_l3sqc_credits()
349 intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl); in gen8_set_l3sqc_credits()
352 static void xehpsdv_init_clock_gating(struct drm_i915_private *i915) in xehpsdv_init_clock_gating() argument
355 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) in xehpsdv_init_clock_gating()
356 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS); in xehpsdv_init_clock_gating()
359 static void dg2_init_clock_gating(struct drm_i915_private *i915) in dg2_init_clock_gating() argument
362 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, in dg2_init_clock_gating()
366 static void pvc_init_clock_gating(struct drm_i915_private *i915) in pvc_init_clock_gating() argument
369 if (IS_PVC_BD_STEP(i915, STEP_A0, STEP_B0)) in pvc_init_clock_gating()
370 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS); in pvc_init_clock_gating()
373 if (IS_PVC_BD_STEP(i915, STEP_A0, STEP_B0)) in pvc_init_clock_gating()
374 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); in pvc_init_clock_gating()
377 static void cnp_init_clock_gating(struct drm_i915_private *i915) in cnp_init_clock_gating() argument
379 if (!HAS_PCH_CNP(i915)) in cnp_init_clock_gating()
383 intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 0, CNP_PWM_CGE_GATING_DISABLE); in cnp_init_clock_gating()
386 static void cfl_init_clock_gating(struct drm_i915_private *i915) in cfl_init_clock_gating() argument
388 cnp_init_clock_gating(i915); in cfl_init_clock_gating()
389 gen9_init_clock_gating(i915); in cfl_init_clock_gating()
392 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); in cfl_init_clock_gating()
398 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); in cfl_init_clock_gating()
404 intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), in cfl_init_clock_gating()
408 static void kbl_init_clock_gating(struct drm_i915_private *i915) in kbl_init_clock_gating() argument
410 gen9_init_clock_gating(i915); in kbl_init_clock_gating()
413 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); in kbl_init_clock_gating()
416 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0)) in kbl_init_clock_gating()
417 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, in kbl_init_clock_gating()
421 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0)) in kbl_init_clock_gating()
422 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, in kbl_init_clock_gating()
429 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); in kbl_init_clock_gating()
435 intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), in kbl_init_clock_gating()
439 static void skl_init_clock_gating(struct drm_i915_private *i915) in skl_init_clock_gating() argument
441 gen9_init_clock_gating(i915); in skl_init_clock_gating()
444 intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL, in skl_init_clock_gating()
448 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); in skl_init_clock_gating()
454 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); in skl_init_clock_gating()
460 intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), in skl_init_clock_gating()
467 intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0, DPFC_DISABLE_DUMMY0); in skl_init_clock_gating()
470 static void bdw_init_clock_gating(struct drm_i915_private *i915) in bdw_init_clock_gating() argument
475 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); in bdw_init_clock_gating()
478 intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL); in bdw_init_clock_gating()
481 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); in bdw_init_clock_gating()
483 for_each_pipe(i915, pipe) { in bdw_init_clock_gating()
485 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), in bdw_init_clock_gating()
491 intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE, in bdw_init_clock_gating()
494 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), in bdw_init_clock_gating()
498 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); in bdw_init_clock_gating()
501 gen8_set_l3sqc_credits(i915, 30, 2); in bdw_init_clock_gating()
504 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1, in bdw_init_clock_gating()
507 lpt_init_clock_gating(i915); in bdw_init_clock_gating()
514 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); in bdw_init_clock_gating()
517 static void hsw_init_clock_gating(struct drm_i915_private *i915) in hsw_init_clock_gating() argument
522 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); in hsw_init_clock_gating()
525 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); in hsw_init_clock_gating()
527 for_each_pipe(i915, pipe) { in hsw_init_clock_gating()
529 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), in hsw_init_clock_gating()
534 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in hsw_init_clock_gating()
538 intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL); in hsw_init_clock_gating()
540 lpt_init_clock_gating(i915); in hsw_init_clock_gating()
543 static void ivb_init_clock_gating(struct drm_i915_private *i915) in ivb_init_clock_gating() argument
545 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); in ivb_init_clock_gating()
548 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); in ivb_init_clock_gating()
551 intel_uncore_write(&i915->uncore, IVB_CHICKEN3, in ivb_init_clock_gating()
555 if (IS_IVB_GT1(i915)) in ivb_init_clock_gating()
556 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, in ivb_init_clock_gating()
560 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, in ivb_init_clock_gating()
562 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2_GT2, in ivb_init_clock_gating()
570 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, in ivb_init_clock_gating()
574 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in ivb_init_clock_gating()
577 g4x_disable_trickle_feed(i915); in ivb_init_clock_gating()
579 intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK, in ivb_init_clock_gating()
582 if (!HAS_PCH_NOP(i915)) in ivb_init_clock_gating()
583 cpt_init_clock_gating(i915); in ivb_init_clock_gating()
585 gen6_check_mch_setup(i915); in ivb_init_clock_gating()
588 static void vlv_init_clock_gating(struct drm_i915_private *i915) in vlv_init_clock_gating() argument
591 intel_uncore_write(&i915->uncore, IVB_CHICKEN3, in vlv_init_clock_gating()
596 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, in vlv_init_clock_gating()
600 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in vlv_init_clock_gating()
607 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, in vlv_init_clock_gating()
613 intel_uncore_rmw(&i915->uncore, GEN7_UCGCTL4, 0, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); in vlv_init_clock_gating()
620 intel_uncore_write(&i915->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS); in vlv_init_clock_gating()
623 static void chv_init_clock_gating(struct drm_i915_private *i915) in chv_init_clock_gating() argument
627 intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE, in chv_init_clock_gating()
631 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), in chv_init_clock_gating()
635 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE); in chv_init_clock_gating()
638 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); in chv_init_clock_gating()
645 gen8_set_l3sqc_credits(i915, 38, 2); in chv_init_clock_gating()
648 static void g4x_init_clock_gating(struct drm_i915_private *i915) in g4x_init_clock_gating() argument
652 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0); in g4x_init_clock_gating()
653 intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | in g4x_init_clock_gating()
656 intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0); in g4x_init_clock_gating()
660 if (IS_GM45(i915)) in g4x_init_clock_gating()
662 intel_uncore_write(&i915->uncore, DSPCLK_GATE_D(i915), dspclk_gate); in g4x_init_clock_gating()
664 g4x_disable_trickle_feed(i915); in g4x_init_clock_gating()
667 static void i965gm_init_clock_gating(struct drm_i915_private *i915) in i965gm_init_clock_gating() argument
669 struct intel_uncore *uncore = &i915->uncore; in i965gm_init_clock_gating()
673 intel_uncore_write(uncore, DSPCLK_GATE_D(i915), 0); in i965gm_init_clock_gating()
681 static void i965g_init_clock_gating(struct drm_i915_private *i915) in i965g_init_clock_gating() argument
683 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | in i965g_init_clock_gating()
688 intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, 0); in i965g_init_clock_gating()
689 intel_uncore_write(&i915->uncore, MI_ARB_STATE, in i965g_init_clock_gating()
693 static void gen3_init_clock_gating(struct drm_i915_private *i915) in gen3_init_clock_gating() argument
695 u32 dstate = intel_uncore_read(&i915->uncore, D_STATE); in gen3_init_clock_gating()
699 intel_uncore_write(&i915->uncore, D_STATE, dstate); in gen3_init_clock_gating()
701 if (IS_PINEVIEW(i915)) in gen3_init_clock_gating()
702 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), in gen3_init_clock_gating()
706 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), in gen3_init_clock_gating()
710 intel_uncore_write(&i915->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); in gen3_init_clock_gating()
713 intel_uncore_write(&i915->uncore, MI_ARB_STATE, in gen3_init_clock_gating()
716 intel_uncore_write(&i915->uncore, MI_ARB_STATE, in gen3_init_clock_gating()
720 static void i85x_init_clock_gating(struct drm_i915_private *i915) in i85x_init_clock_gating() argument
722 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); in i85x_init_clock_gating()
725 intel_uncore_write(&i915->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | in i85x_init_clock_gating()
728 intel_uncore_write(&i915->uncore, MEM_MODE, in i85x_init_clock_gating()
738 intel_uncore_write(&i915->uncore, SCPD0, in i85x_init_clock_gating()
742 static void i830_init_clock_gating(struct drm_i915_private *i915) in i830_init_clock_gating() argument
744 intel_uncore_write(&i915->uncore, MEM_MODE, in i830_init_clock_gating()
749 void intel_clock_gating_init(struct drm_i915_private *i915) in intel_clock_gating_init() argument
751 i915->clock_gating_funcs->init_clock_gating(i915); in intel_clock_gating_init()
754 static void nop_init_clock_gating(struct drm_i915_private *i915) in nop_init_clock_gating() argument
756 drm_dbg_kms(&i915->drm, in nop_init_clock_gating()
791 * @i915: device private
798 void intel_clock_gating_hooks_init(struct drm_i915_private *i915) in intel_clock_gating_hooks_init() argument
800 if (IS_PONTEVECCHIO(i915)) in intel_clock_gating_hooks_init()
801 i915->clock_gating_funcs = &pvc_clock_gating_funcs; in intel_clock_gating_hooks_init()
802 else if (IS_DG2(i915)) in intel_clock_gating_hooks_init()
803 i915->clock_gating_funcs = &dg2_clock_gating_funcs; in intel_clock_gating_hooks_init()
804 else if (IS_XEHPSDV(i915)) in intel_clock_gating_hooks_init()
805 i915->clock_gating_funcs = &xehpsdv_clock_gating_funcs; in intel_clock_gating_hooks_init()
806 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) in intel_clock_gating_hooks_init()
807 i915->clock_gating_funcs = &cfl_clock_gating_funcs; in intel_clock_gating_hooks_init()
808 else if (IS_SKYLAKE(i915)) in intel_clock_gating_hooks_init()
809 i915->clock_gating_funcs = &skl_clock_gating_funcs; in intel_clock_gating_hooks_init()
810 else if (IS_KABYLAKE(i915)) in intel_clock_gating_hooks_init()
811 i915->clock_gating_funcs = &kbl_clock_gating_funcs; in intel_clock_gating_hooks_init()
812 else if (IS_BROXTON(i915)) in intel_clock_gating_hooks_init()
813 i915->clock_gating_funcs = &bxt_clock_gating_funcs; in intel_clock_gating_hooks_init()
814 else if (IS_GEMINILAKE(i915)) in intel_clock_gating_hooks_init()
815 i915->clock_gating_funcs = &glk_clock_gating_funcs; in intel_clock_gating_hooks_init()
816 else if (IS_BROADWELL(i915)) in intel_clock_gating_hooks_init()
817 i915->clock_gating_funcs = &bdw_clock_gating_funcs; in intel_clock_gating_hooks_init()
818 else if (IS_CHERRYVIEW(i915)) in intel_clock_gating_hooks_init()
819 i915->clock_gating_funcs = &chv_clock_gating_funcs; in intel_clock_gating_hooks_init()
820 else if (IS_HASWELL(i915)) in intel_clock_gating_hooks_init()
821 i915->clock_gating_funcs = &hsw_clock_gating_funcs; in intel_clock_gating_hooks_init()
822 else if (IS_IVYBRIDGE(i915)) in intel_clock_gating_hooks_init()
823 i915->clock_gating_funcs = &ivb_clock_gating_funcs; in intel_clock_gating_hooks_init()
824 else if (IS_VALLEYVIEW(i915)) in intel_clock_gating_hooks_init()
825 i915->clock_gating_funcs = &vlv_clock_gating_funcs; in intel_clock_gating_hooks_init()
826 else if (GRAPHICS_VER(i915) == 6) in intel_clock_gating_hooks_init()
827 i915->clock_gating_funcs = &gen6_clock_gating_funcs; in intel_clock_gating_hooks_init()
828 else if (GRAPHICS_VER(i915) == 5) in intel_clock_gating_hooks_init()
829 i915->clock_gating_funcs = &ilk_clock_gating_funcs; in intel_clock_gating_hooks_init()
830 else if (IS_G4X(i915)) in intel_clock_gating_hooks_init()
831 i915->clock_gating_funcs = &g4x_clock_gating_funcs; in intel_clock_gating_hooks_init()
832 else if (IS_I965GM(i915)) in intel_clock_gating_hooks_init()
833 i915->clock_gating_funcs = &i965gm_clock_gating_funcs; in intel_clock_gating_hooks_init()
834 else if (IS_I965G(i915)) in intel_clock_gating_hooks_init()
835 i915->clock_gating_funcs = &i965g_clock_gating_funcs; in intel_clock_gating_hooks_init()
836 else if (GRAPHICS_VER(i915) == 3) in intel_clock_gating_hooks_init()
837 i915->clock_gating_funcs = &gen3_clock_gating_funcs; in intel_clock_gating_hooks_init()
838 else if (IS_I85X(i915) || IS_I865G(i915)) in intel_clock_gating_hooks_init()
839 i915->clock_gating_funcs = &i85x_clock_gating_funcs; in intel_clock_gating_hooks_init()
840 else if (GRAPHICS_VER(i915) == 2) in intel_clock_gating_hooks_init()
841 i915->clock_gating_funcs = &i830_clock_gating_funcs; in intel_clock_gating_hooks_init()
843 i915->clock_gating_funcs = &nop_clock_gating_funcs; in intel_clock_gating_hooks_init()