Lines Matching full:glk
1357 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
2658 #define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
2659 #define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
3590 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
3616 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
3631 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
3641 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
3719 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
3720 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
3721 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
4051 #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
4081 #define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */
4083 #define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */
4085 #define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */
4087 #define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */
4604 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
5460 /* SKL/BXT/GLK power wells */