Lines Matching +full:smi +full:- +full:based
86 * implemented via a per-engine length decoding vfunc.
91 * in the per-engine command tables.
149 * A non-zero step value implies that the command may access multiple
164 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
167 * If the check specifies a non-zero condition_mask then the parser
169 * are non-zero.
192 #define STD_MI_OPCODE_SHIFT (32 - 9)
193 #define STD_3D_OPCODE_SHIFT (32 - 16)
194 #define STD_2D_OPCODE_SHIFT (32 - 10)
195 #define STD_MFX_OPCODE_SHIFT (32 - 16)
207 #define SMI STD_MI_OPCODE_SHIFT macro
218 ---------------------------------------------------------- */
220 CMD( MI_NOOP, SMI, F, 1, S ),
221 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ),
222 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, R ),
223 CMD( MI_ARB_CHECK, SMI, F, 1, S ),
224 CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
225 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
226 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
227 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
228 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
230 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B,
237 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B,
249 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
253 CMD( MI_FLUSH, SMI, F, 1, S ),
254 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
255 CMD( MI_PREDICATE, SMI, F, 1, S ),
256 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ),
257 CMD( MI_SET_APPID, SMI, F, 1, S ),
258 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
259 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),
260 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
261 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B,
267 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),
268 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B,
274 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B,
280 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
314 CMD( MI_SET_PREDICATE, SMI, F, 1, S ),
315 CMD( MI_RS_CONTROL, SMI, F, 1, S ),
316 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),
317 CMD( MI_SET_APPID, SMI, F, 1, S ),
318 CMD( MI_RS_CONTEXT, SMI, F, 1, S ),
319 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),
320 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
321 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,
323 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),
324 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ),
325 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ),
337 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
338 CMD( MI_SET_APPID, SMI, F, 1, S ),
339 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
345 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
346 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
366 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
374 * It has a length field but it uses a non-standard length bias.
381 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
382 CMD( MI_SET_APPID, SMI, F, 1, S ),
383 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
389 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
390 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
410 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
419 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
420 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B,
426 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
427 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
452 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),
453 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
458 * need to re-enforce the register access checks. We therefore only need to
463 * 2) Those that do not have the default 8-bit length
467 * cmds on Gen9 use a standard 8-bit Length field.
469 * none allow access to non-general registers, so in fact no BLT cmds are
474 CMD( MI_NOOP, SMI, F, 1, S ),
475 CMD( MI_USER_INTERRUPT, SMI, F, 1, S ),
476 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ),
477 CMD( MI_FLUSH, SMI, F, 1, S ),
478 CMD( MI_ARB_CHECK, SMI, F, 1, S ),
479 CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
480 CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
481 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
482 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, S ),
483 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, S ),
484 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ),
485 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
487 CMD( MI_UPDATE_GTT, SMI, !F, 0x3FF, S ),
488 CMD( MI_STORE_REGISTER_MEM_GEN8, SMI, F, 4, W,
490 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, S ),
491 CMD( MI_LOAD_REGISTER_MEM_GEN8, SMI, F, 4, W,
493 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,
500 #define MI_BB_START_OPERAND_MASK GENMASK(SMI-1, 0)
502 CMD( MI_BATCH_BUFFER_START_GEN8, SMI, !F, 0xFF, B,
511 CMD(MI_NOOP, SMI, F, 1, S);
514 #undef SMI
567 * mask is non-zero the argument of immediate register writes will be
568 * AND-ed with mask, and the command will be rejected if the result
571 * Registers with non-zero mask are only allowed to be written using
580 /* Convenience macro for adding 32-bit registers. */
588 * Convenience macro for adding 64-bit registers.
591 * access commands only allow 32-bit accesses. Hence, we have to include
592 * entries for both halves of the 64-bit registers.
817 for (j = 0; j < table->count; j++) { in validate_cmds_sorted()
819 &table->table[j]; in validate_cmds_sorted()
820 u32 curr = desc->cmd.value & desc->cmd.mask; in validate_cmds_sorted()
823 drm_err(&engine->i915->drm, in validate_cmds_sorted()
826 engine->name, engine->id, in validate_cmds_sorted()
850 drm_err(&engine->i915->drm, in check_sorted()
853 engine->name, engine->id, in check_sorted()
869 for (i = 0; i < engine->reg_table_count; i++) { in validate_regs_sorted()
870 table = &engine->reg_tables[i]; in validate_regs_sorted()
871 if (!check_sorted(engine, table->regs, table->num_regs)) in validate_regs_sorted()
889 * non-opcode bits being set. But if we don't include those bits, some 3D
912 hash_init(engine->cmd_hash); in init_hash_table()
917 for (j = 0; j < table->count; j++) { in init_hash_table()
919 &table->table[j]; in init_hash_table()
924 return -ENOMEM; in init_hash_table()
926 desc_node->desc = desc; in init_hash_table()
927 hash_add(engine->cmd_hash, &desc_node->node, in init_hash_table()
928 cmd_header_key(desc->cmd.value)); in init_hash_table()
941 hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) { in fini_hash_table()
942 hash_del(&desc_node->node); in fini_hash_table()
948 * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine
952 * struct intel_engine_cs based on whether the platform requires software
961 if (GRAPHICS_VER(engine->i915) != 7 && !(GRAPHICS_VER(engine->i915) == 9 && in intel_engine_init_cmd_parser()
962 engine->class == COPY_ENGINE_CLASS)) in intel_engine_init_cmd_parser()
965 switch (engine->class) { in intel_engine_init_cmd_parser()
967 if (IS_HASWELL(engine->i915)) { in intel_engine_init_cmd_parser()
976 if (IS_HASWELL(engine->i915)) { in intel_engine_init_cmd_parser()
977 engine->reg_tables = hsw_render_reg_tables; in intel_engine_init_cmd_parser()
978 engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables); in intel_engine_init_cmd_parser()
980 engine->reg_tables = ivb_render_reg_tables; in intel_engine_init_cmd_parser()
981 engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables); in intel_engine_init_cmd_parser()
983 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask; in intel_engine_init_cmd_parser()
988 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; in intel_engine_init_cmd_parser()
991 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; in intel_engine_init_cmd_parser()
992 if (GRAPHICS_VER(engine->i915) == 9) { in intel_engine_init_cmd_parser()
995 engine->get_cmd_length_mask = in intel_engine_init_cmd_parser()
999 engine->flags |= I915_ENGINE_REQUIRES_CMD_PARSER; in intel_engine_init_cmd_parser()
1000 } else if (IS_HASWELL(engine->i915)) { in intel_engine_init_cmd_parser()
1008 if (GRAPHICS_VER(engine->i915) == 9) { in intel_engine_init_cmd_parser()
1009 engine->reg_tables = gen9_blt_reg_tables; in intel_engine_init_cmd_parser()
1010 engine->reg_table_count = in intel_engine_init_cmd_parser()
1012 } else if (IS_HASWELL(engine->i915)) { in intel_engine_init_cmd_parser()
1013 engine->reg_tables = hsw_blt_reg_tables; in intel_engine_init_cmd_parser()
1014 engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables); in intel_engine_init_cmd_parser()
1016 engine->reg_tables = ivb_blt_reg_tables; in intel_engine_init_cmd_parser()
1017 engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables); in intel_engine_init_cmd_parser()
1024 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; in intel_engine_init_cmd_parser()
1027 MISSING_CASE(engine->class); in intel_engine_init_cmd_parser()
1032 drm_err(&engine->i915->drm, in intel_engine_init_cmd_parser()
1034 engine->name); in intel_engine_init_cmd_parser()
1038 drm_err(&engine->i915->drm, in intel_engine_init_cmd_parser()
1039 "%s: registers are not sorted\n", engine->name); in intel_engine_init_cmd_parser()
1045 drm_err(&engine->i915->drm, in intel_engine_init_cmd_parser()
1046 "%s: initialised failed!\n", engine->name); in intel_engine_init_cmd_parser()
1051 engine->flags |= I915_ENGINE_USING_CMD_PARSER; in intel_engine_init_cmd_parser()
1056 return -EINVAL; in intel_engine_init_cmd_parser()
1062 * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields
1082 hash_for_each_possible(engine->cmd_hash, desc_node, node, in find_cmd_in_table()
1084 const struct drm_i915_cmd_descriptor *desc = desc_node->desc; in find_cmd_in_table()
1085 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) in find_cmd_in_table()
1097 * command parser tables, this function fills in default_desc based on the
1108 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) in find_cmd()
1115 mask = engine->get_cmd_length_mask(cmd_header); in find_cmd()
1119 default_desc->cmd.value = cmd_header; in find_cmd()
1120 default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT; in find_cmd()
1121 default_desc->length.mask = mask; in find_cmd()
1122 default_desc->flags = CMD_DESC_SKIP; in find_cmd()
1131 int mid = start + (end - start) / 2; in __find_reg()
1132 int ret = addr - i915_mmio_reg_offset(table[mid].addr); in __find_reg()
1146 const struct drm_i915_reg_table *table = engine->reg_tables; in find_reg()
1148 int count = engine->reg_table_count; in find_reg()
1150 for (; !reg && (count > 0); ++table, --count) in find_reg()
1151 reg = __find_reg(table->regs, table->num_regs, addr); in find_reg()
1182 src = ERR_PTR(-ENODEV); in copy_batch()
1198 * if we only every write full cache-lines. Since we know that in copy_batch()
1212 int len = min(remain, PAGE_SIZE - x); in copy_batch()
1221 remain -= len; in copy_batch()
1228 memset32(dst + length, 0, (dst_obj->base.size - length) / sizeof(u32)); in copy_batch()
1239 return desc->cmd.value == (cmd & desc->cmd.mask); in cmd_desc_is()
1246 if (desc->flags & CMD_DESC_SKIP) in check_cmd()
1249 if (desc->flags & CMD_DESC_REJECT) { in check_cmd()
1254 if (desc->flags & CMD_DESC_REGISTER) { in check_cmd()
1260 const u32 step = desc->reg.step ? desc->reg.step : length; in check_cmd()
1263 for (offset = desc->reg.offset; offset < length; in check_cmd()
1265 const u32 reg_addr = cmd[offset] & desc->reg.mask; in check_cmd()
1271 reg_addr, *cmd, engine->name); in check_cmd()
1279 if (reg->mask) { in check_cmd()
1294 (cmd[offset + 1] & reg->mask) != reg->value)) { in check_cmd()
1303 if (desc->flags & CMD_DESC_BITMASK) { in check_cmd()
1309 if (desc->bits[i].mask == 0) in check_cmd()
1312 if (desc->bits[i].condition_mask != 0) { in check_cmd()
1314 desc->bits[i].condition_offset; in check_cmd()
1316 desc->bits[i].condition_mask; in check_cmd()
1322 if (desc->bits[i].offset >= length) { in check_cmd()
1324 *cmd, engine->name); in check_cmd()
1328 dword = cmd[desc->bits[i].offset] & in check_cmd()
1329 desc->bits[i].mask; in check_cmd()
1331 if (dword != desc->bits[i].expected) { in check_cmd()
1334 desc->bits[i].mask, in check_cmd()
1335 desc->bits[i].expected, in check_cmd()
1336 dword, engine->name); in check_cmd()
1356 DRM_DEBUG("CMD: Rejecting BB_START for ggtt based submission\n"); in check_bbstart()
1357 return -EACCES; in check_bbstart()
1363 return -EINVAL; in check_bbstart()
1367 jump_offset = jump_target - batch_addr; in check_bbstart()
1376 return -EINVAL; in check_bbstart()
1397 return -EINVAL; in check_bbstart()
1417 return ERR_PTR(-ENOMEM); in alloc_whitelist()
1425 * intel_engine_cmd_parser() - parse a batch buffer for privilege violations
1436 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
1458 batch->size)); in intel_engine_cmd_parser()
1461 cmd = copy_batch(shadow->obj, batch->obj, in intel_engine_cmd_parser()
1492 ret = -EINVAL; in intel_engine_cmd_parser()
1496 if (desc->flags & CMD_DESC_FIXED) in intel_engine_cmd_parser()
1497 length = desc->length.fixed; in intel_engine_cmd_parser()
1499 length = (*cmd & desc->length.mask) + LENGTH_BIAS; in intel_engine_cmd_parser()
1501 if ((batch_end - cmd) < length) { in intel_engine_cmd_parser()
1505 batch_end - cmd); in intel_engine_cmd_parser()
1506 ret = -EINVAL; in intel_engine_cmd_parser()
1511 ret = -EACCES; in intel_engine_cmd_parser()
1529 ret = -EINVAL; in intel_engine_cmd_parser()
1538 * 1 - starting at offset 0, in privileged mode in intel_engine_cmd_parser()
1539 * 2 - starting at offset batch_len, as non-privileged in intel_engine_cmd_parser()
1544 * entry to chain to the original unsafe non-privileged batch, in intel_engine_cmd_parser()
1551 cmd = page_mask_bits(shadow->obj->mm.mapping); in intel_engine_cmd_parser()
1555 if (ret == -EACCES) { in intel_engine_cmd_parser()
1559 if (IS_HASWELL(engine->i915)) in intel_engine_cmd_parser()
1562 GEM_BUG_ON(!IS_GRAPHICS_VER(engine->i915, 6, 7)); in intel_engine_cmd_parser()
1572 i915_gem_object_flush_map(shadow->obj); in intel_engine_cmd_parser()
1576 i915_gem_object_unpin_map(shadow->obj); in intel_engine_cmd_parser()
1581 * i915_cmd_parser_get_version() - get the cmd parser version number
1594 /* If the command parser is not enabled, report 0 - unsupported */ in i915_cmd_parser_get_version()
1620 * for oacontrol state is moving to i915-perf. in i915_cmd_parser_get_version()