Lines Matching +full:pch +full:- +full:msi +full:- +full:1
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
62 #define iir_to_regbase(iir) (iir - 0x8)
63 #define ier_to_regbase(ier) (ier - 0xC)
65 #define get_event_virt_handler(irq, e) (irq->events[e].v_handler)
66 #define get_irq_info(irq, e) (irq->events[e].info)
170 struct intel_gvt_irq *irq = &gvt->irq; in regbase_to_irq_info()
173 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) { in regbase_to_irq_info()
174 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) in regbase_to_irq_info()
175 return irq->info[i]; in regbase_to_irq_info()
182 * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler
198 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_imr_handler()
199 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_reg_imr_handler()
202 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_imr_handler()
207 ops->check_pending_irq(vgpu); in intel_vgpu_reg_imr_handler()
213 * intel_vgpu_reg_master_irq_handler - master IRQ write emulation handler
228 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_master_irq_handler()
229 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_reg_master_irq_handler()
233 trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier, in intel_vgpu_reg_master_irq_handler()
246 ops->check_pending_irq(vgpu); in intel_vgpu_reg_master_irq_handler()
252 * intel_vgpu_reg_ier_handler - Generic IER write emulation handler
267 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_ier_handler()
268 struct drm_i915_private *i915 = gvt->gt->i915; in intel_vgpu_reg_ier_handler()
269 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_reg_ier_handler()
273 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_ier_handler()
279 if (drm_WARN_ON(&i915->drm, !info)) in intel_vgpu_reg_ier_handler()
280 return -EINVAL; in intel_vgpu_reg_ier_handler()
282 if (info->has_upstream_irq) in intel_vgpu_reg_ier_handler()
285 ops->check_pending_irq(vgpu); in intel_vgpu_reg_ier_handler()
291 * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler
306 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_reg_iir_handler()
307 struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt, in intel_vgpu_reg_iir_handler()
311 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_iir_handler()
314 if (drm_WARN_ON(&i915->drm, !info)) in intel_vgpu_reg_iir_handler()
315 return -EINVAL; in intel_vgpu_reg_iir_handler()
319 if (info->has_upstream_irq) in intel_vgpu_reg_iir_handler()
326 { INTEL_GVT_IRQ_INFO_MASTER, 1, INTEL_GVT_IRQ_INFO_GT0, 0xffff0000 },
338 { -1, -1, ~0 },
344 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in update_upstream_irq()
345 struct intel_gvt_irq *irq = &vgpu->gvt->irq; in update_upstream_irq()
346 struct intel_gvt_irq_map *map = irq->irq_map; in update_upstream_irq()
352 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) in update_upstream_irq()
354 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); in update_upstream_irq()
356 if (!info->has_upstream_irq) in update_upstream_irq()
359 for (map = irq->irq_map; map->up_irq_bit != -1; map++) { in update_upstream_irq()
360 if (info->group != map->down_irq_group) in update_upstream_irq()
364 up_irq_info = irq->info[map->up_irq_group]; in update_upstream_irq()
366 drm_WARN_ON(&i915->drm, up_irq_info != in update_upstream_irq()
367 irq->info[map->up_irq_group]); in update_upstream_irq()
369 bit = map->up_irq_bit; in update_upstream_irq()
371 if (val & map->down_irq_bitmask) in update_upstream_irq()
372 set_bits |= (1 << bit); in update_upstream_irq()
374 clear_bits |= (1 << bit); in update_upstream_irq()
377 if (drm_WARN_ON(&i915->drm, !up_irq_info)) in update_upstream_irq()
380 if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) { in update_upstream_irq()
381 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); in update_upstream_irq()
387 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
389 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
394 if (up_irq_info->has_upstream_irq) in update_upstream_irq()
404 for (map = irq->irq_map; map->up_irq_bit != -1; map++) { in init_irq_map()
405 up_info = irq->info[map->up_irq_group]; in init_irq_map()
406 up_bit = map->up_irq_bit; in init_irq_map()
407 down_info = irq->info[map->down_irq_group]; in init_irq_map()
409 set_bit(up_bit, up_info->downstream_irq_bitmap); in init_irq_map()
410 down_info->has_upstream_irq = true; in init_irq_map()
412 gvt_dbg_irq("[up] grp %d bit %d -> [down] grp %d bitmask %x\n", in init_irq_map()
413 up_info->group, up_bit, in init_irq_map()
414 down_info->group, map->down_irq_bitmask); in init_irq_map()
427 unsigned long offset = vgpu->gvt->device_info.msi_cap_offset; in inject_virtual_interrupt()
435 /* Do not generate MSI if MSIEN is disabled */ in inject_virtual_interrupt()
439 if (WARN(control & GENMASK(15, 1), "only support one MSI format\n")) in inject_virtual_interrupt()
442 trace_inject_msi(vgpu->id, addr, data); in inject_virtual_interrupt()
449 * vblank interrupt request. But msi_trigger is null until msi is in inject_virtual_interrupt()
453 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status)) in inject_virtual_interrupt()
455 if (vgpu->msi_trigger) in inject_virtual_interrupt()
456 eventfd_signal(vgpu->msi_trigger); in inject_virtual_interrupt()
470 reg_base = i915_mmio_reg_offset(info->reg_base); in propagate_event()
471 bit = irq->events[event].bit; in propagate_event()
475 trace_propagate_event(vgpu->id, irq_name[event], bit); in propagate_event()
485 if (!vgpu->irq.irq_warn_once[event]) { in handle_default_event_virt()
487 vgpu->id, event, irq_name[event]); in handle_default_event_virt()
488 vgpu->irq.irq_warn_once[event] = true; in handle_default_event_virt()
498 .name = #regname"-IRQ", \
500 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = \
505 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt1, GEN8_GT_ISR(1));
517 .name = "PCH-IRQ",
519 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] =
525 struct intel_gvt_irq *irq = &vgpu->gvt->irq; in gen8_check_pending_irq()
532 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) { in gen8_check_pending_irq()
533 struct intel_gvt_irq_info *info = irq->info[i]; in gen8_check_pending_irq()
536 if (!info->has_upstream_irq) in gen8_check_pending_irq()
539 reg_base = i915_mmio_reg_offset(info->reg_base); in gen8_check_pending_irq()
557 s->events[e].bit = b; \ in gen8_init_irq()
558 s->events[e].info = s->info[i]; \ in gen8_init_irq()
559 s->info[i]->bit_to_event[b] = e;\ in gen8_init_irq()
564 s->info[g] = i; \ in gen8_init_irq()
565 (i)->group = g; \ in gen8_init_irq()
566 set_bit(g, s->irq_info_bitmap); \ in gen8_init_irq()
598 if (HAS_ENGINE(gvt->gt, VCS1)) { in gen8_init_irq()
623 /* PCH events */ in gen8_init_irq()
630 if (IS_BROADWELL(gvt->gt->i915)) { in gen8_init_irq()
643 } else if (GRAPHICS_VER(gvt->gt->i915) >= 9) { in gen8_init_irq()
668 * intel_vgpu_trigger_virtual_event - Trigger a virtual event for a vGPU
680 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_trigger_virtual_event()
681 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_trigger_virtual_event()
682 struct intel_gvt_irq *irq = &gvt->irq; in intel_vgpu_trigger_virtual_event()
684 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_trigger_virtual_event()
687 drm_WARN_ON(&i915->drm, !handler); in intel_vgpu_trigger_virtual_event()
691 ops->check_pending_irq(vgpu); in intel_vgpu_trigger_virtual_event()
700 irq->events[i].info = NULL; in init_events()
701 irq->events[i].v_handler = handle_default_event_virt; in init_events()
706 * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem
709 * This function is called at driver loading stage, to initialize the GVT-g IRQ
717 struct intel_gvt_irq *irq = &gvt->irq; in intel_gvt_init_irq()
721 irq->ops = &gen8_irq_ops; in intel_gvt_init_irq()
722 irq->irq_map = gen8_irq_map; in intel_gvt_init_irq()
728 irq->ops->init_irq(irq); in intel_gvt_init_irq()