24  * low-voltage mode when idle, using down to 0V while at this stage.  This
78 		intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);  in gen11_rc6_enable()
80 		intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);  in gen11_rc6_enable()
137 		for (i = 0; i < I915_MAX_VCS; i++)  in gen11_rc6_enable()
171 	intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);  in gen9_rc6_enable()
173 	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);  in gen9_rc6_enable()
228 	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);  in gen8_rc6_enable()
256 	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);  in gen6_rc6_enable()
273 	rc6vids = 0;  in gen6_rc6_enable()
278 		   (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {  in gen6_rc6_enable()
281 			GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);  in gen6_rc6_enable()
282 		rc6vids &= 0xffff00;  in gen6_rc6_enable()
301 	if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {  in chv_rc6_init()
310 	return 0;  in chv_rc6_init()
331 							0);  in vlv_rc6_init()
364 	return 0;  in vlv_rc6_init()
380 	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);  in chv_rc6_enable()
382 	/* TO threshold set to 500 us (0x186 * 1.28 us) */  in chv_rc6_enable()
383 	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x186);  in chv_rc6_enable()
401 	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);  in vlv_rc6_enable()
408 	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x557);  in vlv_rc6_enable()
527 	if (IS_MEDIA_GT_IP_STEP(gt, IP_VER(13, 0), STEP_A0, STEP_B0)) {  in rc6_supported()
576 		intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, 0);  in __intel_rc6_disable()
577 	intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, 0);  in __intel_rc6_disable()
578 	intel_uncore_write_fw(uncore, GEN6_RC_STATE, 0);  in __intel_rc6_disable()
585 		[0 ... INTEL_RC6_RES_MAX - 1] = INVALID_MMIO_REG,  in rc6_res_reg_init()
621 		err = 0;  in intel_rc6_init()
626 	rc6->supported = err == 0;  in intel_rc6_init()
631 	memset(rc6->prev_hw_residency, 0, sizeof(rc6->prev_hw_residency));  in intel_rc6_sanitize()
669 		rc6->ctl_enable = 0;  in intel_rc6_enable()
712 		target = 0x6; /* deepest rc6 */  in intel_rc6_park()
714 		target = 0x5; /* deep rc6 */  in intel_rc6_park()
716 		target = 0x4; /* normal rc6 */  in intel_rc6_park()
806 		return 0;  in intel_rc6_residency_ns()