Lines Matching +full:- +full:70
1 // SPDX-License-Identifier: MIT
18 * independent values of a register per hardware unit (e.g., per-subslice,
19 * per-L3bank, etc.). The specific types of replication that exist vary
20 * per-platform.
38 #define HAS_MSLICE_STEERING(i915) (INTEL_INFO(i915)->has_mslice_steering)
62 { 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
86 * will always provide us with a non-terminated value. We'll stick them
90 { 0x004000, 0x004AFF }, /* HALF-BSLICE */
93 { 0x00B000, 0x00B0FF }, /* HALF-BSLICE */
95 { 0x00C800, 0x00CFFF }, /* HALF-BSLICE */
96 { 0x00D800, 0x00D8FF }, /* HALF-BSLICE */
98 { 0x00E900, 0x00E9FF }, /* HALF-BSLICE */
99 { 0x00EC00, 0x00EEFF }, /* HALF-BSLICE */
100 { 0x00F000, 0x00FFFF }, /* HALF-BSLICE */
101 { 0x024180, 0x0241FF }, /* HALF-BSLICE */
126 { 0x008140, 0x00815F }, /* SLICE (0x8140-0x814F), DSS (0x8150-0x815F) */
127 { 0x0094D0, 0x00955F }, /* SLICE (0x94D0-0x951F), DSS (0x9520-0x955F) */
131 { 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
143 struct drm_i915_private *i915 = gt->i915; in intel_gt_mcr_init()
147 spin_lock_init(>->mcr_lock); in intel_gt_mcr_init()
154 gt->info.mslice_mask = in intel_gt_mcr_init()
155 intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask, in intel_gt_mcr_init()
157 gt->info.mslice_mask |= in intel_gt_mcr_init()
158 (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & in intel_gt_mcr_init()
161 if (!gt->info.mslice_mask) /* should be impossible! */ in intel_gt_mcr_init()
165 if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) { in intel_gt_mcr_init()
166 gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table; in intel_gt_mcr_init()
167 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { in intel_gt_mcr_init()
169 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || in intel_gt_mcr_init()
172 intel_uncore_read(gt->uncore, in intel_gt_mcr_init()
176 intel_uncore_read(gt->uncore, XEHP_FUSE4)); in intel_gt_mcr_init()
183 gt->info.l3bank_mask |= 0x3 << 2 * i; in intel_gt_mcr_init()
185 gt->steering_table[INSTANCE0] = xelpg_instance0_steering_table; in intel_gt_mcr_init()
186 gt->steering_table[L3BANK] = xelpg_l3bank_steering_table; in intel_gt_mcr_init()
187 gt->steering_table[DSS] = xelpg_dss_steering_table; in intel_gt_mcr_init()
189 gt->steering_table[INSTANCE0] = pvc_instance0_steering_table; in intel_gt_mcr_init()
191 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table; in intel_gt_mcr_init()
192 gt->steering_table[LNCF] = dg2_lncf_steering_table; in intel_gt_mcr_init()
199 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table; in intel_gt_mcr_init()
200 gt->steering_table[LNCF] = xehpsdv_lncf_steering_table; in intel_gt_mcr_init()
201 gt->steering_table[GAM] = xehpsdv_gam_steering_table; in intel_gt_mcr_init()
204 gt->steering_table[L3BANK] = icl_l3bank_steering_table; in intel_gt_mcr_init()
205 gt->info.l3bank_mask = in intel_gt_mcr_init()
206 ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & in intel_gt_mcr_init()
208 if (!gt->info.l3bank_mask) /* should be impossible! */ in intel_gt_mcr_init()
215 MISSING_CASE(INTEL_INFO(i915)->platform); in intel_gt_mcr_init()
220 * Although the rest of the driver should use MCR-specific functions to
233 * rw_with_mcr_steering_fw - Access a register with specific MCR steering
250 struct intel_uncore *uncore = gt->uncore; in rw_with_mcr_steering_fw()
253 lockdep_assert_held(>->mcr_lock); in rw_with_mcr_steering_fw()
255 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 70)) { in rw_with_mcr_steering_fw()
267 } else if (GRAPHICS_VER(uncore->i915) >= 11) { in rw_with_mcr_steering_fw()
310 * For pre-MTL platforms, we need to restore the old value of the in rw_with_mcr_steering_fw()
315 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 70) && rw_flag == FW_REG_WRITE) in rw_with_mcr_steering_fw()
317 else if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 70)) in rw_with_mcr_steering_fw()
328 struct intel_uncore *uncore = gt->uncore; in rw_with_mcr_steering()
340 spin_lock(&uncore->lock); in rw_with_mcr_steering()
346 spin_unlock(&uncore->lock); in rw_with_mcr_steering()
353 * intel_gt_mcr_lock - Acquire MCR steering lock
362 * Context: Takes gt->mcr_lock. uncore->lock should *not* be held when this
367 __acquires(>->mcr_lock) in intel_gt_mcr_lock()
372 lockdep_assert_not_held(>->uncore->lock); in intel_gt_mcr_lock()
379 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { in intel_gt_mcr_lock()
383 * are some issues if higher-level platform sleep states are in intel_gt_mcr_lock()
393 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_GT); in intel_gt_mcr_lock()
395 err = wait_for(intel_uncore_read_fw(gt->uncore, in intel_gt_mcr_lock()
405 spin_lock_irqsave(>->mcr_lock, __flags); in intel_gt_mcr_lock()
414 if (err == -ETIMEDOUT) { in intel_gt_mcr_lock()
416 add_taint_for_CI(gt->i915, TAINT_WARN); /* CI is now unreliable */ in intel_gt_mcr_lock()
421 * intel_gt_mcr_unlock - Release MCR steering lock
427 * Context: Releases gt->mcr_lock
430 __releases(>->mcr_lock) in intel_gt_mcr_unlock()
432 spin_unlock_irqrestore(>->mcr_lock, flags); in intel_gt_mcr_unlock()
434 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { in intel_gt_mcr_unlock()
435 intel_uncore_write_fw(gt->uncore, MTL_STEER_SEMAPHORE, 0x1); in intel_gt_mcr_unlock()
437 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_GT); in intel_gt_mcr_unlock()
442 * intel_gt_mcr_lock_sanitize - Sanitize MCR steering lock
457 lockdep_assert_not_held(>->mcr_lock); in intel_gt_mcr_lock_sanitize()
459 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) in intel_gt_mcr_lock_sanitize()
460 intel_uncore_write_fw(gt->uncore, MTL_STEER_SEMAPHORE, 0x1); in intel_gt_mcr_lock_sanitize()
464 * intel_gt_mcr_read - read a specific instance of an MCR register
470 * Context: Takes and releases gt->mcr_lock
483 * intel_gt_mcr_unicast_write - write a specific instance of an MCR register
493 * Context: Calls a function that takes and releases gt->mcr_lock
502 * intel_gt_mcr_multicast_write - write a value to all instances of an MCR register
509 * Context: Takes and releases gt->mcr_lock
519 * Ensure we have multicast behavior, just in case some non-i915 agent in intel_gt_mcr_multicast_write()
522 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) in intel_gt_mcr_multicast_write()
523 intel_uncore_write_fw(gt->uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST); in intel_gt_mcr_multicast_write()
525 intel_uncore_write(gt->uncore, mcr_reg_cast(reg), value); in intel_gt_mcr_multicast_write()
531 * intel_gt_mcr_multicast_write_fw - write a value to all instances of an MCR register
541 * Context: The caller must hold gt->mcr_lock.
545 lockdep_assert_held(>->mcr_lock); in intel_gt_mcr_multicast_write_fw()
548 * Ensure we have multicast behavior, just in case some non-i915 agent in intel_gt_mcr_multicast_write_fw()
551 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) in intel_gt_mcr_multicast_write_fw()
552 intel_uncore_write_fw(gt->uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST); in intel_gt_mcr_multicast_write_fw()
554 intel_uncore_write_fw(gt->uncore, mcr_reg_cast(reg), value); in intel_gt_mcr_multicast_write_fw()
558 * intel_gt_mcr_multicast_rmw - Performs a multicast RMW operations
564 * Performs a read-modify-write on an MCR register in a multicast manner.
566 * expected to have the same value. The read will target any non-terminated
573 * Context: Calls functions that take and release gt->mcr_lock
588 * reg_needs_read_steering - determine whether a register read requires
598 * steering type, or if the default (subslice-based) steering IDs are suitable
608 if (likely(!gt->steering_table[type])) in reg_needs_read_steering()
612 offset += gt->uncore->gsi_offset; in reg_needs_read_steering()
614 for (entry = gt->steering_table[type]; entry->end; entry++) { in reg_needs_read_steering()
615 if (offset >= entry->start && offset <= entry->end) in reg_needs_read_steering()
623 * get_nonterminated_steering - determines valid IDs for a class of MCR steering
630 * MCR class to a non-terminated instance.
641 *instance = __ffs(gt->info.l3bank_mask); in get_nonterminated_steering()
644 GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915)); in get_nonterminated_steering()
645 *group = __ffs(gt->info.mslice_mask); in get_nonterminated_steering()
653 GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915)); in get_nonterminated_steering()
654 *group = __ffs(gt->info.mslice_mask) << 1; in get_nonterminated_steering()
658 *group = IS_DG2(gt->i915) ? 1 : 0; in get_nonterminated_steering()
662 dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0); in get_nonterminated_steering()
669 * will always provide a non-terminated value. in get_nonterminated_steering()
675 if ((VDBOX_MASK(gt) | VEBOX_MASK(gt) | gt->info.sfc_mask) & BIT(0)) in get_nonterminated_steering()
689 * intel_gt_mcr_get_nonterminated_steering - find group/instance values that
690 * will steer a register to a non-terminated instance
714 *group = gt->default_steering.groupid; in intel_gt_mcr_get_nonterminated_steering()
715 *instance = gt->default_steering.instanceid; in intel_gt_mcr_get_nonterminated_steering()
719 * intel_gt_mcr_read_any_fw - reads one instance of an MCR register
723 * Reads a GT MCR register. The read will be steered to a non-terminated
729 * Context: The caller must hold gt->mcr_lock.
731 * Returns the value from a non-terminated instance of @reg.
738 lockdep_assert_held(>->mcr_lock); in intel_gt_mcr_read_any_fw()
749 return intel_uncore_read_fw(gt->uncore, mcr_reg_cast(reg)); in intel_gt_mcr_read_any_fw()
753 * intel_gt_mcr_read_any - reads one instance of an MCR register
757 * Reads a GT MCR register. The read will be steered to a non-terminated
760 * Context: Calls a function that takes and releases gt->mcr_lock.
762 * Returns the value from a non-terminated instance of @reg.
778 return intel_uncore_read(gt->uncore, mcr_reg_cast(reg)); in intel_gt_mcr_read_any()
791 if (!gt->steering_table[type]) { in report_steering_type()
804 for (entry = gt->steering_table[type]; entry->end; entry++) in report_steering_type()
805 drm_printf(p, "\t0x%06x - 0x%06x\n", entry->start, entry->end); in report_steering_type()
815 if (GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)) in intel_gt_mcr_report_steering()
817 gt->default_steering.groupid, in intel_gt_mcr_report_steering()
818 gt->default_steering.instanceid); in intel_gt_mcr_report_steering()
820 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { in intel_gt_mcr_report_steering()
822 if (gt->steering_table[i]) in intel_gt_mcr_report_steering()
824 } else if (IS_PONTEVECCHIO(gt->i915)) { in intel_gt_mcr_report_steering()
826 } else if (HAS_MSLICE_STEERING(gt->i915)) { in intel_gt_mcr_report_steering()
833 * intel_gt_mcr_get_ss_steering - returns the group/instance steering for a SS
845 if (IS_PONTEVECCHIO(gt->i915)) { in intel_gt_mcr_get_ss_steering()
848 } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) { in intel_gt_mcr_get_ss_steering()
859 * intel_gt_mcr_wait_for_reg - wait until MCR register matches expected state
876 * This function is basically an MCR-friendly version of
878 * on GAM registers which are a bit special --- although they're MCR registers,
885 * Context: Calls a function that takes and releases gt->mcr_lock
886 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
897 lockdep_assert_not_held(>->mcr_lock); in intel_gt_mcr_wait_for_reg()
906 ret = -ETIMEDOUT; in intel_gt_mcr_wait_for_reg()