40 	426, 469, 234, 373, 442, 221, 110, 311, 411,		/* 62 - 70 */
41 	461, 486, 243, 377, 188, 350, 175, 343, 427, 213,	/* 71 - 80 */
42 	106, 53, 282, 397, 454, 227, 113, 56, 284, 142,		/* 81 - 90 */
43 	71, 35, 273, 136, 324, 418, 465, 488, 500, 506		/* 91 - 100 */
61 			struct intel_crtc_state *config,  in dsi_calc_mnp()  argument
71 		drm_err(&dev_priv->drm, "DSI CLK Out of Range\n");  in dsi_calc_mnp()
72 		return -ECHRNG;  in dsi_calc_mnp()
89 	delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n));  in dsi_calc_mnp()
95 			 * +/- the required clock  in dsi_calc_mnp()
98 			int d = abs(target_dsi_clk - calc_dsi_clk);  in dsi_calc_mnp()
108 	config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);  in dsi_calc_mnp()
109 	config->dsi_pll.div =  in dsi_calc_mnp()
110 		(ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT |  in dsi_calc_mnp()
111 		(u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;  in dsi_calc_mnp()
117 			struct intel_crtc_state *config)  in vlv_dsi_pclk()  argument
119 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in vlv_dsi_pclk()
121 	int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);  in vlv_dsi_pclk()
128 	pll_ctl = config->dsi_pll.ctrl;  in vlv_dsi_pclk()
129 	pll_div = config->dsi_pll.div;  in vlv_dsi_pclk()
133 	pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);  in vlv_dsi_pclk()
147 	p--;  in vlv_dsi_pclk()
150 		drm_err(&dev_priv->drm, "wrong P1 divisor\n");  in vlv_dsi_pclk()
160 		drm_err(&dev_priv->drm, "wrong m_seed programmed\n");  in vlv_dsi_pclk()
168 	return DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp);  in vlv_dsi_pclk()
176 			struct intel_crtc_state *config)  in vlv_dsi_pll_compute()  argument
178 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in vlv_dsi_pll_compute()
182 	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,  in vlv_dsi_pll_compute()
183 				    intel_dsi->lane_count);  in vlv_dsi_pll_compute()
185 	ret = dsi_calc_mnp(dev_priv, config, dsi_clk);  in vlv_dsi_pll_compute()
187 		drm_dbg_kms(&dev_priv->drm, "dsi_calc_mnp failed\n");  in vlv_dsi_pll_compute()
191 	if (intel_dsi->ports & (1 << PORT_A))  in vlv_dsi_pll_compute()
192 		config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;  in vlv_dsi_pll_compute()
194 	if (intel_dsi->ports & (1 << PORT_C))  in vlv_dsi_pll_compute()
195 		config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;  in vlv_dsi_pll_compute()
197 	config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;  in vlv_dsi_pll_compute()
199 	drm_dbg_kms(&dev_priv->drm, "dsi pll div %08x, ctrl %08x\n",  in vlv_dsi_pll_compute()
200 		    config->dsi_pll.div, config->dsi_pll.ctrl);  in vlv_dsi_pll_compute()
202 	pclk = vlv_dsi_pclk(encoder, config);  in vlv_dsi_pll_compute()
203 	config->port_clock = pclk;  in vlv_dsi_pll_compute()
206 	config->hw.adjusted_mode.crtc_clock = pclk;  in vlv_dsi_pll_compute()
207 	if (intel_dsi->dual_link)  in vlv_dsi_pll_compute()
208 		config->hw.adjusted_mode.crtc_clock *= 2;  in vlv_dsi_pll_compute()
214 			const struct intel_crtc_state *config)  in vlv_dsi_pll_enable()  argument
216 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in vlv_dsi_pll_enable()
218 	drm_dbg_kms(&dev_priv->drm, "\n");  in vlv_dsi_pll_enable()
223 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);  in vlv_dsi_pll_enable()
225 		      config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);  in vlv_dsi_pll_enable()
232 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);  in vlv_dsi_pll_enable()
238 		drm_err(&dev_priv->drm, "DSI PLL lock failed\n");  in vlv_dsi_pll_enable()
243 	drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n");  in vlv_dsi_pll_enable()
248 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in vlv_dsi_pll_disable()
251 	drm_dbg_kms(&dev_priv->drm, "\n");  in vlv_dsi_pll_disable()
278 	 * GEMINLAKE only PORT A divider values are checked while for BXT  in bxt_dsi_pll_is_enabled()
287 			drm_dbg(&dev_priv->drm,  in bxt_dsi_pll_is_enabled()
293 			drm_dbg(&dev_priv->drm,  in bxt_dsi_pll_is_enabled()
304 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in bxt_dsi_pll_disable()
306 	drm_dbg_kms(&dev_priv->drm, "\n");  in bxt_dsi_pll_disable()
316 		drm_err(&dev_priv->drm,  in bxt_dsi_pll_disable()
321 		     struct intel_crtc_state *config)  in vlv_dsi_get_pclk()  argument
323 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in vlv_dsi_get_pclk()
326 	drm_dbg_kms(&dev_priv->drm, "\n");  in vlv_dsi_get_pclk()
333 	config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;  in vlv_dsi_get_pclk()
334 	config->dsi_pll.div = pll_div;  in vlv_dsi_get_pclk()
336 	return vlv_dsi_pclk(encoder, config);  in vlv_dsi_get_pclk()
340 			const struct intel_crtc_state *config)  in bxt_dsi_pclk()  argument
343 	int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);  in bxt_dsi_pclk()
346 	dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;  in bxt_dsi_pclk()
349 	return DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp);  in bxt_dsi_pclk()
353 		     struct intel_crtc_state *config)  in bxt_dsi_get_pclk()  argument
355 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in bxt_dsi_get_pclk()
358 	config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL);  in bxt_dsi_get_pclk()
360 	pclk = bxt_dsi_pclk(encoder, config);  in bxt_dsi_get_pclk()
362 	drm_dbg(&dev_priv->drm, "Calculated pclk=%u\n", pclk);  in bxt_dsi_get_pclk()
366 void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)  in vlv_dsi_reset_clocks()  argument
369 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in vlv_dsi_reset_clocks()
372 	temp = intel_de_read(dev_priv, MIPI_CTRL(port));  in vlv_dsi_reset_clocks()
374 	intel_de_write(dev_priv, MIPI_CTRL(port),  in vlv_dsi_reset_clocks()
375 		       temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT);  in vlv_dsi_reset_clocks()
379 				   const struct intel_crtc_state *config)  in glk_dsi_program_esc_clock()  argument
390 	pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;  in glk_dsi_program_esc_clock()
419 		       (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK);  in glk_dsi_program_esc_clock()
421 		       (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK);  in glk_dsi_program_esc_clock()
425 static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,  in bxt_dsi_program_clocks()  argument
426 				   const struct intel_crtc_state *config)  in bxt_dsi_program_clocks()  argument
440 	tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));  in bxt_dsi_program_clocks()
441 	tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));  in bxt_dsi_program_clocks()
442 	tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));  in bxt_dsi_program_clocks()
443 	tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));  in bxt_dsi_program_clocks()
446 	pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;  in bxt_dsi_program_clocks()
453 	tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;  in bxt_dsi_program_clocks()
458 	rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;  in bxt_dsi_program_clocks()
470 	tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);  in bxt_dsi_program_clocks()
471 	tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);  in bxt_dsi_program_clocks()
472 	tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);  in bxt_dsi_program_clocks()
473 	tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);  in bxt_dsi_program_clocks()
479 			struct intel_crtc_state *config)  in bxt_dsi_pll_compute()  argument
481 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in bxt_dsi_pll_compute()
487 	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,  in bxt_dsi_pll_compute()
488 				    intel_dsi->lane_count);  in bxt_dsi_pll_compute()
506 		drm_err(&dev_priv->drm,  in bxt_dsi_pll_compute()
508 		return -ECHRNG;  in bxt_dsi_pll_compute()
510 		drm_dbg_kms(&dev_priv->drm, "DSI PLL calculation is Done!!\n");  in bxt_dsi_pll_compute()
517 	config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;  in bxt_dsi_pll_compute()
523 		config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;  in bxt_dsi_pll_compute()
525 	pclk = bxt_dsi_pclk(encoder, config);  in bxt_dsi_pll_compute()
526 	config->port_clock = pclk;  in bxt_dsi_pll_compute()
529 	config->hw.adjusted_mode.crtc_clock = pclk;  in bxt_dsi_pll_compute()
530 	if (intel_dsi->dual_link)  in bxt_dsi_pll_compute()
531 		config->hw.adjusted_mode.crtc_clock *= 2;  in bxt_dsi_pll_compute()
537 			const struct intel_crtc_state *config)  in bxt_dsi_pll_enable()  argument
539 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in bxt_dsi_pll_enable()
541 	enum port port;  in bxt_dsi_pll_enable()  local
543 	drm_dbg_kms(&dev_priv->drm, "\n");  in bxt_dsi_pll_enable()
546 	intel_de_write(dev_priv, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);  in bxt_dsi_pll_enable()
551 		for_each_dsi_port(port, intel_dsi->ports)  in bxt_dsi_pll_enable()
552 			bxt_dsi_program_clocks(encoder->base.dev, port, config);  in bxt_dsi_pll_enable()
554 		glk_dsi_program_esc_clock(encoder->base.dev, config);  in bxt_dsi_pll_enable()
563 		drm_err(&dev_priv->drm,  in bxt_dsi_pll_enable()
568 	drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n");  in bxt_dsi_pll_enable()
571 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)  in bxt_dsi_reset_clocks()  argument
574 	struct drm_device *dev = encoder->base.dev;  in bxt_dsi_reset_clocks()
580 		tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));  in bxt_dsi_reset_clocks()
581 		tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));  in bxt_dsi_reset_clocks()
582 		tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));  in bxt_dsi_reset_clocks()
583 		tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));  in bxt_dsi_reset_clocks()
590 	intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);  in bxt_dsi_reset_clocks()