108 	config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);  in dsi_calc_mnp()
109 	config->dsi_pll.div =  in dsi_calc_mnp()
128 	pll_ctl = config->dsi_pll.ctrl;  in vlv_dsi_pclk()
129 	pll_div = config->dsi_pll.div;  in vlv_dsi_pclk()
192 		config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;  in vlv_dsi_pll_compute()
195 		config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;  in vlv_dsi_pll_compute()
197 	config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;  in vlv_dsi_pll_compute()
200 		    config->dsi_pll.div, config->dsi_pll.ctrl);  in vlv_dsi_pll_compute()
223 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);  in vlv_dsi_pll_enable()
225 		      config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);  in vlv_dsi_pll_enable()
232 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);  in vlv_dsi_pll_enable()
333 	config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;  in vlv_dsi_get_pclk()
334 	config->dsi_pll.div = pll_div;  in vlv_dsi_get_pclk()
346 	dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;  in bxt_dsi_pclk()
358 	config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL);  in bxt_dsi_get_pclk()
390 	pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;  in glk_dsi_program_esc_clock()
446 	pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;  in bxt_dsi_program_clocks()
517 	config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;  in bxt_dsi_pll_compute()
523 		config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;  in bxt_dsi_pll_compute()
546 	intel_de_write(dev_priv, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);  in bxt_dsi_pll_enable()