Lines Matching +full:hpd +full:- +full:reliable +full:- +full:delay
47 * Since Haswell Display controller supports Panel Self-Refresh on display
61 * The implementation uses the hardware-based PSR support which automatically
62 * enters/exits self-refresh mode. The hardware takes care of sending the
65 * changes to know when to exit self-refresh mode again. Unfortunately that
70 * issues the self-refresh re-enable code is done from a work queue, which
78 * entry/exit allows the HW to enter a low-power state even when page flipping
94 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl):
158 * In standby mode (as opposed to link-off) this makes no difference
172 * The rest of the bits are more self-explanatory and/or
178 if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST) in intel_encoder_can_psr()
187 struct intel_connector *connector = intel_dp->attached_connector; in psr_global_enabled()
190 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in psr_global_enabled()
192 if (i915->display.params.enable_psr == -1) in psr_global_enabled()
193 return connector->panel.vbt.psr.enable; in psr_global_enabled()
194 return i915->display.params.enable_psr; in psr_global_enabled()
206 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in psr2_global_enabled()
211 if (i915->display.params.enable_psr == 1) in psr2_global_enabled()
222 EDP_PSR_ERROR(intel_dp->psr.transcoder); in psr_irq_psr_error_bit_get()
230 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); in psr_irq_post_exit_bit_get()
238 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); in psr_irq_pre_entry_bit_get()
246 EDP_PSR_MASK(intel_dp->psr.transcoder); in psr_irq_mask_get()
324 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_irq_control()
328 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) in psr_irq_control()
339 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); in psr_event_print()
341 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); in psr_event_print()
343 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); in psr_event_print()
345 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); in psr_event_print()
347 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); in psr_event_print()
349 drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); in psr_event_print()
351 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); in psr_event_print()
353 drm_dbg_kms(&i915->drm, "\tMemory up\n"); in psr_event_print()
355 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); in psr_event_print()
357 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); in psr_event_print()
359 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); in psr_event_print()
361 drm_dbg_kms(&i915->drm, "\tRegister updated\n"); in psr_event_print()
363 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); in psr_event_print()
365 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); in psr_event_print()
367 drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); in psr_event_print()
369 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); in psr_event_print()
371 drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); in psr_event_print()
377 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_irq_handler()
381 intel_dp->psr.last_entry_attempt = time_ns; in intel_psr_irq_handler()
382 drm_dbg_kms(&dev_priv->drm, in intel_psr_irq_handler()
388 intel_dp->psr.last_exit = time_ns; in intel_psr_irq_handler()
389 drm_dbg_kms(&dev_priv->drm, in intel_psr_irq_handler()
398 psr_event_print(dev_priv, val, intel_dp->psr.psr2_enabled); in intel_psr_irq_handler()
403 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", in intel_psr_irq_handler()
406 intel_dp->psr.irq_aux_error = true; in intel_psr_irq_handler()
419 queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); in intel_psr_irq_handler()
427 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, in intel_dp_get_alpm_status()
438 if (drm_dp_dpcd_readb(&intel_dp->aux, in intel_dp_get_sink_sync_latency()
442 drm_dbg_kms(&i915->drm, in intel_dp_get_sink_sync_latency()
455 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { in intel_dp_get_su_granularity()
462 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2); in intel_dp_get_su_granularity()
464 drm_dbg_kms(&i915->drm, in intel_dp_get_su_granularity()
473 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); in intel_dp_get_su_granularity()
475 drm_dbg_kms(&i915->drm, in intel_dp_get_su_granularity()
483 intel_dp->psr.su_w_granularity = w; in intel_dp_get_su_granularity()
484 intel_dp->psr.su_y_granularity = y; in intel_dp_get_su_granularity()
492 intel_dp->psr.sink_panel_replay_support = false; in _panel_replay_init_dpcd()
493 drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd); in _panel_replay_init_dpcd()
496 drm_dbg_kms(&i915->drm, in _panel_replay_init_dpcd()
501 drm_dbg_kms(&i915->drm, in _panel_replay_init_dpcd()
503 intel_dp->psr.sink_panel_replay_support = true; in _panel_replay_init_dpcd()
509 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); in _psr_init_dpcd()
511 drm_dbg_kms(&i915->drm, "eDP panel supports PSR version %x\n", in _psr_init_dpcd()
512 intel_dp->psr_dpcd[0]); in _psr_init_dpcd()
514 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { in _psr_init_dpcd()
515 drm_dbg_kms(&i915->drm, in _psr_init_dpcd()
520 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { in _psr_init_dpcd()
521 drm_dbg_kms(&i915->drm, in _psr_init_dpcd()
526 intel_dp->psr.sink_support = true; in _psr_init_dpcd()
527 intel_dp->psr.sink_sync_latency = in _psr_init_dpcd()
531 intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) { in _psr_init_dpcd()
532 bool y_req = intel_dp->psr_dpcd[1] & in _psr_init_dpcd()
538 * Y-coordinate) can handle Y-coordinates in VSC but we are in _psr_init_dpcd()
544 * Y-coordinate requirement panels we would need to enable in _psr_init_dpcd()
547 intel_dp->psr.sink_psr2_support = y_req && alpm; in _psr_init_dpcd()
548 drm_dbg_kms(&i915->drm, "PSR2 %ssupported\n", in _psr_init_dpcd()
549 intel_dp->psr.sink_psr2_support ? "" : "not "); in _psr_init_dpcd()
557 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, in intel_psr_init_dpcd()
558 sizeof(intel_dp->psr_dpcd)); in intel_psr_init_dpcd()
560 if (intel_dp->psr_dpcd[0]) in intel_psr_init_dpcd()
563 if (intel_dp->psr.sink_psr2_support) { in intel_psr_init_dpcd()
564 intel_dp->psr.colorimetry_support = in intel_psr_init_dpcd()
573 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in hsw_psr_setup_aux()
580 [3] = 1 - 1, in hsw_psr_setup_aux()
589 intel_dp_aux_pack(&aux_msg[i], sizeof(aux_msg) - i)); in hsw_psr_setup_aux()
591 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); in hsw_psr_setup_aux()
594 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), in hsw_psr_setup_aux()
612 if (intel_dp->psr.panel_replay_enabled) in intel_psr_enable_sink()
615 if (intel_dp->psr.psr2_enabled) { in intel_psr_enable_sink()
617 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, in intel_psr_enable_sink()
623 if (intel_dp->psr.link_standby) in intel_psr_enable_sink()
630 if (intel_dp->psr.req_psr2_sdp_prior_scanline) in intel_psr_enable_sink()
633 if (intel_dp->psr.entry_setup_frames > 0) in intel_psr_enable_sink()
636 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); in intel_psr_enable_sink()
638 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); in intel_psr_enable_sink()
643 struct intel_connector *connector = intel_dp->attached_connector; in intel_psr1_get_tp_time()
650 if (dev_priv->display.params.psr_safest_params) { in intel_psr1_get_tp_time()
656 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) in intel_psr1_get_tp_time()
658 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) in intel_psr1_get_tp_time()
660 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) in intel_psr1_get_tp_time()
665 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) in intel_psr1_get_tp_time()
667 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) in intel_psr1_get_tp_time()
669 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) in intel_psr1_get_tp_time()
679 connector->panel.vbt.psr.tp1_wakeup_time_us == 0 && in intel_psr1_get_tp_time()
680 connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) in intel_psr1_get_tp_time()
685 drm_dp_tps3_supported(intel_dp->dpcd)) in intel_psr1_get_tp_time()
695 struct intel_connector *connector = intel_dp->attached_connector; in psr_compute_idle_frames()
700 * off-by-one issue that HW has in some cases. in psr_compute_idle_frames()
702 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); in psr_compute_idle_frames()
703 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); in psr_compute_idle_frames()
705 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) in psr_compute_idle_frames()
714 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in hsw_activate_psr1()
726 if (intel_dp->psr.link_standby) in hsw_activate_psr1()
735 val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); in hsw_activate_psr1()
743 struct intel_connector *connector = intel_dp->attached_connector; in intel_psr2_get_tp_time()
747 if (dev_priv->display.params.psr_safest_params) in intel_psr2_get_tp_time()
750 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && in intel_psr2_get_tp_time()
751 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) in intel_psr2_get_tp_time()
753 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) in intel_psr2_get_tp_time()
755 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) in intel_psr2_get_tp_time()
765 return intel_dp->psr.io_wake_lines < 9 && in psr2_block_count_lines()
766 intel_dp->psr.fast_wake_lines < 9 ? 8 : 12; in psr2_block_count_lines()
779 intel_dp->psr.sink_sync_latency + 1, in frames_before_su_entry()
783 if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry) in frames_before_su_entry()
784 frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1; in frames_before_su_entry()
793 intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), in dg2_activate_panel_replay()
796 intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, in dg2_activate_panel_replay()
803 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in hsw_activate_psr2()
826 /* Wa_22012278275:adl-p */ in hsw_activate_psr2()
844 tmp = map[intel_dp->psr.io_wake_lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; in hsw_activate_psr2()
847 tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; in hsw_activate_psr2()
850 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); in hsw_activate_psr2()
851 val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); in hsw_activate_psr2()
853 val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); in hsw_activate_psr2()
854 val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); in hsw_activate_psr2()
857 if (intel_dp->psr.req_psr2_sdp_prior_scanline) in hsw_activate_psr2()
861 psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); in hsw_activate_psr2()
863 if (intel_dp->psr.psr2_sel_fetch_enabled) { in hsw_activate_psr2()
867 drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); in hsw_activate_psr2()
896 if (!crtc_state->hw.active) in intel_get_frame_time_us()
900 drm_mode_vrefresh(&crtc_state->hw.adjusted_mode)); in intel_get_frame_time_us()
907 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr2_program_idle_frames()
935 mutex_lock(&intel_dp->psr.lock); in tgl_dc3co_disable_work()
937 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) in tgl_dc3co_disable_work()
942 mutex_unlock(&intel_dp->psr.lock); in tgl_dc3co_disable_work()
947 if (!intel_dp->psr.dc3co_exitline) in tgl_disallow_dc3co_on_psr2_exit()
950 cancel_delayed_work(&intel_dp->psr.dc3co_work); in tgl_disallow_dc3co_on_psr2_exit()
960 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; in dc3co_is_pipe_port_compatible()
962 enum port port = dig_port->base.port; in dc3co_is_pipe_port_compatible()
974 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; in tgl_dc3co_exitline_compute_config()
976 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; in tgl_dc3co_exitline_compute_config()
990 if (crtc_state->enable_psr2_sel_fetch) in tgl_dc3co_exitline_compute_config()
993 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO)) in tgl_dc3co_exitline_compute_config()
999 /* Wa_16011303918:adl-p */ in tgl_dc3co_exitline_compute_config()
1008 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; in tgl_dc3co_exitline_compute_config()
1010 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) in tgl_dc3co_exitline_compute_config()
1013 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; in tgl_dc3co_exitline_compute_config()
1021 if (!dev_priv->display.params.enable_psr2_sel_fetch && in intel_psr2_sel_fetch_config_valid()
1022 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { in intel_psr2_sel_fetch_config_valid()
1023 drm_dbg_kms(&dev_priv->drm, in intel_psr2_sel_fetch_config_valid()
1028 if (crtc_state->uapi.async_flip) { in intel_psr2_sel_fetch_config_valid()
1029 drm_dbg_kms(&dev_priv->drm, in intel_psr2_sel_fetch_config_valid()
1034 return crtc_state->enable_psr2_sel_fetch = true; in intel_psr2_sel_fetch_config_valid()
1041 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in psr2_granularity_check()
1042 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; in psr2_granularity_check()
1043 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; in psr2_granularity_check()
1047 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) in psr2_granularity_check()
1050 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) in psr2_granularity_check()
1054 if (!crtc_state->enable_psr2_sel_fetch) in psr2_granularity_check()
1055 return intel_dp->psr.su_y_granularity == 4; in psr2_granularity_check()
1063 y_granularity = intel_dp->psr.su_y_granularity; in psr2_granularity_check()
1064 else if (intel_dp->psr.su_y_granularity <= 2) in psr2_granularity_check()
1066 else if ((intel_dp->psr.su_y_granularity % 4) == 0) in psr2_granularity_check()
1067 y_granularity = intel_dp->psr.su_y_granularity; in psr2_granularity_check()
1072 if (crtc_state->dsc.compression_enable && in psr2_granularity_check()
1073 vdsc_cfg->slice_height % y_granularity) in psr2_granularity_check()
1076 crtc_state->su_y_granularity = y_granularity; in psr2_granularity_check()
1083 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; in _compute_psr2_sdp_prior_scanline_indication()
1087 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; in _compute_psr2_sdp_prior_scanline_indication()
1088 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); in _compute_psr2_sdp_prior_scanline_indication()
1091 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); in _compute_psr2_sdp_prior_scanline_indication()
1093 if ((hblank_ns - req_ns) > 100) in _compute_psr2_sdp_prior_scanline_indication()
1096 /* Not supported <13 / Wa_22012279113:adl-p */ in _compute_psr2_sdp_prior_scanline_indication()
1097 if (DISPLAY_VER(dev_priv) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b) in _compute_psr2_sdp_prior_scanline_indication()
1100 crtc_state->req_psr2_sdp_prior_scanline = true; in _compute_psr2_sdp_prior_scanline_indication()
1115 * it is not enough -> use 45 us. in _compute_psr2_wake_times()
1126 &crtc_state->hw.adjusted_mode, io_wake_time); in _compute_psr2_wake_times()
1128 &crtc_state->hw.adjusted_mode, fast_wake_time); in _compute_psr2_wake_times()
1134 if (i915->display.params.psr_safest_params) in _compute_psr2_wake_times()
1138 intel_dp->psr.io_wake_lines = max(io_wake_lines, 7); in _compute_psr2_wake_times()
1139 intel_dp->psr.fast_wake_lines = max(fast_wake_lines, 7); in _compute_psr2_wake_times()
1148 int psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); in intel_psr_entry_setup_frames()
1152 drm_dbg_kms(&i915->drm, in intel_psr_entry_setup_frames()
1154 intel_dp->psr_dpcd[1]); in intel_psr_entry_setup_frames()
1155 return -ETIME; in intel_psr_entry_setup_frames()
1159 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { in intel_psr_entry_setup_frames()
1163 drm_dbg_kms(&i915->drm, in intel_psr_entry_setup_frames()
1167 drm_dbg_kms(&i915->drm, in intel_psr_entry_setup_frames()
1170 return -ETIME; in intel_psr_entry_setup_frames()
1181 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; in intel_psr2_config_valid()
1182 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; in intel_psr2_config_valid()
1185 if (!intel_dp->psr.sink_psr2_support) in intel_psr2_config_valid()
1190 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n"); in intel_psr2_config_valid()
1197 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n"); in intel_psr2_config_valid()
1202 drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n"); in intel_psr2_config_valid()
1206 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { in intel_psr2_config_valid()
1207 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1209 transcoder_name(crtc_state->cpu_transcoder)); in intel_psr2_config_valid()
1214 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); in intel_psr2_config_valid()
1223 if (crtc_state->dsc.compression_enable && in intel_psr2_config_valid()
1225 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1230 if (crtc_state->crc_enabled) { in intel_psr2_config_valid()
1231 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1250 if (crtc_state->pipe_bpp > max_bpp) { in intel_psr2_config_valid()
1251 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1253 crtc_state->pipe_bpp, max_bpp); in intel_psr2_config_valid()
1257 /* Wa_16011303918:adl-p */ in intel_psr2_config_valid()
1258 if (crtc_state->vrr.enable && in intel_psr2_config_valid()
1260 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1266 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1272 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1278 if (crtc_state->hw.adjusted_mode.crtc_vblank_end - in intel_psr2_config_valid()
1279 crtc_state->hw.adjusted_mode.crtc_vblank_start < in intel_psr2_config_valid()
1281 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1289 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1296 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n"); in intel_psr2_config_valid()
1300 if (!crtc_state->enable_psr2_sel_fetch && in intel_psr2_config_valid()
1302 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1313 crtc_state->enable_psr2_sel_fetch = false; in intel_psr2_config_valid()
1321 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in _psr_compute_config()
1328 if (crtc_state->vrr.enable) in _psr_compute_config()
1337 intel_dp->psr.entry_setup_frames = entry_setup_frames; in _psr_compute_config()
1339 drm_dbg_kms(&dev_priv->drm, in _psr_compute_config()
1352 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_psr_compute_config()
1355 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); in intel_psr_compute_config()
1359 if (intel_dp->psr.sink_not_reliable) { in intel_psr_compute_config()
1360 drm_dbg_kms(&dev_priv->drm, in intel_psr_compute_config()
1361 "PSR sink implementation is not reliable\n"); in intel_psr_compute_config()
1365 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { in intel_psr_compute_config()
1366 drm_dbg_kms(&dev_priv->drm, in intel_psr_compute_config()
1372 crtc_state->has_panel_replay = true; in intel_psr_compute_config()
1374 crtc_state->has_psr = _psr_compute_config(intel_dp, crtc_state); in intel_psr_compute_config()
1376 if (!(crtc_state->has_panel_replay || crtc_state->has_psr)) in intel_psr_compute_config()
1379 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); in intel_psr_compute_config()
1381 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); in intel_psr_compute_config()
1383 &crtc_state->psr_vsc); in intel_psr_compute_config()
1389 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_psr_get_config()
1391 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_psr_get_config()
1398 intel_dp = &dig_port->dp; in intel_psr_get_config()
1402 mutex_lock(&intel_dp->psr.lock); in intel_psr_get_config()
1403 if (!intel_dp->psr.enabled) in intel_psr_get_config()
1406 if (intel_dp->psr.panel_replay_enabled) { in intel_psr_get_config()
1407 pipe_config->has_panel_replay = true; in intel_psr_get_config()
1413 pipe_config->has_psr = true; in intel_psr_get_config()
1416 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; in intel_psr_get_config()
1417 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); in intel_psr_get_config()
1419 if (!intel_dp->psr.psr2_enabled) in intel_psr_get_config()
1425 pipe_config->enable_psr2_sel_fetch = true; in intel_psr_get_config()
1430 pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val); in intel_psr_get_config()
1433 mutex_unlock(&intel_dp->psr.lock); in intel_psr_get_config()
1439 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_activate()
1441 drm_WARN_ON(&dev_priv->drm, in intel_psr_activate()
1445 drm_WARN_ON(&dev_priv->drm, in intel_psr_activate()
1448 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); in intel_psr_activate()
1450 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_activate()
1452 /* psr1, psr2 and panel-replay are mutually exclusive.*/ in intel_psr_activate()
1453 if (intel_dp->psr.panel_replay_enabled) in intel_psr_activate()
1455 else if (intel_dp->psr.psr2_enabled) in intel_psr_activate()
1460 intel_dp->psr.active = true; in intel_psr_activate()
1465 switch (intel_dp->psr.pipe) { in wa_16013835468_bit_get()
1475 MISSING_CASE(intel_dp->psr.pipe); in wa_16013835468_bit_get()
1492 set_wa_bit |= crtc_state->wm_level_disabled; in wm_optimization_wa()
1496 set_wa_bit |= crtc_state->hw.adjusted_mode.crtc_vblank_start != in wm_optimization_wa()
1497 crtc_state->hw.adjusted_mode.crtc_vdisplay; in wm_optimization_wa()
1511 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_enable_source()
1522 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also in intel_psr_enable_source()
1531 * For some unknown reason on HSW non-ULT (or at least on in intel_psr_enable_source()
1563 if (intel_dp->psr.dc3co_exitline) in intel_psr_enable_source()
1565 intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE); in intel_psr_enable_source()
1569 intel_dp->psr.psr2_sel_fetch_enabled ? in intel_psr_enable_source()
1578 if (intel_dp->psr.psr2_enabled) { in intel_psr_enable_source()
1586 * All supported adlp panels have 1-based X granularity, this may in intel_psr_enable_source()
1587 * cause issues if non-supported panels are used. in intel_psr_enable_source()
1608 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_interrupt_error_check()
1622 intel_dp->psr.sink_not_reliable = true; in psr_interrupt_error_check()
1623 drm_dbg_kms(&dev_priv->drm, in psr_interrupt_error_check()
1636 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); in intel_psr_enable_locked()
1637 struct intel_encoder *encoder = &dig_port->base; in intel_psr_enable_locked()
1640 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); in intel_psr_enable_locked()
1642 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; in intel_psr_enable_locked()
1643 intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; in intel_psr_enable_locked()
1644 intel_dp->psr.busy_frontbuffer_bits = 0; in intel_psr_enable_locked()
1645 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; in intel_psr_enable_locked()
1646 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; in intel_psr_enable_locked()
1649 intel_dp->psr.dc3co_exit_delay = val; in intel_psr_enable_locked()
1650 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; in intel_psr_enable_locked()
1651 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; in intel_psr_enable_locked()
1652 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; in intel_psr_enable_locked()
1653 intel_dp->psr.req_psr2_sdp_prior_scanline = in intel_psr_enable_locked()
1654 crtc_state->req_psr2_sdp_prior_scanline; in intel_psr_enable_locked()
1659 if (intel_dp->psr.panel_replay_enabled) in intel_psr_enable_locked()
1660 drm_dbg_kms(&dev_priv->drm, "Enabling Panel Replay\n"); in intel_psr_enable_locked()
1662 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", in intel_psr_enable_locked()
1663 intel_dp->psr.psr2_enabled ? "2" : "1"); in intel_psr_enable_locked()
1665 intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc); in intel_psr_enable_locked()
1669 intel_dp->psr.enabled = true; in intel_psr_enable_locked()
1670 intel_dp->psr.paused = false; in intel_psr_enable_locked()
1678 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_exit()
1681 if (!intel_dp->psr.active) { in intel_psr_exit()
1684 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); in intel_psr_exit()
1688 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); in intel_psr_exit()
1693 if (intel_dp->psr.panel_replay_enabled) { in intel_psr_exit()
1694 intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), in intel_psr_exit()
1696 } else if (intel_dp->psr.psr2_enabled) { in intel_psr_exit()
1702 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); in intel_psr_exit()
1707 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); in intel_psr_exit()
1709 intel_dp->psr.active = false; in intel_psr_exit()
1715 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_wait_exit_locked()
1719 if (intel_dp->psr.psr2_enabled) { in intel_psr_wait_exit_locked()
1730 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); in intel_psr_wait_exit_locked()
1736 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_disable_locked()
1738 dp_to_dig_port(intel_dp)->base.port); in intel_psr_disable_locked()
1740 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_disable_locked()
1742 if (!intel_dp->psr.enabled) in intel_psr_disable_locked()
1745 if (intel_dp->psr.panel_replay_enabled) in intel_psr_disable_locked()
1746 drm_dbg_kms(&dev_priv->drm, "Disabling Panel Replay\n"); in intel_psr_disable_locked()
1748 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", in intel_psr_disable_locked()
1749 intel_dp->psr.psr2_enabled ? "2" : "1"); in intel_psr_disable_locked()
1762 if (intel_dp->psr.psr2_enabled) { in intel_psr_disable_locked()
1776 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); in intel_psr_disable_locked()
1778 if (intel_dp->psr.psr2_enabled) in intel_psr_disable_locked()
1779 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); in intel_psr_disable_locked()
1781 intel_dp->psr.enabled = false; in intel_psr_disable_locked()
1782 intel_dp->psr.panel_replay_enabled = false; in intel_psr_disable_locked()
1783 intel_dp->psr.psr2_enabled = false; in intel_psr_disable_locked()
1784 intel_dp->psr.psr2_sel_fetch_enabled = false; in intel_psr_disable_locked()
1785 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; in intel_psr_disable_locked()
1789 * intel_psr_disable - Disable PSR
1800 if (!old_crtc_state->has_psr) in intel_psr_disable()
1803 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp))) in intel_psr_disable()
1806 mutex_lock(&intel_dp->psr.lock); in intel_psr_disable()
1810 mutex_unlock(&intel_dp->psr.lock); in intel_psr_disable()
1811 cancel_work_sync(&intel_dp->psr.work); in intel_psr_disable()
1812 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); in intel_psr_disable()
1816 * intel_psr_pause - Pause PSR
1824 struct intel_psr *psr = &intel_dp->psr; in intel_psr_pause()
1829 mutex_lock(&psr->lock); in intel_psr_pause()
1831 if (!psr->enabled) { in intel_psr_pause()
1832 mutex_unlock(&psr->lock); in intel_psr_pause()
1837 drm_WARN_ON(&dev_priv->drm, psr->paused); in intel_psr_pause()
1841 psr->paused = true; in intel_psr_pause()
1843 mutex_unlock(&psr->lock); in intel_psr_pause()
1845 cancel_work_sync(&psr->work); in intel_psr_pause()
1846 cancel_delayed_work_sync(&psr->dc3co_work); in intel_psr_pause()
1850 * intel_psr_resume - Resume PSR
1857 struct intel_psr *psr = &intel_dp->psr; in intel_psr_resume()
1862 mutex_lock(&psr->lock); in intel_psr_resume()
1864 if (!psr->paused) in intel_psr_resume()
1867 psr->paused = false; in intel_psr_resume()
1871 mutex_unlock(&psr->lock); in intel_psr_resume()
1904 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_force_hw_tracking_exit()
1906 if (intel_dp->psr.psr2_sel_fetch_enabled) in psr_force_hw_tracking_exit()
1918 * instead of disabling and re-enabling. in psr_force_hw_tracking_exit()
1927 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); in psr_force_hw_tracking_exit()
1932 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_psr2_program_trans_man_trk_ctl()
1933 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_psr2_program_trans_man_trk_ctl()
1936 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_program_trans_man_trk_ctl()
1939 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, in intel_psr2_program_trans_man_trk_ctl()
1940 crtc_state->uapi.encoder_mask) { in intel_psr2_program_trans_man_trk_ctl()
1943 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr2_program_trans_man_trk_ctl()
1944 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) in intel_psr2_program_trans_man_trk_ctl()
1950 crtc_state->psr2_man_track_ctl); in intel_psr2_program_trans_man_trk_ctl()
1956 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in psr2_man_trk_ctl_calc()
1957 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in psr2_man_trk_ctl_calc()
1969 if (clip->y1 == -1) in psr2_man_trk_ctl_calc()
1973 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1); in psr2_man_trk_ctl_calc()
1974 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1); in psr2_man_trk_ctl_calc()
1976 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); in psr2_man_trk_ctl_calc()
1978 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1); in psr2_man_trk_ctl_calc()
1979 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1); in psr2_man_trk_ctl_calc()
1982 crtc_state->psr2_man_track_ctl = val; in psr2_man_trk_ctl_calc()
1992 if (overlap_damage_area->y1 == -1) { in clip_area_update()
1993 overlap_damage_area->y1 = damage_area->y1; in clip_area_update()
1994 overlap_damage_area->y2 = damage_area->y2; in clip_area_update()
1998 if (damage_area->y1 < overlap_damage_area->y1) in clip_area_update()
1999 overlap_damage_area->y1 = damage_area->y1; in clip_area_update()
2001 if (damage_area->y2 > overlap_damage_area->y2) in clip_area_update()
2002 overlap_damage_area->y2 = damage_area->y2; in clip_area_update()
2008 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_psr2_sel_fetch_pipe_alignment()
2009 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_psr2_sel_fetch_pipe_alignment()
2013 if (crtc_state->dsc.compression_enable && in intel_psr2_sel_fetch_pipe_alignment()
2015 y_alignment = vdsc_cfg->slice_height; in intel_psr2_sel_fetch_pipe_alignment()
2017 y_alignment = crtc_state->su_y_granularity; in intel_psr2_sel_fetch_pipe_alignment()
2019 pipe_clip->y1 -= pipe_clip->y1 % y_alignment; in intel_psr2_sel_fetch_pipe_alignment()
2020 if (pipe_clip->y2 % y_alignment) in intel_psr2_sel_fetch_pipe_alignment()
2021 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment; in intel_psr2_sel_fetch_pipe_alignment()
2035 if (plane_state->uapi.dst.y1 < 0 || in psr2_sel_fetch_plane_state_supported()
2036 plane_state->uapi.dst.x1 < 0 || in psr2_sel_fetch_plane_state_supported()
2037 plane_state->scaler_id >= 0 || in psr2_sel_fetch_plane_state_supported()
2038 plane_state->uapi.rotation != DRM_MODE_ROTATE_0) in psr2_sel_fetch_plane_state_supported()
2053 if (crtc_state->scaler_state.scaler_id >= 0) in psr2_sel_fetch_pipe_state_supported()
2062 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_psr2_sel_fetch_update()
2064 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; in intel_psr2_sel_fetch_update()
2070 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_sel_fetch_update()
2086 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, in intel_psr2_sel_fetch_update()
2089 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) in intel_psr2_sel_fetch_update()
2092 if (!new_plane_state->uapi.visible && in intel_psr2_sel_fetch_update()
2093 !old_plane_state->uapi.visible) in intel_psr2_sel_fetch_update()
2106 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || in intel_psr2_sel_fetch_update()
2107 !drm_rect_equals(&new_plane_state->uapi.dst, in intel_psr2_sel_fetch_update()
2108 &old_plane_state->uapi.dst)) { in intel_psr2_sel_fetch_update()
2109 if (old_plane_state->uapi.visible) { in intel_psr2_sel_fetch_update()
2110 damaged_area.y1 = old_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2111 damaged_area.y2 = old_plane_state->uapi.dst.y2; in intel_psr2_sel_fetch_update()
2113 &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2116 if (new_plane_state->uapi.visible) { in intel_psr2_sel_fetch_update()
2117 damaged_area.y1 = new_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2118 damaged_area.y2 = new_plane_state->uapi.dst.y2; in intel_psr2_sel_fetch_update()
2120 &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2123 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { in intel_psr2_sel_fetch_update()
2125 damaged_area.y1 = new_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2126 damaged_area.y2 = new_plane_state->uapi.dst.y2; in intel_psr2_sel_fetch_update()
2128 &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2132 src = drm_plane_state_src(&new_plane_state->uapi); in intel_psr2_sel_fetch_update()
2135 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi, in intel_psr2_sel_fetch_update()
2136 &new_plane_state->uapi, &damaged_area)) in intel_psr2_sel_fetch_update()
2139 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; in intel_psr2_sel_fetch_update()
2140 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; in intel_psr2_sel_fetch_update()
2141 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; in intel_psr2_sel_fetch_update()
2142 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; in intel_psr2_sel_fetch_update()
2144 clip_area_update(&pipe_clip, &damaged_area, &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2153 if (pipe_clip.y1 == -1) { in intel_psr2_sel_fetch_update()
2154 drm_info_once(&dev_priv->drm, in intel_psr2_sel_fetch_update()
2156 pipe_name(crtc->pipe)); in intel_psr2_sel_fetch_update()
2166 crtc_state->splitter.enable) in intel_psr2_sel_fetch_update()
2169 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); in intel_psr2_sel_fetch_update()
2182 struct intel_plane *linked = new_plane_state->planar_linked_plane; in intel_psr2_sel_fetch_update()
2184 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || in intel_psr2_sel_fetch_update()
2185 !new_plane_state->uapi.visible) in intel_psr2_sel_fetch_update()
2189 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; in intel_psr2_sel_fetch_update()
2190 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) { in intel_psr2_sel_fetch_update()
2191 sel_fetch_area->y1 = -1; in intel_psr2_sel_fetch_update()
2192 sel_fetch_area->y2 = -1; in intel_psr2_sel_fetch_update()
2194 * if plane sel fetch was previously enabled -> in intel_psr2_sel_fetch_update()
2197 if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0) in intel_psr2_sel_fetch_update()
2198 crtc_state->update_planes |= BIT(plane->id); in intel_psr2_sel_fetch_update()
2208 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; in intel_psr2_sel_fetch_update()
2209 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2210 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2211 crtc_state->update_planes |= BIT(plane->id); in intel_psr2_sel_fetch_update()
2225 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; in intel_psr2_sel_fetch_update()
2226 linked_sel_fetch_area->y1 = sel_fetch_area->y1; in intel_psr2_sel_fetch_update()
2227 linked_sel_fetch_area->y2 = sel_fetch_area->y2; in intel_psr2_sel_fetch_update()
2228 crtc_state->update_planes |= BIT(linked->id); in intel_psr2_sel_fetch_update()
2240 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_psr_pre_plane_update()
2250 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, in intel_psr_pre_plane_update()
2251 old_crtc_state->uapi.encoder_mask) { in intel_psr_pre_plane_update()
2253 struct intel_psr *psr = &intel_dp->psr; in intel_psr_pre_plane_update()
2256 mutex_lock(&psr->lock); in intel_psr_pre_plane_update()
2260 * - PSR disabled in new state in intel_psr_pre_plane_update()
2261 * - All planes will go inactive in intel_psr_pre_plane_update()
2262 * - Changing between PSR versions in intel_psr_pre_plane_update()
2263 * - Display WA #1136: skl, bxt in intel_psr_pre_plane_update()
2266 needs_to_disable |= !new_crtc_state->has_psr; in intel_psr_pre_plane_update()
2267 needs_to_disable |= !new_crtc_state->active_planes; in intel_psr_pre_plane_update()
2268 needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled; in intel_psr_pre_plane_update()
2270 new_crtc_state->wm_level_disabled; in intel_psr_pre_plane_update()
2272 if (psr->enabled && needs_to_disable) in intel_psr_pre_plane_update()
2274 else if (psr->enabled && new_crtc_state->wm_level_disabled) in intel_psr_pre_plane_update()
2278 mutex_unlock(&psr->lock); in intel_psr_pre_plane_update()
2285 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_psr_post_plane_update()
2290 if (!(crtc_state->has_psr || crtc_state->has_panel_replay)) in intel_psr_post_plane_update()
2293 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, in intel_psr_post_plane_update()
2294 crtc_state->uapi.encoder_mask) { in intel_psr_post_plane_update()
2296 struct intel_psr *psr = &intel_dp->psr; in intel_psr_post_plane_update()
2299 mutex_lock(&psr->lock); in intel_psr_post_plane_update()
2301 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes); in intel_psr_post_plane_update()
2303 keep_disabled |= psr->sink_not_reliable; in intel_psr_post_plane_update()
2304 keep_disabled |= !crtc_state->active_planes; in intel_psr_post_plane_update()
2308 crtc_state->wm_level_disabled; in intel_psr_post_plane_update()
2310 if (!psr->enabled && !keep_disabled) in intel_psr_post_plane_update()
2312 else if (psr->enabled && !crtc_state->wm_level_disabled) in intel_psr_post_plane_update()
2317 if (crtc_state->crc_enabled && psr->enabled) in intel_psr_post_plane_update()
2322 * invalidate -> flip -> flush sequence. in intel_psr_post_plane_update()
2324 intel_dp->psr.busy_frontbuffer_bits = 0; in intel_psr_post_plane_update()
2326 mutex_unlock(&psr->lock); in intel_psr_post_plane_update()
2333 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr2_ready_for_pipe_update_locked()
2348 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr1_ready_for_pipe_update_locked()
2362 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
2370 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev); in intel_psr_wait_for_idle_locked()
2373 if (!new_crtc_state->has_psr) in intel_psr_wait_for_idle_locked()
2376 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, in intel_psr_wait_for_idle_locked()
2377 new_crtc_state->uapi.encoder_mask) { in intel_psr_wait_for_idle_locked()
2381 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_wait_for_idle_locked()
2383 if (!intel_dp->psr.enabled) in intel_psr_wait_for_idle_locked()
2386 if (intel_dp->psr.psr2_enabled) in intel_psr_wait_for_idle_locked()
2392 drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n"); in intel_psr_wait_for_idle_locked()
2399 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in __psr_wait_for_idle_locked()
2404 if (!intel_dp->psr.enabled) in __psr_wait_for_idle_locked()
2407 if (intel_dp->psr.psr2_enabled) { in __psr_wait_for_idle_locked()
2415 mutex_unlock(&intel_dp->psr.lock); in __psr_wait_for_idle_locked()
2419 drm_err(&dev_priv->drm, in __psr_wait_for_idle_locked()
2420 "Timed out waiting for PSR Idle for re-enable\n"); in __psr_wait_for_idle_locked()
2423 mutex_lock(&intel_dp->psr.lock); in __psr_wait_for_idle_locked()
2424 return err == 0 && intel_dp->psr.enabled; in __psr_wait_for_idle_locked()
2435 state = drm_atomic_state_alloc(&dev_priv->drm); in intel_psr_fastset_force()
2437 return -ENOMEM; in intel_psr_fastset_force()
2441 state->acquire_ctx = &ctx; in intel_psr_fastset_force()
2442 to_intel_atomic_state(state)->internal = true; in intel_psr_fastset_force()
2445 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); in intel_psr_fastset_force()
2450 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) in intel_psr_fastset_force()
2459 if (!conn_state->crtc) in intel_psr_fastset_force()
2462 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); in intel_psr_fastset_force()
2468 /* Mark mode as changed to trigger a pipe->update() */ in intel_psr_fastset_force()
2469 crtc_state->mode_changed = true; in intel_psr_fastset_force()
2476 if (err == -EDEADLK) { in intel_psr_fastset_force()
2499 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); in intel_psr_debug_set()
2500 return -EINVAL; in intel_psr_debug_set()
2503 ret = mutex_lock_interruptible(&intel_dp->psr.lock); in intel_psr_debug_set()
2507 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; in intel_psr_debug_set()
2508 intel_dp->psr.debug = val; in intel_psr_debug_set()
2514 if (intel_dp->psr.enabled) in intel_psr_debug_set()
2517 mutex_unlock(&intel_dp->psr.lock); in intel_psr_debug_set()
2527 struct intel_psr *psr = &intel_dp->psr; in intel_psr_handle_irq()
2530 psr->sink_not_reliable = true; in intel_psr_handle_irq()
2532 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); in intel_psr_handle_irq()
2540 mutex_lock(&intel_dp->psr.lock); in intel_psr_work()
2542 if (!intel_dp->psr.enabled) in intel_psr_work()
2545 if (READ_ONCE(intel_dp->psr.irq_aux_error)) in intel_psr_work()
2549 * We have to make sure PSR is ready for re-enable in intel_psr_work()
2552 * and be ready for re-enable. in intel_psr_work()
2562 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) in intel_psr_work()
2567 mutex_unlock(&intel_dp->psr.lock); in intel_psr_work()
2573 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr_invalidate_handle()
2575 if (intel_dp->psr.psr2_sel_fetch_enabled) { in _psr_invalidate_handle()
2578 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { in _psr_invalidate_handle()
2580 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); in _psr_invalidate_handle()
2588 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); in _psr_invalidate_handle()
2589 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; in _psr_invalidate_handle()
2596 * intel_psr_invalidate - Invalidate PSR
2616 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_psr_invalidate()
2620 mutex_lock(&intel_dp->psr.lock); in intel_psr_invalidate()
2621 if (!intel_dp->psr.enabled) { in intel_psr_invalidate()
2622 mutex_unlock(&intel_dp->psr.lock); in intel_psr_invalidate()
2627 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); in intel_psr_invalidate()
2628 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; in intel_psr_invalidate()
2633 mutex_unlock(&intel_dp->psr.lock); in intel_psr_invalidate()
2648 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled || in tgl_dc3co_flush_locked()
2649 !intel_dp->psr.active) in tgl_dc3co_flush_locked()
2653 * At every frontbuffer flush flip event modified delay of delayed work, in tgl_dc3co_flush_locked()
2657 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) in tgl_dc3co_flush_locked()
2661 mod_delayed_work(i915->unordered_wq, &intel_dp->psr.dc3co_work, in tgl_dc3co_flush_locked()
2662 intel_dp->psr.dc3co_exit_delay); in tgl_dc3co_flush_locked()
2668 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr_flush_handle()
2670 if (intel_dp->psr.psr2_sel_fetch_enabled) { in _psr_flush_handle()
2671 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { in _psr_flush_handle()
2673 if (intel_dp->psr.busy_frontbuffer_bits == 0) { in _psr_flush_handle()
2687 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); in _psr_flush_handle()
2688 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; in _psr_flush_handle()
2700 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) in _psr_flush_handle()
2701 queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); in _psr_flush_handle()
2706 * intel_psr_flush - Flush PSR
2723 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_psr_flush()
2727 mutex_lock(&intel_dp->psr.lock); in intel_psr_flush()
2728 if (!intel_dp->psr.enabled) { in intel_psr_flush()
2729 mutex_unlock(&intel_dp->psr.lock); in intel_psr_flush()
2734 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); in intel_psr_flush()
2735 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; in intel_psr_flush()
2742 if (intel_dp->psr.paused) in intel_psr_flush()
2747 !intel_dp->psr.psr2_sel_fetch_enabled)) { in intel_psr_flush()
2758 mutex_unlock(&intel_dp->psr.lock); in intel_psr_flush()
2763 * intel_psr_init - Init basic PSR work and mutex.
2772 struct intel_connector *connector = intel_dp->attached_connector; in intel_psr_init()
2788 if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) { in intel_psr_init()
2789 drm_dbg_kms(&dev_priv->drm, in intel_psr_init()
2795 intel_dp->psr.source_panel_replay_support = true; in intel_psr_init()
2797 intel_dp->psr.source_support = true; in intel_psr_init()
2802 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; in intel_psr_init()
2804 INIT_WORK(&intel_dp->psr.work, intel_psr_work); in intel_psr_init()
2805 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); in intel_psr_init()
2806 mutex_init(&intel_dp->psr.lock); in intel_psr_init()
2812 struct drm_dp_aux *aux = &intel_dp->aux; in psr_get_status_and_error_status()
2816 offset = intel_dp->psr.panel_replay_enabled ? in psr_get_status_and_error_status()
2823 offset = intel_dp->psr.panel_replay_enabled ? in psr_get_status_and_error_status()
2838 struct drm_dp_aux *aux = &intel_dp->aux; in psr_alpm_check()
2839 struct intel_psr *psr = &intel_dp->psr; in psr_alpm_check()
2843 if (!psr->psr2_enabled) in psr_alpm_check()
2848 drm_err(&dev_priv->drm, "Error reading ALPM status\n"); in psr_alpm_check()
2854 psr->sink_not_reliable = true; in psr_alpm_check()
2855 drm_dbg_kms(&dev_priv->drm, in psr_alpm_check()
2866 struct intel_psr *psr = &intel_dp->psr; in psr_capability_changed_check()
2870 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); in psr_capability_changed_check()
2872 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); in psr_capability_changed_check()
2878 psr->sink_not_reliable = true; in psr_capability_changed_check()
2879 drm_dbg_kms(&dev_priv->drm, in psr_capability_changed_check()
2883 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); in psr_capability_changed_check()
2890 struct intel_psr *psr = &intel_dp->psr; in intel_psr_short_pulse()
2899 mutex_lock(&psr->lock); in intel_psr_short_pulse()
2901 if (!psr->enabled) in intel_psr_short_pulse()
2905 drm_err(&dev_priv->drm, in intel_psr_short_pulse()
2912 psr->sink_not_reliable = true; in intel_psr_short_pulse()
2916 drm_dbg_kms(&dev_priv->drm, in intel_psr_short_pulse()
2919 drm_dbg_kms(&dev_priv->drm, in intel_psr_short_pulse()
2922 drm_dbg_kms(&dev_priv->drm, in intel_psr_short_pulse()
2925 drm_dbg_kms(&dev_priv->drm, in intel_psr_short_pulse()
2929 drm_err(&dev_priv->drm, in intel_psr_short_pulse()
2933 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); in intel_psr_short_pulse()
2939 mutex_unlock(&psr->lock); in intel_psr_short_pulse()
2949 mutex_lock(&intel_dp->psr.lock); in intel_psr_enabled()
2950 ret = intel_dp->psr.enabled; in intel_psr_enabled()
2951 mutex_unlock(&intel_dp->psr.lock); in intel_psr_enabled()
2957 * intel_psr_lock - grab PSR lock
2966 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in intel_psr_lock()
2969 if (!crtc_state->has_psr) in intel_psr_lock()
2972 for_each_intel_encoder_mask_with_psr(&i915->drm, encoder, in intel_psr_lock()
2973 crtc_state->uapi.encoder_mask) { in intel_psr_lock()
2976 mutex_lock(&intel_dp->psr.lock); in intel_psr_lock()
2982 * intel_psr_unlock - release PSR lock
2989 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in intel_psr_unlock()
2992 if (!crtc_state->has_psr) in intel_psr_unlock()
2995 for_each_intel_encoder_mask_with_psr(&i915->drm, encoder, in intel_psr_unlock()
2996 crtc_state->uapi.encoder_mask) { in intel_psr_unlock()
2999 mutex_unlock(&intel_dp->psr.lock); in intel_psr_unlock()
3008 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_source_status()
3012 if (intel_dp->psr.psr2_enabled) { in psr_source_status()
3053 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_status()
3054 struct intel_psr *psr = &intel_dp->psr; in intel_psr_status()
3061 str_yes_no(psr->sink_support)); in intel_psr_status()
3063 if (psr->sink_support) in intel_psr_status()
3064 seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); in intel_psr_status()
3065 seq_printf(m, ", Panel Replay = %s\n", str_yes_no(psr->sink_panel_replay_support)); in intel_psr_status()
3067 if (!(psr->sink_support || psr->sink_panel_replay_support)) in intel_psr_status()
3070 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); in intel_psr_status()
3071 mutex_lock(&psr->lock); in intel_psr_status()
3073 if (psr->panel_replay_enabled) in intel_psr_status()
3075 else if (psr->enabled) in intel_psr_status()
3076 status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled"; in intel_psr_status()
3081 if (!psr->enabled) { in intel_psr_status()
3082 seq_printf(m, "PSR sink not reliable: %s\n", in intel_psr_status()
3083 str_yes_no(psr->sink_not_reliable)); in intel_psr_status()
3088 if (psr->panel_replay_enabled) { in intel_psr_status()
3091 } else if (psr->psr2_enabled) { in intel_psr_status()
3102 psr->busy_frontbuffer_bits); in intel_psr_status()
3111 if (psr->debug & I915_PSR_DEBUG_IRQ) { in intel_psr_status()
3113 psr->last_entry_attempt); in intel_psr_status()
3114 seq_printf(m, "Last exit at: %lld\n", psr->last_exit); in intel_psr_status()
3117 if (psr->psr2_enabled) { in intel_psr_status()
3142 str_enabled_disabled(psr->psr2_sel_fetch_enabled)); in intel_psr_status()
3146 mutex_unlock(&psr->lock); in intel_psr_status()
3147 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); in intel_psr_status()
3154 struct drm_i915_private *dev_priv = m->private; in i915_edp_psr_status_show()
3159 return -ENODEV; in i915_edp_psr_status_show()
3162 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in i915_edp_psr_status_show()
3168 return -ENODEV; in i915_edp_psr_status_show()
3180 int ret = -ENODEV; in i915_edp_psr_debug_set()
3185 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in i915_edp_psr_debug_set()
3188 drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val); in i915_edp_psr_debug_set()
3190 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); in i915_edp_psr_debug_set()
3195 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); in i915_edp_psr_debug_set()
3208 return -ENODEV; in i915_edp_psr_debug_get()
3210 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in i915_edp_psr_debug_get()
3214 *val = READ_ONCE(intel_dp->psr.debug); in i915_edp_psr_debug_get()
3218 return -ENODEV; in i915_edp_psr_debug_get()
3227 struct drm_minor *minor = i915->drm.primary; in intel_psr_debugfs_register()
3229 debugfs_create_file("i915_edp_psr_debug", 0644, minor->debugfs_root, in intel_psr_debugfs_register()
3232 debugfs_create_file("i915_edp_psr_status", 0444, minor->debugfs_root, in intel_psr_debugfs_register()
3238 if (intel_dp->psr.panel_replay_enabled) in psr_mode_str()
3239 return "PANEL-REPLAY"; in psr_mode_str()
3240 else if (intel_dp->psr.enabled) in psr_mode_str()
3248 struct intel_connector *connector = m->private; in i915_psr_sink_status_show()
3255 "transition to inactive, capture and display, timing re-sync", in i915_psr_sink_status_show()
3264 "Sink device in the process of re-locking with the Source device", in i915_psr_sink_status_show()
3272 seq_puts(m, "PSR/Panel-Replay Unsupported\n"); in i915_psr_sink_status_show()
3273 return -ENODEV; in i915_psr_sink_status_show()
3276 if (connector->base.status != connector_status_connected) in i915_psr_sink_status_show()
3277 return -ENODEV; in i915_psr_sink_status_show()
3284 if (intel_dp->psr.panel_replay_enabled) { in i915_psr_sink_status_show()
3288 } else if (intel_dp->psr.enabled) { in i915_psr_sink_status_show()
3317 struct intel_connector *connector = m->private; in i915_psr_status_show()
3326 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_psr_connector_debugfs_add()
3327 struct dentry *root = connector->base.debugfs_entry; in intel_psr_connector_debugfs_add()
3330 if ((connector->base.connector_type != DRM_MODE_CONNECTOR_eDP && in intel_psr_connector_debugfs_add()
3331 connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) || in intel_psr_connector_debugfs_add()
3332 connector->mst_port) in intel_psr_connector_debugfs_add()