Lines Matching +full:vdd +full:- +full:s
1 // SPDX-License-Identifier: MIT
31 switch (pps->pps_pipe) { in pps_name()
43 MISSING_CASE(pps->pps_pipe); in pps_name()
47 switch (pps->pps_idx) { in pps_name()
53 MISSING_CASE(pps->pps_idx); in pps_name()
70 mutex_lock(&dev_priv->display.pps.mutex); in intel_pps_lock()
80 mutex_unlock(&dev_priv->display.pps.mutex); in intel_pps_unlock()
91 enum pipe pipe = intel_dp->pps.pps_pipe; in vlv_power_sequencer_kick()
97 if (drm_WARN(&dev_priv->drm, in vlv_power_sequencer_kick()
98 intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN, in vlv_power_sequencer_kick()
99 "skipping %s kick due to [ENCODER:%d:%s] being active\n", in vlv_power_sequencer_kick()
100 pps_name(dev_priv, &intel_dp->pps), in vlv_power_sequencer_kick()
101 dig_port->base.base.base.id, dig_port->base.base.name)) in vlv_power_sequencer_kick()
104 drm_dbg_kms(&dev_priv->drm, in vlv_power_sequencer_kick()
105 "kicking %s for [ENCODER:%d:%s]\n", in vlv_power_sequencer_kick()
106 pps_name(dev_priv, &intel_dp->pps), in vlv_power_sequencer_kick()
107 dig_port->base.base.base.id, dig_port->base.base.name); in vlv_power_sequencer_kick()
109 /* Preserve the BIOS-computed detected bit. This is in vlv_power_sequencer_kick()
110 * supposed to be read-only. in vlv_power_sequencer_kick()
112 DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; in vlv_power_sequencer_kick()
126 * So enable temporarily it if it's not already enabled. in vlv_power_sequencer_kick()
133 drm_err(&dev_priv->drm, in vlv_power_sequencer_kick()
144 * Otherwise even VDD force bit won't work. in vlv_power_sequencer_kick()
146 intel_de_write(dev_priv, intel_dp->output_reg, DP); in vlv_power_sequencer_kick()
147 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
149 intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN); in vlv_power_sequencer_kick()
150 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
152 intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN); in vlv_power_sequencer_kick()
153 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
170 * Pick one that's not used by other ports. in vlv_find_free_pps()
172 for_each_intel_dp(&dev_priv->drm, encoder) { in vlv_find_free_pps()
175 if (encoder->type == INTEL_OUTPUT_EDP) { in vlv_find_free_pps()
176 drm_WARN_ON(&dev_priv->drm, in vlv_find_free_pps()
177 intel_dp->pps.active_pipe != INVALID_PIPE && in vlv_find_free_pps()
178 intel_dp->pps.active_pipe != in vlv_find_free_pps()
179 intel_dp->pps.pps_pipe); in vlv_find_free_pps()
181 if (intel_dp->pps.pps_pipe != INVALID_PIPE) in vlv_find_free_pps()
182 pipes &= ~(1 << intel_dp->pps.pps_pipe); in vlv_find_free_pps()
184 drm_WARN_ON(&dev_priv->drm, in vlv_find_free_pps()
185 intel_dp->pps.pps_pipe != INVALID_PIPE); in vlv_find_free_pps()
187 if (intel_dp->pps.active_pipe != INVALID_PIPE) in vlv_find_free_pps()
188 pipes &= ~(1 << intel_dp->pps.active_pipe); in vlv_find_free_pps()
195 return ffs(pipes) - 1; in vlv_find_free_pps()
205 lockdep_assert_held(&dev_priv->display.pps.mutex); in vlv_power_sequencer_pipe()
208 drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); in vlv_power_sequencer_pipe()
210 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE && in vlv_power_sequencer_pipe()
211 intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe); in vlv_power_sequencer_pipe()
213 if (intel_dp->pps.pps_pipe != INVALID_PIPE) in vlv_power_sequencer_pipe()
214 return intel_dp->pps.pps_pipe; in vlv_power_sequencer_pipe()
222 if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE)) in vlv_power_sequencer_pipe()
226 intel_dp->pps.pps_pipe = pipe; in vlv_power_sequencer_pipe()
228 drm_dbg_kms(&dev_priv->drm, in vlv_power_sequencer_pipe()
229 "picked %s for [ENCODER:%d:%s]\n", in vlv_power_sequencer_pipe()
230 pps_name(dev_priv, &intel_dp->pps), in vlv_power_sequencer_pipe()
231 dig_port->base.base.base.id, dig_port->base.base.name); in vlv_power_sequencer_pipe()
238 * Even vdd force doesn't work until we've made in vlv_power_sequencer_pipe()
243 return intel_dp->pps.pps_pipe; in vlv_power_sequencer_pipe()
250 int pps_idx = intel_dp->pps.pps_idx; in bxt_power_sequencer_idx()
252 lockdep_assert_held(&dev_priv->display.pps.mutex); in bxt_power_sequencer_idx()
255 drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); in bxt_power_sequencer_idx()
257 if (!intel_dp->pps.pps_reset) in bxt_power_sequencer_idx()
260 intel_dp->pps.pps_reset = false; in bxt_power_sequencer_idx()
315 enum port port = dig_port->base.port; in vlv_initial_power_sequencer_setup()
317 lockdep_assert_held(&dev_priv->display.pps.mutex); in vlv_initial_power_sequencer_setup()
321 intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port, in vlv_initial_power_sequencer_setup()
323 /* didn't find one? pick one where vdd is on */ in vlv_initial_power_sequencer_setup()
324 if (intel_dp->pps.pps_pipe == INVALID_PIPE) in vlv_initial_power_sequencer_setup()
325 intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port, in vlv_initial_power_sequencer_setup()
328 if (intel_dp->pps.pps_pipe == INVALID_PIPE) in vlv_initial_power_sequencer_setup()
329 intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port, in vlv_initial_power_sequencer_setup()
333 if (intel_dp->pps.pps_pipe == INVALID_PIPE) { in vlv_initial_power_sequencer_setup()
334 drm_dbg_kms(&dev_priv->drm, in vlv_initial_power_sequencer_setup()
335 "[ENCODER:%d:%s] no initial power sequencer\n", in vlv_initial_power_sequencer_setup()
336 dig_port->base.base.base.id, dig_port->base.base.name); in vlv_initial_power_sequencer_setup()
340 drm_dbg_kms(&dev_priv->drm, in vlv_initial_power_sequencer_setup()
341 "[ENCODER:%d:%s] initial power sequencer: %s\n", in vlv_initial_power_sequencer_setup()
342 dig_port->base.base.base.id, dig_port->base.base.name, in vlv_initial_power_sequencer_setup()
343 pps_name(dev_priv, &intel_dp->pps)); in vlv_initial_power_sequencer_setup()
367 if (intel_dp->pps.pps_idx == 1 && in intel_pps_is_valid()
385 return -1; in bxt_initial_pps_idx()
391 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in pps_initial_setup()
392 struct intel_connector *connector = intel_dp->attached_connector; in pps_initial_setup()
393 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in pps_initial_setup()
395 lockdep_assert_held(&i915->display.pps.mutex); in pps_initial_setup()
404 intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller; in pps_initial_setup()
406 intel_dp->pps.pps_idx = 0; in pps_initial_setup()
408 if (drm_WARN_ON(&i915->drm, intel_dp->pps.pps_idx >= intel_num_pps(i915))) in pps_initial_setup()
409 intel_dp->pps.pps_idx = -1; in pps_initial_setup()
412 if (intel_dp->pps.pps_idx < 0) in pps_initial_setup()
413 intel_dp->pps.pps_idx = bxt_initial_pps_idx(i915, pps_has_pp_on); in pps_initial_setup()
414 /* didn't find one? pick one where vdd is on */ in pps_initial_setup()
415 if (intel_dp->pps.pps_idx < 0) in pps_initial_setup()
416 intel_dp->pps.pps_idx = bxt_initial_pps_idx(i915, pps_has_vdd_on); in pps_initial_setup()
418 if (intel_dp->pps.pps_idx < 0) { in pps_initial_setup()
419 intel_dp->pps.pps_idx = bxt_initial_pps_idx(i915, pps_any); in pps_initial_setup()
421 drm_dbg_kms(&i915->drm, in pps_initial_setup()
422 "[ENCODER:%d:%s] no initial power sequencer, assuming %s\n", in pps_initial_setup()
423 encoder->base.base.id, encoder->base.name, in pps_initial_setup()
424 pps_name(i915, &intel_dp->pps)); in pps_initial_setup()
426 drm_dbg_kms(&i915->drm, in pps_initial_setup()
427 "[ENCODER:%d:%s] initial power sequencer: %s\n", in pps_initial_setup()
428 encoder->base.base.id, encoder->base.name, in pps_initial_setup()
429 pps_name(i915, &intel_dp->pps)); in pps_initial_setup()
439 if (drm_WARN_ON(&dev_priv->drm, !IS_LP(dev_priv))) in intel_pps_reset_all()
455 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_pps_reset_all()
458 drm_WARN_ON(&dev_priv->drm, in intel_pps_reset_all()
459 intel_dp->pps.active_pipe != INVALID_PIPE); in intel_pps_reset_all()
461 if (encoder->type != INTEL_OUTPUT_EDP) in intel_pps_reset_all()
465 intel_dp->pps.pps_reset = true; in intel_pps_reset_all()
467 intel_dp->pps.pps_pipe = INVALID_PIPE; in intel_pps_reset_all()
492 pps_idx = intel_dp->pps.pps_idx; in intel_pps_get_registers()
494 regs->pp_ctrl = PP_CONTROL(pps_idx); in intel_pps_get_registers()
495 regs->pp_stat = PP_STATUS(pps_idx); in intel_pps_get_registers()
496 regs->pp_on = PP_ON_DELAYS(pps_idx); in intel_pps_get_registers()
497 regs->pp_off = PP_OFF_DELAYS(pps_idx); in intel_pps_get_registers()
502 regs->pp_div = INVALID_MMIO_REG; in intel_pps_get_registers()
504 regs->pp_div = PP_DIVISOR(pps_idx); in intel_pps_get_registers()
531 lockdep_assert_held(&dev_priv->display.pps.mutex); in edp_have_panel_power()
534 intel_dp->pps.pps_pipe == INVALID_PIPE) in edp_have_panel_power()
544 lockdep_assert_held(&dev_priv->display.pps.mutex); in edp_have_panel_vdd()
547 intel_dp->pps.pps_pipe == INVALID_PIPE) in edp_have_panel_vdd()
562 drm_WARN(&dev_priv->drm, 1, in intel_pps_check_power_unlocked()
563 "[ENCODER:%d:%s] %s powered off while attempting AUX CH communication.\n", in intel_pps_check_power_unlocked()
564 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_check_power_unlocked()
565 pps_name(dev_priv, &intel_dp->pps)); in intel_pps_check_power_unlocked()
566 drm_dbg_kms(&dev_priv->drm, in intel_pps_check_power_unlocked()
567 "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in intel_pps_check_power_unlocked()
568 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_check_power_unlocked()
569 pps_name(dev_priv, &intel_dp->pps), in intel_pps_check_power_unlocked()
593 lockdep_assert_held(&dev_priv->display.pps.mutex); in wait_panel_status()
600 drm_dbg_kms(&dev_priv->drm, in wait_panel_status()
601 "[ENCODER:%d:%s] %s mask: 0x%08x value: 0x%08x PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in wait_panel_status()
602 dig_port->base.base.base.id, dig_port->base.base.name, in wait_panel_status()
603 pps_name(dev_priv, &intel_dp->pps), in wait_panel_status()
610 drm_err(&dev_priv->drm, in wait_panel_status()
611 "[ENCODER:%d:%s] %s panel status timeout: PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in wait_panel_status()
612 dig_port->base.base.base.id, dig_port->base.base.name, in wait_panel_status()
613 pps_name(dev_priv, &intel_dp->pps), in wait_panel_status()
617 drm_dbg_kms(&dev_priv->drm, "Wait complete\n"); in wait_panel_status()
625 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] %s wait for panel power on\n", in wait_panel_on()
626 dig_port->base.base.base.id, dig_port->base.base.name, in wait_panel_on()
627 pps_name(i915, &intel_dp->pps)); in wait_panel_on()
636 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] %s wait for panel power off time\n", in wait_panel_off()
637 dig_port->base.base.base.id, dig_port->base.base.name, in wait_panel_off()
638 pps_name(i915, &intel_dp->pps)); in wait_panel_off()
649 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] %s wait for panel power cycle\n", in wait_panel_power_cycle()
650 dig_port->base.base.base.id, dig_port->base.base.name, in wait_panel_power_cycle()
651 pps_name(i915, &intel_dp->pps)); in wait_panel_power_cycle()
656 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time); in wait_panel_power_cycle()
658 /* When we disable the VDD override bit last we have to do the manual in wait_panel_power_cycle()
660 if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay) in wait_panel_power_cycle()
662 intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration); in wait_panel_power_cycle()
680 wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on, in wait_backlight_on()
681 intel_dp->pps.backlight_on_delay); in wait_backlight_on()
686 wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off, in edp_wait_backlight_off()
687 intel_dp->pps.backlight_off_delay); in edp_wait_backlight_off()
699 lockdep_assert_held(&dev_priv->display.pps.mutex); in ilk_get_pp_control()
702 if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) && in ilk_get_pp_control()
721 bool need_to_disable = !intel_dp->pps.want_panel_vdd; in intel_pps_vdd_on_unlocked()
723 lockdep_assert_held(&dev_priv->display.pps.mutex); in intel_pps_vdd_on_unlocked()
728 cancel_delayed_work(&intel_dp->pps.panel_vdd_work); in intel_pps_vdd_on_unlocked()
729 intel_dp->pps.want_panel_vdd = true; in intel_pps_vdd_on_unlocked()
734 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref); in intel_pps_vdd_on_unlocked()
735 intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv, in intel_pps_vdd_on_unlocked()
741 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s turning VDD on\n", in intel_pps_vdd_on_unlocked()
742 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_vdd_on_unlocked()
743 pps_name(dev_priv, &intel_dp->pps)); in intel_pps_vdd_on_unlocked()
753 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in intel_pps_vdd_on_unlocked()
754 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_vdd_on_unlocked()
755 pps_name(dev_priv, &intel_dp->pps), in intel_pps_vdd_on_unlocked()
762 drm_dbg_kms(&dev_priv->drm, in intel_pps_vdd_on_unlocked()
763 "[ENCODER:%d:%s] %s panel power wasn't enabled\n", in intel_pps_vdd_on_unlocked()
764 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_vdd_on_unlocked()
765 pps_name(dev_priv, &intel_dp->pps)); in intel_pps_vdd_on_unlocked()
766 msleep(intel_dp->pps.panel_power_up_delay); in intel_pps_vdd_on_unlocked()
782 bool vdd; in intel_pps_vdd_on() local
787 vdd = false; in intel_pps_vdd_on()
789 vdd = intel_pps_vdd_on_unlocked(intel_dp); in intel_pps_vdd_on()
790 I915_STATE_WARN(i915, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n", in intel_pps_vdd_on()
791 dp_to_dig_port(intel_dp)->base.base.base.id, in intel_pps_vdd_on()
792 dp_to_dig_port(intel_dp)->base.base.name, in intel_pps_vdd_on()
793 pps_name(i915, &intel_dp->pps)); in intel_pps_vdd_on()
804 lockdep_assert_held(&dev_priv->display.pps.mutex); in intel_pps_vdd_off_sync_unlocked()
806 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd); in intel_pps_vdd_off_sync_unlocked()
811 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s turning VDD off\n", in intel_pps_vdd_off_sync_unlocked()
812 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_vdd_off_sync_unlocked()
813 pps_name(dev_priv, &intel_dp->pps)); in intel_pps_vdd_off_sync_unlocked()
825 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", in intel_pps_vdd_off_sync_unlocked()
826 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_vdd_off_sync_unlocked()
827 pps_name(dev_priv, &intel_dp->pps), in intel_pps_vdd_off_sync_unlocked()
832 intel_dp->pps.panel_power_off_time = ktime_get_boottime(); in intel_pps_vdd_off_sync_unlocked()
836 fetch_and_zero(&intel_dp->pps.vdd_wakeref)); in intel_pps_vdd_off_sync_unlocked()
846 cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work); in intel_pps_vdd_off_sync()
848 * vdd might still be enabled due to the delayed vdd off. in intel_pps_vdd_off_sync()
849 * Make sure vdd is actually turned off here. in intel_pps_vdd_off_sync()
863 if (!intel_dp->pps.want_panel_vdd) in edp_panel_vdd_work()
875 * so keep VDD enabled until we're done with init. in edp_panel_vdd_schedule_off()
877 if (intel_dp->pps.initializing) in edp_panel_vdd_schedule_off()
885 delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5); in edp_panel_vdd_schedule_off()
886 queue_delayed_work(i915->unordered_wq, in edp_panel_vdd_schedule_off()
887 &intel_dp->pps.panel_vdd_work, delay); in edp_panel_vdd_schedule_off()
899 lockdep_assert_held(&dev_priv->display.pps.mutex); in intel_pps_vdd_off_unlocked()
904 I915_STATE_WARN(dev_priv, !intel_dp->pps.want_panel_vdd, in intel_pps_vdd_off_unlocked()
905 "[ENCODER:%d:%s] %s VDD not forced on", in intel_pps_vdd_off_unlocked()
906 dp_to_dig_port(intel_dp)->base.base.base.id, in intel_pps_vdd_off_unlocked()
907 dp_to_dig_port(intel_dp)->base.base.name, in intel_pps_vdd_off_unlocked()
908 pps_name(dev_priv, &intel_dp->pps)); in intel_pps_vdd_off_unlocked()
910 intel_dp->pps.want_panel_vdd = false; in intel_pps_vdd_off_unlocked()
924 lockdep_assert_held(&dev_priv->display.pps.mutex); in intel_pps_on_unlocked()
929 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s turn panel power on\n", in intel_pps_on_unlocked()
930 dp_to_dig_port(intel_dp)->base.base.base.id, in intel_pps_on_unlocked()
931 dp_to_dig_port(intel_dp)->base.base.name, in intel_pps_on_unlocked()
932 pps_name(dev_priv, &intel_dp->pps)); in intel_pps_on_unlocked()
934 if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp), in intel_pps_on_unlocked()
935 "[ENCODER:%d:%s] %s panel power already on\n", in intel_pps_on_unlocked()
936 dp_to_dig_port(intel_dp)->base.base.base.id, in intel_pps_on_unlocked()
937 dp_to_dig_port(intel_dp)->base.base.name, in intel_pps_on_unlocked()
938 pps_name(dev_priv, &intel_dp->pps))) in intel_pps_on_unlocked()
960 intel_dp->pps.last_power_on = jiffies; in intel_pps_on_unlocked()
987 lockdep_assert_held(&dev_priv->display.pps.mutex); in intel_pps_off_unlocked()
992 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s turn panel power off\n", in intel_pps_off_unlocked()
993 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_off_unlocked()
994 pps_name(dev_priv, &intel_dp->pps)); in intel_pps_off_unlocked()
996 drm_WARN(&dev_priv->drm, !intel_dp->pps.want_panel_vdd, in intel_pps_off_unlocked()
997 "[ENCODER:%d:%s] %s need VDD to turn off panel\n", in intel_pps_off_unlocked()
998 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_off_unlocked()
999 pps_name(dev_priv, &intel_dp->pps)); in intel_pps_off_unlocked()
1002 /* We need to switch off panel power _and_ force vdd, for otherwise some in intel_pps_off_unlocked()
1009 intel_dp->pps.want_panel_vdd = false; in intel_pps_off_unlocked()
1015 intel_dp->pps.panel_power_off_time = ktime_get_boottime(); in intel_pps_off_unlocked()
1017 /* We got a reference when we enabled the VDD. */ in intel_pps_off_unlocked()
1020 fetch_and_zero(&intel_dp->pps.vdd_wakeref)); in intel_pps_off_unlocked()
1080 intel_dp->pps.last_backlight_off = jiffies; in intel_pps_backlight_off()
1090 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_pps_backlight_power()
1101 drm_dbg_kms(&i915->drm, "panel power control backlight %s\n", in intel_pps_backlight_power()
1113 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in vlv_detach_power_sequencer()
1114 enum pipe pipe = intel_dp->pps.pps_pipe; in vlv_detach_power_sequencer()
1117 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE); in vlv_detach_power_sequencer()
1119 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
1126 * have the same port selected (even if only one has power/vdd in vlv_detach_power_sequencer()
1129 * selected in multiple power sequencers, but let's clear the in vlv_detach_power_sequencer()
1133 drm_dbg_kms(&dev_priv->drm, in vlv_detach_power_sequencer()
1134 "detaching %s from [ENCODER:%d:%s]\n", in vlv_detach_power_sequencer()
1135 pps_name(dev_priv, &intel_dp->pps), in vlv_detach_power_sequencer()
1136 dig_port->base.base.base.id, dig_port->base.base.name); in vlv_detach_power_sequencer()
1140 intel_dp->pps.pps_pipe = INVALID_PIPE; in vlv_detach_power_sequencer()
1148 lockdep_assert_held(&dev_priv->display.pps.mutex); in vlv_steal_power_sequencer()
1150 for_each_intel_dp(&dev_priv->drm, encoder) { in vlv_steal_power_sequencer()
1153 drm_WARN(&dev_priv->drm, intel_dp->pps.active_pipe == pipe, in vlv_steal_power_sequencer()
1154 "stealing PPS %c from active [ENCODER:%d:%s]\n", in vlv_steal_power_sequencer()
1155 pipe_name(pipe), encoder->base.base.id, in vlv_steal_power_sequencer()
1156 encoder->base.name); in vlv_steal_power_sequencer()
1158 if (intel_dp->pps.pps_pipe != pipe) in vlv_steal_power_sequencer()
1161 drm_dbg_kms(&dev_priv->drm, in vlv_steal_power_sequencer()
1162 "stealing PPS %c from [ENCODER:%d:%s]\n", in vlv_steal_power_sequencer()
1163 pipe_name(pipe), encoder->base.base.id, in vlv_steal_power_sequencer()
1164 encoder->base.name); in vlv_steal_power_sequencer()
1166 /* make sure vdd is off before we steal it */ in vlv_steal_power_sequencer()
1174 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_pps_init()
1176 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_pps_init()
1178 lockdep_assert_held(&dev_priv->display.pps.mutex); in vlv_pps_init()
1180 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE); in vlv_pps_init()
1182 if (intel_dp->pps.pps_pipe != INVALID_PIPE && in vlv_pps_init()
1183 intel_dp->pps.pps_pipe != crtc->pipe) { in vlv_pps_init()
1186 * port previously make sure to turn off vdd there while in vlv_pps_init()
1196 vlv_steal_power_sequencer(dev_priv, crtc->pipe); in vlv_pps_init()
1198 intel_dp->pps.active_pipe = crtc->pipe; in vlv_pps_init()
1203 /* now it's all ours */ in vlv_pps_init()
1204 intel_dp->pps.pps_pipe = crtc->pipe; in vlv_pps_init()
1206 drm_dbg_kms(&dev_priv->drm, in vlv_pps_init()
1207 "initializing %s for [ENCODER:%d:%s]\n", in vlv_pps_init()
1208 pps_name(dev_priv, &intel_dp->pps), in vlv_pps_init()
1209 encoder->base.base.id, encoder->base.name); in vlv_pps_init()
1221 lockdep_assert_held(&dev_priv->display.pps.mutex); in pps_vdd_init()
1227 * The VDD bit needs a power domain reference, so if the bit is in pps_vdd_init()
1229 * schedule a vdd off, so we don't hold on to the reference in pps_vdd_init()
1232 drm_dbg_kms(&dev_priv->drm, in pps_vdd_init()
1233 "[ENCODER:%d:%s] %s VDD left on by BIOS, adjusting state tracking\n", in pps_vdd_init()
1234 dig_port->base.base.base.id, dig_port->base.base.name, in pps_vdd_init()
1235 pps_name(dev_priv, &intel_dp->pps)); in pps_vdd_init()
1236 drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref); in pps_vdd_init()
1237 intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv, in pps_vdd_init()
1262 intel_dp->pps.panel_power_off_time = 0; in pps_init_timestamps()
1263 intel_dp->pps.last_power_on = jiffies; in pps_init_timestamps()
1264 intel_dp->pps.last_backlight_off = jiffies; in pps_init_timestamps()
1286 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
1287 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
1288 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1289 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1296 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; in intel_pps_readout_hw_state()
1298 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000; in intel_pps_readout_hw_state()
1308 drm_dbg_kms(&i915->drm, "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", in intel_pps_dump_state()
1310 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); in intel_pps_dump_state()
1318 struct edp_power_seq *sw = &intel_dp->pps.pps_delays; in intel_pps_verify_state()
1322 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || in intel_pps_verify_state()
1323 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { in intel_pps_verify_state()
1324 drm_err(&i915->drm, "PPS state mismatch\n"); in intel_pps_verify_state()
1332 return delays->t1_t3 || delays->t8 || delays->t9 || in pps_delays_valid()
1333 delays->t10 || delays->t11_t12; in pps_delays_valid()
1341 lockdep_assert_held(&dev_priv->display.pps.mutex); in pps_init_delays_bios()
1343 if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays)) in pps_init_delays_bios()
1344 intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays); in pps_init_delays_bios()
1346 *bios = intel_dp->pps.bios_pps_delays; in pps_init_delays_bios()
1355 struct intel_connector *connector = intel_dp->attached_connector; in pps_init_delays_vbt()
1357 *vbt = connector->panel.vbt.edp.pps; in pps_init_delays_vbt()
1362 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay in pps_init_delays_vbt()
1368 vbt->t11_t12 = max_t(u16, vbt->t11_t12, 1300 * 10); in pps_init_delays_vbt()
1369 drm_dbg_kms(&dev_priv->drm, in pps_init_delays_vbt()
1371 vbt->t11_t12); in pps_init_delays_vbt()
1378 vbt->t11_t12 += 100 * 10; in pps_init_delays_vbt()
1388 lockdep_assert_held(&dev_priv->display.pps.mutex); in pps_init_delays_spec()
1392 spec->t1_t3 = 210 * 10; in pps_init_delays_spec()
1393 spec->t8 = 50 * 10; /* no limit for t8, use t7 instead */ in pps_init_delays_spec()
1394 spec->t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ in pps_init_delays_spec()
1395 spec->t10 = 500 * 10; in pps_init_delays_spec()
1400 spec->t11_t12 = (510 + 100) * 10; in pps_init_delays_spec()
1409 *final = &intel_dp->pps.pps_delays; in pps_init_delays()
1411 lockdep_assert_held(&dev_priv->display.pps.mutex); in pps_init_delays()
1423 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ in pps_init_delays()
1433 #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) in pps_init_delays()
1434 intel_dp->pps.panel_power_up_delay = get_delay(t1_t3); in pps_init_delays()
1435 intel_dp->pps.backlight_on_delay = get_delay(t8); in pps_init_delays()
1436 intel_dp->pps.backlight_off_delay = get_delay(t9); in pps_init_delays()
1437 intel_dp->pps.panel_power_down_delay = get_delay(t10); in pps_init_delays()
1438 intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12); in pps_init_delays()
1441 drm_dbg_kms(&dev_priv->drm, in pps_init_delays()
1443 intel_dp->pps.panel_power_up_delay, in pps_init_delays()
1444 intel_dp->pps.panel_power_down_delay, in pps_init_delays()
1445 intel_dp->pps.panel_power_cycle_delay); in pps_init_delays()
1447 drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n", in pps_init_delays()
1448 intel_dp->pps.backlight_on_delay, in pps_init_delays()
1449 intel_dp->pps.backlight_off_delay); in pps_init_delays()
1458 final->t8 = 1; in pps_init_delays()
1459 final->t9 = 1; in pps_init_delays()
1465 final->t11_t12 = roundup(final->t11_t12, 100 * 10); in pps_init_delays()
1472 int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000; in pps_init_registers()
1474 enum port port = dp_to_dig_port(intel_dp)->base.port; in pps_init_registers()
1475 const struct edp_power_seq *seq = &intel_dp->pps.pps_delays; in pps_init_registers()
1477 lockdep_assert_held(&dev_priv->display.pps.mutex); in pps_init_registers()
1482 * On some VLV machines the BIOS can leave the VDD in pps_init_registers()
1487 * intel_pps_vdd_on_unlocked() would notice that the VDD was in pps_init_registers()
1489 * domain reference. Disable VDD first to avoid this. in pps_init_registers()
1490 * This also avoids spuriously turning the VDD on as in pps_init_registers()
1496 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON, in pps_init_registers()
1500 drm_dbg_kms(&dev_priv->drm, in pps_init_registers()
1501 "VDD already on, disabling first\n"); in pps_init_registers()
1508 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | in pps_init_registers()
1509 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); in pps_init_registers()
1510 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | in pps_init_registers()
1511 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); in pps_init_registers()
1544 …P_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_… in pps_init_registers()
1548 DIV_ROUND_UP(seq->t11_t12, 1000))); in pps_init_registers()
1550 drm_dbg_kms(&dev_priv->drm, in pps_init_registers()
1589 intel_dp->pps.initializing = true; in intel_pps_init()
1590 INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work); in intel_pps_init()
1608 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in pps_init_late()
1609 struct intel_connector *connector = intel_dp->attached_connector; in pps_init_late()
1617 drm_WARN(&i915->drm, connector->panel.vbt.backlight.controller >= 0 && in pps_init_late()
1618 intel_dp->pps.pps_idx != connector->panel.vbt.backlight.controller, in pps_init_late()
1619 "[ENCODER:%d:%s] power sequencer mismatch: %d (initial) vs. %d (VBT)\n", in pps_init_late()
1620 encoder->base.base.id, encoder->base.name, in pps_init_late()
1621 intel_dp->pps.pps_idx, connector->panel.vbt.backlight.controller); in pps_init_late()
1623 if (connector->panel.vbt.backlight.controller >= 0) in pps_init_late()
1624 intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller; in pps_init_late()
1632 /* Reinit delays after per-panel info has been parsed from VBT */ in intel_pps_init_late()
1635 memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays)); in intel_pps_init_late()
1639 intel_dp->pps.initializing = false; in intel_pps_init_late()
1667 i915->display.pps.mmio_base = PCH_PPS_BASE; in intel_pps_setup()
1669 i915->display.pps.mmio_base = VLV_PPS_BASE; in intel_pps_setup()
1671 i915->display.pps.mmio_base = PPS_BASE; in intel_pps_setup()
1681 if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv))) in assert_pps_unlocked()
1717 drm_WARN_ON(&dev_priv->drm, in assert_pps_unlocked()