Lines Matching +full:e +full:- +full:ddc
3 * Copyright © 2006-2009 Intel Corporation
64 return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev); in intel_hdmi_to_i915()
75 drm_WARN(&dev_priv->drm, in assert_hdmi_port_disabled()
76 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
84 drm_WARN(&dev_priv->drm, in assert_hdmi_transcoder_func_disabled()
206 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_write_infoframe()
210 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), in g4x_write_infoframe()
241 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_read_infoframe()
255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_infoframes_enabled()
261 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) in g4x_infoframes_enabled()
274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in ibx_write_infoframe()
275 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_write_infoframe()
276 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in ibx_write_infoframe()
280 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), in ibx_write_infoframe()
291 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), in ibx_write_infoframe()
297 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); in ibx_write_infoframe()
312 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in ibx_read_infoframe()
313 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_read_infoframe()
317 intel_de_rmw(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), in ibx_read_infoframe()
321 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); in ibx_read_infoframe()
327 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in ibx_infoframes_enabled()
328 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in ibx_infoframes_enabled()
335 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) in ibx_infoframes_enabled()
349 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in cpt_write_infoframe()
350 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_write_infoframe()
351 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in cpt_write_infoframe()
355 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), in cpt_write_infoframe()
369 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), in cpt_write_infoframe()
375 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); in cpt_write_infoframe()
390 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in cpt_read_infoframe()
391 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_read_infoframe()
395 intel_de_rmw(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), in cpt_read_infoframe()
399 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); in cpt_read_infoframe()
405 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in cpt_infoframes_enabled()
406 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in cpt_infoframes_enabled()
423 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_write_infoframe()
424 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_write_infoframe()
425 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); in vlv_write_infoframe()
429 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), in vlv_write_infoframe()
441 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); in vlv_write_infoframe()
447 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); in vlv_write_infoframe()
462 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_read_infoframe()
463 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_read_infoframe()
467 intel_de_rmw(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), in vlv_read_infoframe()
472 VLV_TVIDEO_DIP_DATA(crtc->pipe)); in vlv_read_infoframe()
478 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_infoframes_enabled()
479 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in vlv_infoframes_enabled()
485 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) in vlv_infoframes_enabled()
499 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_write_infoframe()
500 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in hsw_write_infoframe()
508 drm_WARN_ON(&dev_priv->drm, len > data_size); in hsw_write_infoframe()
526 if (IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && type == DP_SDP_VSC) in hsw_write_infoframe()
538 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_read_infoframe()
539 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in hsw_read_infoframe()
551 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_infoframes_enabled()
553 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); in hsw_infoframes_enabled()
591 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_infoframes_enabled()
596 val = dig_port->infoframes_enabled(encoder, crtc_state); in intel_hdmi_infoframes_enabled()
640 if ((crtc_state->infoframes.enable & in intel_write_infoframe()
644 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) in intel_write_infoframe()
648 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); in intel_write_infoframe()
649 if (drm_WARN_ON(encoder->base.dev, len < 0)) in intel_write_infoframe()
657 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); in intel_write_infoframe()
669 if ((crtc_state->infoframes.enable & in intel_read_infoframe()
673 dig_port->read_infoframe(encoder, crtc_state, in intel_read_infoframe()
680 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); in intel_read_infoframe()
682 drm_dbg_kms(encoder->base.dev, in intel_read_infoframe()
687 if (frame->any.type != type) in intel_read_infoframe()
688 drm_dbg_kms(encoder->base.dev, in intel_read_infoframe()
690 frame->any.type, type); in intel_read_infoframe()
698 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; in intel_hdmi_compute_avi_infoframe()
700 &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_avi_infoframe()
701 struct drm_connector *connector = conn_state->connector; in intel_hdmi_compute_avi_infoframe()
704 if (!crtc_state->has_infoframe) in intel_hdmi_compute_avi_infoframe()
707 crtc_state->infoframes.enable |= in intel_hdmi_compute_avi_infoframe()
715 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) in intel_hdmi_compute_avi_infoframe()
716 frame->colorspace = HDMI_COLORSPACE_YUV420; in intel_hdmi_compute_avi_infoframe()
717 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) in intel_hdmi_compute_avi_infoframe()
718 frame->colorspace = HDMI_COLORSPACE_YUV444; in intel_hdmi_compute_avi_infoframe()
720 frame->colorspace = HDMI_COLORSPACE_RGB; in intel_hdmi_compute_avi_infoframe()
725 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && in intel_hdmi_compute_avi_infoframe()
726 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); in intel_hdmi_compute_avi_infoframe()
728 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { in intel_hdmi_compute_avi_infoframe()
731 crtc_state->limited_color_range ? in intel_hdmi_compute_avi_infoframe()
735 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; in intel_hdmi_compute_avi_infoframe()
736 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; in intel_hdmi_compute_avi_infoframe()
744 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_avi_infoframe()
755 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_hdmi_compute_spd_infoframe()
756 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; in intel_hdmi_compute_spd_infoframe()
759 if (!crtc_state->has_infoframe) in intel_hdmi_compute_spd_infoframe()
762 crtc_state->infoframes.enable |= in intel_hdmi_compute_spd_infoframe()
770 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_spd_infoframe()
773 frame->sdi = HDMI_SPD_SDI_PC; in intel_hdmi_compute_spd_infoframe()
776 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_spd_infoframe()
788 &crtc_state->infoframes.hdmi.vendor.hdmi; in intel_hdmi_compute_hdmi_infoframe()
790 &conn_state->connector->display_info; in intel_hdmi_compute_hdmi_infoframe()
793 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) in intel_hdmi_compute_hdmi_infoframe()
796 crtc_state->infoframes.enable |= in intel_hdmi_compute_hdmi_infoframe()
800 conn_state->connector, in intel_hdmi_compute_hdmi_infoframe()
801 &crtc_state->hw.adjusted_mode); in intel_hdmi_compute_hdmi_infoframe()
802 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_hdmi_infoframe()
806 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_hdmi_infoframe()
817 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; in intel_hdmi_compute_drm_infoframe()
818 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_compute_drm_infoframe()
824 if (!crtc_state->has_infoframe) in intel_hdmi_compute_drm_infoframe()
827 if (!conn_state->hdr_output_metadata) in intel_hdmi_compute_drm_infoframe()
830 crtc_state->infoframes.enable |= in intel_hdmi_compute_drm_infoframe()
835 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_compute_drm_infoframe()
841 if (drm_WARN_ON(&dev_priv->drm, ret)) in intel_hdmi_compute_drm_infoframe()
852 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_set_infoframes()
854 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in g4x_set_infoframes()
857 u32 port = VIDEO_DIP_PORT(encoder->port); in g4x_set_infoframes()
876 drm_dbg_kms(&dev_priv->drm, in g4x_set_infoframes()
890 drm_dbg_kms(&dev_priv->drm, in g4x_set_infoframes()
908 &crtc_state->infoframes.avi); in g4x_set_infoframes()
911 &crtc_state->infoframes.spd); in g4x_set_infoframes()
914 &crtc_state->infoframes.hdmi); in g4x_set_infoframes()
921 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
922 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
923 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
924 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
950 return mode->crtc_hdisplay % pixels_per_group == 0 && in gcp_default_phase_possible()
951 mode->crtc_htotal % pixels_per_group == 0 && in gcp_default_phase_possible()
952 mode->crtc_hblank_start % pixels_per_group == 0 && in gcp_default_phase_possible()
953 mode->crtc_hblank_end % pixels_per_group == 0 && in gcp_default_phase_possible()
954 mode->crtc_hsync_start % pixels_per_group == 0 && in gcp_default_phase_possible()
955 mode->crtc_hsync_end % pixels_per_group == 0 && in gcp_default_phase_possible()
956 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || in gcp_default_phase_possible()
957 mode->crtc_htotal/2 % pixels_per_group == 0); in gcp_default_phase_possible()
964 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_set_gcp_infoframe()
965 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_hdmi_set_gcp_infoframe()
968 if ((crtc_state->infoframes.enable & in intel_hdmi_set_gcp_infoframe()
973 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); in intel_hdmi_set_gcp_infoframe()
975 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_set_gcp_infoframe()
977 reg = TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_set_gcp_infoframe()
981 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); in intel_hdmi_set_gcp_infoframe()
989 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_read_gcp_infoframe()
990 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_hdmi_read_gcp_infoframe()
993 if ((crtc_state->infoframes.enable & in intel_hdmi_read_gcp_infoframe()
998 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); in intel_hdmi_read_gcp_infoframe()
1000 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_read_gcp_infoframe()
1002 reg = TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_read_gcp_infoframe()
1006 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); in intel_hdmi_read_gcp_infoframe()
1013 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_compute_gcp_infoframe()
1015 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) in intel_hdmi_compute_gcp_infoframe()
1018 crtc_state->infoframes.enable |= in intel_hdmi_compute_gcp_infoframe()
1022 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
1023 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; in intel_hdmi_compute_gcp_infoframe()
1026 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_compute_gcp_infoframe()
1027 &crtc_state->hw.adjusted_mode)) in intel_hdmi_compute_gcp_infoframe()
1028 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; in intel_hdmi_compute_gcp_infoframe()
1036 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in ibx_set_infoframes()
1037 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_set_infoframes()
1039 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in ibx_set_infoframes()
1040 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in ibx_set_infoframes()
1042 u32 port = VIDEO_DIP_PORT(encoder->port); in ibx_set_infoframes()
1061 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, in ibx_set_infoframes()
1081 &crtc_state->infoframes.avi); in ibx_set_infoframes()
1084 &crtc_state->infoframes.spd); in ibx_set_infoframes()
1087 &crtc_state->infoframes.hdmi); in ibx_set_infoframes()
1095 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in cpt_set_infoframes()
1096 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_set_infoframes()
1098 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in cpt_set_infoframes()
1130 &crtc_state->infoframes.avi); in cpt_set_infoframes()
1133 &crtc_state->infoframes.spd); in cpt_set_infoframes()
1136 &crtc_state->infoframes.hdmi); in cpt_set_infoframes()
1144 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_set_infoframes()
1145 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_set_infoframes()
1147 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); in vlv_set_infoframes()
1149 u32 port = VIDEO_DIP_PORT(encoder->port); in vlv_set_infoframes()
1168 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, in vlv_set_infoframes()
1188 &crtc_state->infoframes.avi); in vlv_set_infoframes()
1191 &crtc_state->infoframes.spd); in vlv_set_infoframes()
1194 &crtc_state->infoframes.hdmi); in vlv_set_infoframes()
1202 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_set_infoframes()
1203 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); in hsw_set_infoframes()
1207 crtc_state->cpu_transcoder); in hsw_set_infoframes()
1228 &crtc_state->infoframes.avi); in hsw_set_infoframes()
1231 &crtc_state->infoframes.spd); in hsw_set_infoframes()
1234 &crtc_state->infoframes.hdmi); in hsw_set_infoframes()
1237 &crtc_state->infoframes.drm); in hsw_set_infoframes()
1243 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; in intel_dp_dual_mode_set_tmds_output() local
1245 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) in intel_dp_dual_mode_set_tmds_output()
1248 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n", in intel_dp_dual_mode_set_tmds_output()
1251 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, in intel_dp_dual_mode_set_tmds_output()
1252 hdmi->dp_dual_mode.type, ddc, enable); in intel_dp_dual_mode_set_tmds_output()
1258 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp_read()
1259 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; in intel_hdmi_hdcp_read() local
1276 ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs)); in intel_hdmi_hdcp_read()
1279 return ret >= 0 ? -EIO : ret; in intel_hdmi_hdcp_read()
1285 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp_write()
1286 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; in intel_hdmi_hdcp_write() local
1293 return -ENOMEM; in intel_hdmi_hdcp_write()
1303 ret = i2c_transfer(ddc, &msg, 1); in intel_hdmi_hdcp_write()
1307 ret = -EIO; in intel_hdmi_hdcp_write()
1317 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_write_an_aksv()
1318 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp_write_an_aksv()
1319 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; in intel_hdmi_hdcp_write_an_aksv() local
1325 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n", in intel_hdmi_hdcp_write_an_aksv()
1330 ret = intel_gmbus_output_aksv(ddc); in intel_hdmi_hdcp_write_an_aksv()
1332 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret); in intel_hdmi_hdcp_write_an_aksv()
1341 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_read_bksv()
1347 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n", in intel_hdmi_hdcp_read_bksv()
1356 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_read_bstatus()
1362 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n", in intel_hdmi_hdcp_read_bstatus()
1371 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_repeater_present()
1377 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", in intel_hdmi_hdcp_repeater_present()
1389 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_read_ri_prime()
1395 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n", in intel_hdmi_hdcp_read_ri_prime()
1404 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_read_ksv_ready()
1410 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", in intel_hdmi_hdcp_read_ksv_ready()
1422 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_read_ksv_fifo()
1427 drm_dbg_kms(&i915->drm, in intel_hdmi_hdcp_read_ksv_fifo()
1428 "Read ksv fifo over DDC failed (%d)\n", ret); in intel_hdmi_hdcp_read_ksv_fifo()
1438 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_read_v_prime_part()
1442 return -EINVAL; in intel_hdmi_hdcp_read_v_prime_part()
1447 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n", in intel_hdmi_hdcp_read_v_prime_part()
1455 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); in kbl_repositioning_enc_en_signal()
1457 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); in kbl_repositioning_enc_en_signal()
1462 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe)); in kbl_repositioning_enc_en_signal()
1468 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, in kbl_repositioning_enc_en_signal()
1471 drm_err(&dev_priv->drm, in kbl_repositioning_enc_en_signal()
1476 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, in kbl_repositioning_enc_en_signal()
1479 drm_err(&dev_priv->drm, in kbl_repositioning_enc_en_signal()
1492 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp_toggle_signalling()
1493 struct intel_connector *connector = hdmi->attached_connector; in intel_hdmi_hdcp_toggle_signalling()
1494 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); in intel_hdmi_hdcp_toggle_signalling()
1500 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, in intel_hdmi_hdcp_toggle_signalling()
1504 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n", in intel_hdmi_hdcp_toggle_signalling()
1524 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_check_link_once()
1525 enum port port = dig_port->base.port; in intel_hdmi_hdcp_check_link_once()
1526 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; in intel_hdmi_hdcp_check_link_once()
1543 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n", in intel_hdmi_hdcp_check_link_once()
1555 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_check_link()
1562 drm_err(&i915->drm, "Link check failed\n"); in intel_hdmi_hdcp_check_link()
1605 return -EINVAL; in get_hdcp2_msg_timeout()
1613 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in hdcp2_detect_msg_availability()
1619 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n", in hdcp2_detect_msg_availability()
1640 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp2_wait_for_msg()
1655 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n", in intel_hdmi_hdcp2_wait_for_msg()
1677 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp2_read_msg()
1678 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp2_read_msg()
1679 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; in intel_hdmi_hdcp2_read_msg()
1684 hdcp->is_paired); in intel_hdmi_hdcp2_read_msg()
1693 drm_dbg_kms(&i915->drm, in intel_hdmi_hdcp2_read_msg()
1696 return -EINVAL; in intel_hdmi_hdcp2_read_msg()
1702 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n", in intel_hdmi_hdcp2_read_msg()
1720 * Re-auth request and Link Integrity Failures are represented by in intel_hdmi_hdcp2_check_link()
1721 * same bit. i.e reauth_req. in intel_hdmi_hdcp2_check_link()
1768 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_source_max_tmds_clock()
1780 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata); in intel_hdmi_source_max_tmds_clock()
1790 struct intel_connector *connector = hdmi->attached_connector; in intel_has_hdmi_sink()
1792 return connector->base.display_info.is_hdmi && in intel_has_hdmi_sink()
1793 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; in intel_has_hdmi_sink()
1798 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; in intel_hdmi_is_ycbcr420()
1805 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; in hdmi_port_clock_limit()
1809 struct intel_connector *connector = hdmi->attached_connector; in hdmi_port_clock_limit()
1810 const struct drm_display_info *info = &connector->base.display_info; in hdmi_port_clock_limit()
1812 if (hdmi->dp_dual_mode.max_tmds_clock) in hdmi_port_clock_limit()
1814 hdmi->dp_dual_mode.max_tmds_clock); in hdmi_port_clock_limit()
1816 if (info->max_tmds_clock) in hdmi_port_clock_limit()
1818 info->max_tmds_clock); in hdmi_port_clock_limit()
1832 enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port); in hdmi_port_clock_valid()
1840 /* GLK DPLL can't generate 446-480 MHz */ in hdmi_port_clock_valid()
1844 /* BXT/GLK DPLL can't generate 223-240 MHz */ in hdmi_port_clock_valid()
1849 /* CHV DPLL can't generate 216-240 MHz */ in hdmi_port_clock_valid()
1853 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ in hdmi_port_clock_valid()
1857 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ in hdmi_port_clock_valid()
1862 * SNPS PHYs' MPLLB table-based programming can only handle a fixed in hdmi_port_clock_valid()
1910 const struct drm_display_info *info = &connector->display_info; in intel_hdmi_sink_bpc_possible()
1911 const struct drm_hdmi_info *hdmi = &info->hdmi; in intel_hdmi_sink_bpc_possible()
1919 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; in intel_hdmi_sink_bpc_possible()
1921 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; in intel_hdmi_sink_bpc_possible()
1927 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; in intel_hdmi_sink_bpc_possible()
1929 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; in intel_hdmi_sink_bpc_possible()
1943 struct drm_i915_private *i915 = to_i915(connector->dev); in intel_hdmi_mode_clock_valid()
1953 for (bpc = 12; bpc >= 8; bpc -= 2) { in intel_hdmi_mode_clock_valid()
1968 drm_WARN_ON(&i915->drm, status == MODE_OK); in intel_hdmi_mode_clock_valid()
1980 int clock = mode->clock; in intel_hdmi_mode_valid()
1981 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; in intel_hdmi_mode_valid()
1982 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); in intel_hdmi_mode_valid()
1990 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) in intel_hdmi_mode_valid()
1996 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { in intel_hdmi_mode_valid()
2011 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); in intel_hdmi_mode_valid()
2021 !connector->ycbcr_420_allowed || in intel_hdmi_mode_valid()
2022 !drm_mode_is_420_also(&connector->display_info, mode)) in intel_hdmi_mode_valid()
2037 struct drm_atomic_state *state = crtc_state->uapi.state; in intel_hdmi_bpc_possible()
2043 if (connector_state->crtc != crtc_state->uapi.crtc) in intel_hdmi_bpc_possible()
2047 crtc_state->sink_format)) in intel_hdmi_bpc_possible()
2057 to_i915(crtc_state->uapi.crtc->dev); in hdmi_bpc_possible()
2059 &crtc_state->hw.adjusted_mode; in hdmi_bpc_possible()
2067 (adjusted_mode->crtc_hblank_end - in hdmi_bpc_possible()
2068 adjusted_mode->crtc_hblank_start) % 8 == 2) in hdmi_bpc_possible()
2071 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink); in hdmi_bpc_possible()
2085 bpc = max(crtc_state->pipe_bpp / 3, 8); in intel_hdmi_compute_bpc()
2095 for (; bpc >= 8; bpc -= 2) { in intel_hdmi_compute_bpc()
2097 crtc_state->sink_format); in intel_hdmi_compute_bpc()
2102 crtc_state->has_hdmi_sink) == MODE_OK) in intel_hdmi_compute_bpc()
2106 return -EINVAL; in intel_hdmi_compute_bpc()
2113 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_hdmi_compute_clock()
2115 &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_clock()
2116 int bpc, clock = adjusted_mode->crtc_clock; in intel_hdmi_compute_clock()
2118 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) in intel_hdmi_compute_clock()
2126 crtc_state->port_clock = in intel_hdmi_compute_clock()
2127 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format); in intel_hdmi_compute_clock()
2134 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); in intel_hdmi_compute_clock()
2136 drm_dbg_kms(&i915->drm, in intel_hdmi_compute_clock()
2138 bpc, crtc_state->pipe_bpp); in intel_hdmi_compute_clock()
2149 &crtc_state->hw.adjusted_mode; in intel_hdmi_limited_color_range()
2153 * crtc_state->limited_color_range only applies to RGB, in intel_hdmi_limited_color_range()
2158 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) in intel_hdmi_limited_color_range()
2161 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { in intel_hdmi_limited_color_range()
2162 /* See CEA-861-E - 5.1 Default Encoding Parameters */ in intel_hdmi_limited_color_range()
2163 return crtc_state->has_hdmi_sink && in intel_hdmi_limited_color_range()
2167 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; in intel_hdmi_limited_color_range()
2175 struct drm_connector *connector = conn_state->connector; in intel_hdmi_has_audio()
2179 if (!crtc_state->has_hdmi_sink) in intel_hdmi_has_audio()
2182 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) in intel_hdmi_has_audio()
2183 return connector->display_info.has_audio; in intel_hdmi_has_audio()
2185 return intel_conn_state->force_audio == HDMI_AUDIO_ON; in intel_hdmi_has_audio()
2193 if (!crtc_state->has_hdmi_sink) in intel_hdmi_sink_format()
2196 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) in intel_hdmi_sink_format()
2205 return crtc_state->sink_format; in intel_hdmi_output_format()
2213 struct intel_connector *connector = to_intel_connector(conn_state->connector); in intel_hdmi_compute_output_format()
2214 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_output_format()
2215 const struct drm_display_info *info = &connector->base.display_info; in intel_hdmi_compute_output_format()
2216 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_hdmi_compute_output_format()
2220 crtc_state->sink_format = in intel_hdmi_compute_output_format()
2223 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) { in intel_hdmi_compute_output_format()
2224 drm_dbg_kms(&i915->drm, in intel_hdmi_compute_output_format()
2226 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; in intel_hdmi_compute_output_format()
2229 crtc_state->output_format = intel_hdmi_output_format(crtc_state); in intel_hdmi_compute_output_format()
2232 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || in intel_hdmi_compute_output_format()
2233 !crtc_state->has_hdmi_sink || in intel_hdmi_compute_output_format()
2234 !connector->base.ycbcr_420_allowed || in intel_hdmi_compute_output_format()
2238 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; in intel_hdmi_compute_output_format()
2239 crtc_state->output_format = intel_hdmi_output_format(crtc_state); in intel_hdmi_compute_output_format()
2248 return crtc_state->uapi.encoder_mask && in intel_hdmi_is_cloned()
2249 !is_power_of_2(crtc_state->uapi.encoder_mask); in intel_hdmi_is_cloned()
2285 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_compute_config()
2286 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_hdmi_compute_config()
2287 struct drm_connector *connector = conn_state->connector; in intel_hdmi_compute_config()
2288 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; in intel_hdmi_compute_config()
2291 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_hdmi_compute_config()
2292 return -EINVAL; in intel_hdmi_compute_config()
2294 if (!connector->interlace_allowed && in intel_hdmi_compute_config()
2295 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) in intel_hdmi_compute_config()
2296 return -EINVAL; in intel_hdmi_compute_config()
2298 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_hdmi_compute_config()
2300 if (pipe_config->has_hdmi_sink) in intel_hdmi_compute_config()
2301 pipe_config->has_infoframe = true; in intel_hdmi_compute_config()
2303 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) in intel_hdmi_compute_config()
2304 pipe_config->pixel_multiplier = 2; in intel_hdmi_compute_config()
2306 pipe_config->has_audio = in intel_hdmi_compute_config()
2318 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_compute_config()
2320 pipe_config->hw.adjusted_mode.crtc_clock); in intel_hdmi_compute_config()
2330 pipe_config->limited_color_range = in intel_hdmi_compute_config()
2333 if (conn_state->picture_aspect_ratio) in intel_hdmi_compute_config()
2334 adjusted_mode->picture_aspect_ratio = in intel_hdmi_compute_config()
2335 conn_state->picture_aspect_ratio; in intel_hdmi_compute_config()
2337 pipe_config->lane_count = 4; in intel_hdmi_compute_config()
2339 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) { in intel_hdmi_compute_config()
2340 if (scdc->scrambling.low_rates) in intel_hdmi_compute_config()
2341 pipe_config->hdmi_scrambling = true; in intel_hdmi_compute_config()
2343 if (pipe_config->port_clock > 340000) { in intel_hdmi_compute_config()
2344 pipe_config->hdmi_scrambling = true; in intel_hdmi_compute_config()
2345 pipe_config->hdmi_high_tmds_clock_ratio = true; in intel_hdmi_compute_config()
2353 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n"); in intel_hdmi_compute_config()
2354 return -EINVAL; in intel_hdmi_compute_config()
2358 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n"); in intel_hdmi_compute_config()
2359 return -EINVAL; in intel_hdmi_compute_config()
2363 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n"); in intel_hdmi_compute_config()
2364 return -EINVAL; in intel_hdmi_compute_config()
2368 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n"); in intel_hdmi_compute_config()
2369 return -EINVAL; in intel_hdmi_compute_config()
2391 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; in intel_hdmi_unset_edid()
2392 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; in intel_hdmi_unset_edid()
2394 drm_edid_free(to_intel_connector(connector)->detect_edid); in intel_hdmi_unset_edid()
2395 to_intel_connector(connector)->detect_edid = NULL; in intel_hdmi_unset_edid()
2401 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_dp_dual_mode_detect()
2403 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; in intel_hdmi_dp_dual_mode_detect()
2404 struct i2c_adapter *ddc = connector->ddc; in intel_hdmi_dp_dual_mode_detect() local
2407 type = drm_dp_dual_mode_detect(&dev_priv->drm, ddc); in intel_hdmi_dp_dual_mode_detect()
2419 if (!connector->force && in intel_hdmi_dp_dual_mode_detect()
2420 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { in intel_hdmi_dp_dual_mode_detect()
2421 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_dp_dual_mode_detect()
2432 hdmi->dp_dual_mode.type = type; in intel_hdmi_dp_dual_mode_detect()
2433 hdmi->dp_dual_mode.max_tmds_clock = in intel_hdmi_dp_dual_mode_detect()
2434 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, ddc); in intel_hdmi_dp_dual_mode_detect()
2436 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_dp_dual_mode_detect()
2439 hdmi->dp_dual_mode.max_tmds_clock); in intel_hdmi_dp_dual_mode_detect()
2443 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { in intel_hdmi_dp_dual_mode_detect()
2444 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_dp_dual_mode_detect()
2446 hdmi->dp_dual_mode.max_tmds_clock = 0; in intel_hdmi_dp_dual_mode_detect()
2453 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_set_edid()
2455 struct i2c_adapter *ddc = connector->ddc; in intel_hdmi_set_edid() local
2462 drm_edid = drm_edid_read_ddc(connector, ddc); in intel_hdmi_set_edid()
2464 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) { in intel_hdmi_set_edid()
2465 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_set_edid()
2466 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); in intel_hdmi_set_edid()
2467 intel_gmbus_force_bit(ddc, true); in intel_hdmi_set_edid()
2468 drm_edid = drm_edid_read_ddc(connector, ddc); in intel_hdmi_set_edid()
2469 intel_gmbus_force_bit(ddc, false); in intel_hdmi_set_edid()
2475 to_intel_connector(connector)->detect_edid = drm_edid; in intel_hdmi_set_edid()
2485 cec_notifier_set_phys_addr(intel_hdmi->cec_notifier, in intel_hdmi_set_edid()
2486 connector->display_info.source_physical_address); in intel_hdmi_set_edid()
2495 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_detect()
2497 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; in intel_hdmi_detect()
2500 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", in intel_hdmi_detect()
2501 connector->base.id, connector->name); in intel_hdmi_detect()
2521 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); in intel_hdmi_detect()
2529 struct drm_i915_private *i915 = to_i915(connector->dev); in intel_hdmi_force()
2531 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", in intel_hdmi_force()
2532 connector->base.id, connector->name); in intel_hdmi_force()
2536 if (connector->status != connector_status_connected) in intel_hdmi_force()
2544 /* drm_edid_connector_update() done in ->detect() or ->force() */ in intel_hdmi_get_modes()
2562 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; in intel_hdmi_connector_unregister()
2585 struct drm_i915_private *i915 = to_i915(state->dev); in intel_hdmi_connector_atomic_check()
2602 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_add_properties()
2641 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_handle_sink_scrambling()
2643 &connector->display_info.hdmi.scdc.scrambling; in intel_hdmi_handle_sink_scrambling()
2645 if (!sink_scrambling->supported) in intel_hdmi_handle_sink_scrambling()
2648 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_handle_sink_scrambling()
2650 connector->base.id, connector->name, in intel_hdmi_handle_sink_scrambling()
2734 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); in icl_port_to_ddc_pin()
2769 * final two outputs use type-c pins, even though they're actually in rkl_port_to_ddc_pin()
2770 * combo outputs. With CMP, the traditional DDI A-D pins are used for in rkl_port_to_ddc_pin()
2774 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; in rkl_port_to_ddc_pin()
2783 drm_WARN_ON(&i915->drm, port == PORT_A); in gen9bc_tgp_port_to_ddc_pin()
2787 * final two outputs use type-c pins, even though they're actually in gen9bc_tgp_port_to_ddc_pin()
2788 * combo outputs. With CMP, the traditional DDI A-D pins are used for in gen9bc_tgp_port_to_ddc_pin()
2792 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; in gen9bc_tgp_port_to_ddc_pin()
2809 * Pin mapping for ADL-S requires TC pins for all combo phy outputs in adls_port_to_ddc_pin()
2815 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; in adls_port_to_ddc_pin()
2843 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_default_ddc_pin()
2844 enum port port = encoder->port; in intel_hdmi_default_ddc_pin()
2875 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in get_encoder_by_ddc_pin()
2878 for_each_intel_encoder(&i915->drm, other) { in get_encoder_by_ddc_pin()
2887 connector = enc_to_dig_port(other)->hdmi.attached_connector; in get_encoder_by_ddc_pin()
2889 if (connector && connector->base.ddc == intel_gmbus_get_adapter(i915, ddc_pin)) in get_encoder_by_ddc_pin()
2898 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_hdmi_ddc_pin()
2903 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata); in intel_hdmi_ddc_pin()
2912 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Invalid DDC pin %d\n", in intel_hdmi_ddc_pin()
2913 encoder->base.base.id, encoder->base.name, ddc_pin); in intel_hdmi_ddc_pin()
2919 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] DDC pin %d already claimed by [ENCODER:%d:%s]\n", in intel_hdmi_ddc_pin()
2920 encoder->base.base.id, encoder->base.name, ddc_pin, in intel_hdmi_ddc_pin()
2921 other->base.base.id, other->base.name); in intel_hdmi_ddc_pin()
2925 drm_dbg_kms(&i915->drm, in intel_hdmi_ddc_pin()
2926 "[ENCODER:%d:%s] Using DDC pin 0x%x (%s)\n", in intel_hdmi_ddc_pin()
2927 encoder->base.base.id, encoder->base.name, in intel_hdmi_ddc_pin()
2936 to_i915(dig_port->base.base.dev); in intel_infoframe_init()
2939 dig_port->write_infoframe = vlv_write_infoframe; in intel_infoframe_init()
2940 dig_port->read_infoframe = vlv_read_infoframe; in intel_infoframe_init()
2941 dig_port->set_infoframes = vlv_set_infoframes; in intel_infoframe_init()
2942 dig_port->infoframes_enabled = vlv_infoframes_enabled; in intel_infoframe_init()
2944 dig_port->write_infoframe = g4x_write_infoframe; in intel_infoframe_init()
2945 dig_port->read_infoframe = g4x_read_infoframe; in intel_infoframe_init()
2946 dig_port->set_infoframes = g4x_set_infoframes; in intel_infoframe_init()
2947 dig_port->infoframes_enabled = g4x_infoframes_enabled; in intel_infoframe_init()
2949 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) { in intel_infoframe_init()
2950 dig_port->write_infoframe = lspcon_write_infoframe; in intel_infoframe_init()
2951 dig_port->read_infoframe = lspcon_read_infoframe; in intel_infoframe_init()
2952 dig_port->set_infoframes = lspcon_set_infoframes; in intel_infoframe_init()
2953 dig_port->infoframes_enabled = lspcon_infoframes_enabled; in intel_infoframe_init()
2955 dig_port->write_infoframe = hsw_write_infoframe; in intel_infoframe_init()
2956 dig_port->read_infoframe = hsw_read_infoframe; in intel_infoframe_init()
2957 dig_port->set_infoframes = hsw_set_infoframes; in intel_infoframe_init()
2958 dig_port->infoframes_enabled = hsw_infoframes_enabled; in intel_infoframe_init()
2961 dig_port->write_infoframe = ibx_write_infoframe; in intel_infoframe_init()
2962 dig_port->read_infoframe = ibx_read_infoframe; in intel_infoframe_init()
2963 dig_port->set_infoframes = ibx_set_infoframes; in intel_infoframe_init()
2964 dig_port->infoframes_enabled = ibx_infoframes_enabled; in intel_infoframe_init()
2966 dig_port->write_infoframe = cpt_write_infoframe; in intel_infoframe_init()
2967 dig_port->read_infoframe = cpt_read_infoframe; in intel_infoframe_init()
2968 dig_port->set_infoframes = cpt_set_infoframes; in intel_infoframe_init()
2969 dig_port->infoframes_enabled = cpt_infoframes_enabled; in intel_infoframe_init()
2976 struct drm_connector *connector = &intel_connector->base; in intel_hdmi_init_connector()
2977 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in intel_hdmi_init_connector()
2978 struct intel_encoder *intel_encoder = &dig_port->base; in intel_hdmi_init_connector()
2979 struct drm_device *dev = intel_encoder->base.dev; in intel_hdmi_init_connector()
2981 enum port port = intel_encoder->port; in intel_hdmi_init_connector()
2985 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_init_connector()
2987 intel_encoder->base.base.id, intel_encoder->base.name); in intel_hdmi_init_connector()
2992 if (drm_WARN(dev, dig_port->max_lanes < 4, in intel_hdmi_init_connector()
2994 dig_port->max_lanes, intel_encoder->base.base.id, in intel_hdmi_init_connector()
2995 intel_encoder->base.name)) in intel_hdmi_init_connector()
3010 connector->interlace_allowed = true; in intel_hdmi_init_connector()
3012 connector->stereo_allowed = true; in intel_hdmi_init_connector()
3015 connector->ycbcr_420_allowed = true; in intel_hdmi_init_connector()
3017 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; in intel_hdmi_init_connector()
3020 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; in intel_hdmi_init_connector()
3022 intel_connector->get_hw_state = intel_connector_get_hw_state; in intel_hdmi_init_connector()
3027 intel_hdmi->attached_connector = intel_connector; in intel_hdmi_init_connector()
3033 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_init_connector()
3039 intel_hdmi->cec_notifier = in intel_hdmi_init_connector()
3040 cec_notifier_conn_register(dev->dev, port_identifier(port), in intel_hdmi_init_connector()
3042 if (!intel_hdmi->cec_notifier) in intel_hdmi_init_connector()
3043 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n"); in intel_hdmi_init_connector()
3047 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3071 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3106 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; in intel_hdmi_dsc_get_num_slices()
3117 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || in intel_hdmi_dsc_get_num_slices()
3118 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) in intel_hdmi_dsc_get_num_slices()
3141 * clock per slice (in MHz) as read from HF-VSDB. in intel_hdmi_dsc_get_num_slices()
3173 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); in intel_hdmi_dsc_get_num_slices()
3182 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3260 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; in intel_hdmi_dsc_get_bpp()
3271 bpp_target_x16 -= bpp_decrement_x16; in intel_hdmi_dsc_get_bpp()