49  * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
929 	unsigned int tiles;  in intel_adjust_tile_offset()  local
935 	tiles = (old_offset - new_offset) / tile_size;  in intel_adjust_tile_offset()
937 	*y += tiles / pitch_tiles * tile_height;  in intel_adjust_tile_offset()
938 	*x += tiles % pitch_tiles * tile_width;  in intel_adjust_tile_offset()
1040 		unsigned int tile_rows, tiles, pitch_tiles;  in intel_compute_aligned_offset()  local
1055 		tiles = *x / tile_width;  in intel_compute_aligned_offset()
1058 		offset = (tile_rows * pitch_tiles + tiles) * tile_size;  in intel_compute_aligned_offset()
1368 		 * of 8 main surface tiles.  in plane_view_dst_stride_tiles()
1561 /* Return number of tiles @color_plane needs. */
1567 	unsigned int tiles;  in calc_plane_normal_size()  local
1570 		tiles = plane_view_linear_tiles(fb, color_plane, dims, x, y);  in calc_plane_normal_size()
1572 		tiles = plane_view_src_stride_tiles(fb, color_plane, dims) *  in calc_plane_normal_size()
1579 			tiles++;  in calc_plane_normal_size()
1582 	return tiles;  in calc_plane_normal_size()
1676 		/* how many tiles in total needed in the bo */  in intel_fill_fb_info()