Lines Matching full:i915
66 void (*enable)(struct drm_i915_private *i915,
74 void (*disable)(struct drm_i915_private *i915,
82 bool (*get_hw_state)(struct drm_i915_private *i915,
90 int (*get_freq)(struct drm_i915_private *i915,
109 void (*update_ref_clks)(struct drm_i915_private *i915);
110 void (*dump_hw_state)(struct drm_i915_private *i915,
115 intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915, in intel_atomic_duplicate_dpll_state() argument
122 for_each_shared_dpll(i915, pll, i) in intel_atomic_duplicate_dpll_state()
145 * @i915: i915 device instance
152 intel_get_shared_dpll_by_id(struct drm_i915_private *i915, in intel_get_shared_dpll_by_id() argument
158 for_each_shared_dpll(i915, pll, i) { in intel_get_shared_dpll_by_id()
168 void assert_shared_dpll(struct drm_i915_private *i915, in assert_shared_dpll() argument
175 if (drm_WARN(&i915->drm, !pll, in assert_shared_dpll()
179 cur_state = intel_dpll_get_hw_state(i915, pll, &hw_state); in assert_shared_dpll()
180 I915_STATE_WARN(i915, cur_state != state, in assert_shared_dpll()
197 intel_combo_pll_enable_reg(struct drm_i915_private *i915, in intel_combo_pll_enable_reg() argument
200 if (IS_DG1(i915)) in intel_combo_pll_enable_reg()
202 else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && in intel_combo_pll_enable_reg()
210 intel_tc_pll_enable_reg(struct drm_i915_private *i915, in intel_tc_pll_enable_reg() argument
216 if (IS_ALDERLAKE_P(i915)) in intel_tc_pll_enable_reg()
222 static void _intel_enable_shared_dpll(struct drm_i915_private *i915, in _intel_enable_shared_dpll() argument
226 pll->wakeref = intel_display_power_get(i915, pll->info->power_domain); in _intel_enable_shared_dpll()
228 pll->info->funcs->enable(i915, pll); in _intel_enable_shared_dpll()
232 static void _intel_disable_shared_dpll(struct drm_i915_private *i915, in _intel_disable_shared_dpll() argument
235 pll->info->funcs->disable(i915, pll); in _intel_disable_shared_dpll()
239 intel_display_power_put(i915, pll->info->power_domain, pll->wakeref); in _intel_disable_shared_dpll()
251 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_enable_shared_dpll() local
256 if (drm_WARN_ON(&i915->drm, pll == NULL)) in intel_enable_shared_dpll()
259 mutex_lock(&i915->display.dpll.lock); in intel_enable_shared_dpll()
262 if (drm_WARN_ON(&i915->drm, !(pll->state.pipe_mask & pipe_mask)) || in intel_enable_shared_dpll()
263 drm_WARN_ON(&i915->drm, pll->active_mask & pipe_mask)) in intel_enable_shared_dpll()
268 drm_dbg_kms(&i915->drm, in intel_enable_shared_dpll()
274 drm_WARN_ON(&i915->drm, !pll->on); in intel_enable_shared_dpll()
275 assert_shared_dpll_enabled(i915, pll); in intel_enable_shared_dpll()
278 drm_WARN_ON(&i915->drm, pll->on); in intel_enable_shared_dpll()
280 drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name); in intel_enable_shared_dpll()
282 _intel_enable_shared_dpll(i915, pll); in intel_enable_shared_dpll()
285 mutex_unlock(&i915->display.dpll.lock); in intel_enable_shared_dpll()
297 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_disable_shared_dpll() local
302 if (DISPLAY_VER(i915) < 5) in intel_disable_shared_dpll()
308 mutex_lock(&i915->display.dpll.lock); in intel_disable_shared_dpll()
309 if (drm_WARN(&i915->drm, !(pll->active_mask & pipe_mask), in intel_disable_shared_dpll()
314 drm_dbg_kms(&i915->drm, in intel_disable_shared_dpll()
319 assert_shared_dpll_enabled(i915, pll); in intel_disable_shared_dpll()
320 drm_WARN_ON(&i915->drm, !pll->on); in intel_disable_shared_dpll()
326 drm_dbg_kms(&i915->drm, "disabling %s\n", pll->info->name); in intel_disable_shared_dpll()
328 _intel_disable_shared_dpll(i915, pll); in intel_disable_shared_dpll()
331 mutex_unlock(&i915->display.dpll.lock); in intel_disable_shared_dpll()
335 intel_dpll_mask_all(struct drm_i915_private *i915) in intel_dpll_mask_all() argument
341 for_each_shared_dpll(i915, pll, i) { in intel_dpll_mask_all()
342 drm_WARN_ON(&i915->drm, dpll_mask & BIT(pll->info->id)); in intel_dpll_mask_all()
356 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_find_shared_dpll() local
357 unsigned long dpll_mask_all = intel_dpll_mask_all(i915); in intel_find_shared_dpll()
364 drm_WARN_ON(&i915->drm, dpll_mask & ~dpll_mask_all); in intel_find_shared_dpll()
369 pll = intel_get_shared_dpll_by_id(i915, id); in intel_find_shared_dpll()
383 drm_dbg_kms(&i915->drm, in intel_find_shared_dpll()
395 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] allocated %s\n", in intel_find_shared_dpll()
417 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_reference_shared_dpll_crtc() local
419 drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0); in intel_reference_shared_dpll_crtc()
423 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] reserving %s\n", in intel_reference_shared_dpll_crtc()
456 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_unreference_shared_dpll_crtc() local
458 drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0); in intel_unreference_shared_dpll_crtc()
462 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] releasing %s\n", in intel_unreference_shared_dpll_crtc()
506 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_shared_dpll_swap_state() local
514 for_each_shared_dpll(i915, pll, i) in intel_shared_dpll_swap_state()
518 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915, in ibx_pch_dpll_get_hw_state() argument
526 wakeref = intel_display_power_get_if_enabled(i915, in ibx_pch_dpll_get_hw_state()
531 val = intel_de_read(i915, PCH_DPLL(id)); in ibx_pch_dpll_get_hw_state()
533 hw_state->fp0 = intel_de_read(i915, PCH_FP0(id)); in ibx_pch_dpll_get_hw_state()
534 hw_state->fp1 = intel_de_read(i915, PCH_FP1(id)); in ibx_pch_dpll_get_hw_state()
536 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in ibx_pch_dpll_get_hw_state()
541 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915) in ibx_assert_pch_refclk_enabled() argument
546 val = intel_de_read(i915, PCH_DREF_CONTROL); in ibx_assert_pch_refclk_enabled()
549 I915_STATE_WARN(i915, !enabled, in ibx_assert_pch_refclk_enabled()
553 static void ibx_pch_dpll_enable(struct drm_i915_private *i915, in ibx_pch_dpll_enable() argument
559 ibx_assert_pch_refclk_enabled(i915); in ibx_pch_dpll_enable()
561 intel_de_write(i915, PCH_FP0(id), pll->state.hw_state.fp0); in ibx_pch_dpll_enable()
562 intel_de_write(i915, PCH_FP1(id), pll->state.hw_state.fp1); in ibx_pch_dpll_enable()
564 intel_de_write(i915, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
567 intel_de_posting_read(i915, PCH_DPLL(id)); in ibx_pch_dpll_enable()
575 intel_de_write(i915, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
576 intel_de_posting_read(i915, PCH_DPLL(id)); in ibx_pch_dpll_enable()
580 static void ibx_pch_dpll_disable(struct drm_i915_private *i915, in ibx_pch_dpll_disable() argument
585 intel_de_write(i915, PCH_DPLL(id), 0); in ibx_pch_dpll_disable()
586 intel_de_posting_read(i915, PCH_DPLL(id)); in ibx_pch_dpll_disable()
603 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in ibx_get_dpll() local
607 if (HAS_PCH_IBX(i915)) { in ibx_get_dpll()
610 pll = intel_get_shared_dpll_by_id(i915, id); in ibx_get_dpll()
612 drm_dbg_kms(&i915->drm, in ibx_get_dpll()
635 static void ibx_dump_hw_state(struct drm_i915_private *i915, in ibx_dump_hw_state() argument
638 drm_dbg_kms(&i915->drm, in ibx_dump_hw_state()
667 static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915, in hsw_ddi_wrpll_enable() argument
672 intel_de_write(i915, WRPLL_CTL(id), pll->state.hw_state.wrpll); in hsw_ddi_wrpll_enable()
673 intel_de_posting_read(i915, WRPLL_CTL(id)); in hsw_ddi_wrpll_enable()
677 static void hsw_ddi_spll_enable(struct drm_i915_private *i915, in hsw_ddi_spll_enable() argument
680 intel_de_write(i915, SPLL_CTL, pll->state.hw_state.spll); in hsw_ddi_spll_enable()
681 intel_de_posting_read(i915, SPLL_CTL); in hsw_ddi_spll_enable()
685 static void hsw_ddi_wrpll_disable(struct drm_i915_private *i915, in hsw_ddi_wrpll_disable() argument
690 intel_de_rmw(i915, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0); in hsw_ddi_wrpll_disable()
691 intel_de_posting_read(i915, WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
697 if (i915->display.dpll.pch_ssc_use & BIT(id)) in hsw_ddi_wrpll_disable()
698 intel_init_pch_refclk(i915); in hsw_ddi_wrpll_disable()
701 static void hsw_ddi_spll_disable(struct drm_i915_private *i915, in hsw_ddi_spll_disable() argument
706 intel_de_rmw(i915, SPLL_CTL, SPLL_PLL_ENABLE, 0); in hsw_ddi_spll_disable()
707 intel_de_posting_read(i915, SPLL_CTL); in hsw_ddi_spll_disable()
713 if (i915->display.dpll.pch_ssc_use & BIT(id)) in hsw_ddi_spll_disable()
714 intel_init_pch_refclk(i915); in hsw_ddi_spll_disable()
717 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915, in hsw_ddi_wrpll_get_hw_state() argument
725 wakeref = intel_display_power_get_if_enabled(i915, in hsw_ddi_wrpll_get_hw_state()
730 val = intel_de_read(i915, WRPLL_CTL(id)); in hsw_ddi_wrpll_get_hw_state()
733 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in hsw_ddi_wrpll_get_hw_state()
738 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915, in hsw_ddi_spll_get_hw_state() argument
745 wakeref = intel_display_power_get_if_enabled(i915, in hsw_ddi_spll_get_hw_state()
750 val = intel_de_read(i915, SPLL_CTL); in hsw_ddi_spll_get_hw_state()
753 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in hsw_ddi_spll_get_hw_state()
964 static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915, in hsw_ddi_wrpll_get_freq() argument
975 if (IS_HASWELL(i915) && !IS_HASWELL_ULT(i915)) { in hsw_ddi_wrpll_get_freq()
976 refclk = i915->display.dpll.ref_clks.nssc; in hsw_ddi_wrpll_get_freq()
986 refclk = i915->display.dpll.ref_clks.ssc; in hsw_ddi_wrpll_get_freq()
1008 struct drm_i915_private *i915 = to_i915(state->base.dev); in hsw_ddi_wrpll_compute_dpll() local
1020 crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL, in hsw_ddi_wrpll_compute_dpll()
1042 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in hsw_ddi_lcpll_compute_dpll() local
1051 drm_dbg_kms(&i915->drm, "Invalid clock for DP: %d\n", in hsw_ddi_lcpll_compute_dpll()
1060 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in hsw_ddi_lcpll_get_dpll() local
1080 pll = intel_get_shared_dpll_by_id(i915, pll_id); in hsw_ddi_lcpll_get_dpll()
1088 static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915, in hsw_ddi_lcpll_get_freq() argument
1105 drm_WARN(&i915->drm, 1, "bad port clock sel\n"); in hsw_ddi_lcpll_get_freq()
1139 static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915, in hsw_ddi_spll_get_freq() argument
1156 drm_WARN(&i915->drm, 1, "bad spll freq\n"); in hsw_ddi_spll_get_freq()
1206 static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915) in hsw_update_dpll_ref_clks() argument
1208 i915->display.dpll.ref_clks.ssc = 135000; in hsw_update_dpll_ref_clks()
1210 if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT) in hsw_update_dpll_ref_clks()
1211 i915->display.dpll.ref_clks.nssc = 24000; in hsw_update_dpll_ref_clks()
1213 i915->display.dpll.ref_clks.nssc = 135000; in hsw_update_dpll_ref_clks()
1216 static void hsw_dump_hw_state(struct drm_i915_private *i915, in hsw_dump_hw_state() argument
1219 drm_dbg_kms(&i915->drm, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", in hsw_dump_hw_state()
1237 static void hsw_ddi_lcpll_enable(struct drm_i915_private *i915, in hsw_ddi_lcpll_enable() argument
1242 static void hsw_ddi_lcpll_disable(struct drm_i915_private *i915, in hsw_ddi_lcpll_disable() argument
1247 static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *i915, in hsw_ddi_lcpll_get_hw_state() argument
1314 static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915, in skl_ddi_pll_write_ctrl1() argument
1319 intel_de_rmw(i915, DPLL_CTRL1, in skl_ddi_pll_write_ctrl1()
1322 intel_de_posting_read(i915, DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
1325 static void skl_ddi_pll_enable(struct drm_i915_private *i915, in skl_ddi_pll_enable() argument
1331 skl_ddi_pll_write_ctrl1(i915, pll); in skl_ddi_pll_enable()
1333 intel_de_write(i915, regs[id].cfgcr1, pll->state.hw_state.cfgcr1); in skl_ddi_pll_enable()
1334 intel_de_write(i915, regs[id].cfgcr2, pll->state.hw_state.cfgcr2); in skl_ddi_pll_enable()
1335 intel_de_posting_read(i915, regs[id].cfgcr1); in skl_ddi_pll_enable()
1336 intel_de_posting_read(i915, regs[id].cfgcr2); in skl_ddi_pll_enable()
1339 intel_de_rmw(i915, regs[id].ctl, 0, LCPLL_PLL_ENABLE); in skl_ddi_pll_enable()
1341 if (intel_de_wait_for_set(i915, DPLL_STATUS, DPLL_LOCK(id), 5)) in skl_ddi_pll_enable()
1342 drm_err(&i915->drm, "DPLL %d not locked\n", id); in skl_ddi_pll_enable()
1345 static void skl_ddi_dpll0_enable(struct drm_i915_private *i915, in skl_ddi_dpll0_enable() argument
1348 skl_ddi_pll_write_ctrl1(i915, pll); in skl_ddi_dpll0_enable()
1351 static void skl_ddi_pll_disable(struct drm_i915_private *i915, in skl_ddi_pll_disable() argument
1358 intel_de_rmw(i915, regs[id].ctl, LCPLL_PLL_ENABLE, 0); in skl_ddi_pll_disable()
1359 intel_de_posting_read(i915, regs[id].ctl); in skl_ddi_pll_disable()
1362 static void skl_ddi_dpll0_disable(struct drm_i915_private *i915, in skl_ddi_dpll0_disable() argument
1367 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915, in skl_ddi_pll_get_hw_state() argument
1377 wakeref = intel_display_power_get_if_enabled(i915, in skl_ddi_pll_get_hw_state()
1384 val = intel_de_read(i915, regs[id].ctl); in skl_ddi_pll_get_hw_state()
1388 val = intel_de_read(i915, DPLL_CTRL1); in skl_ddi_pll_get_hw_state()
1393 hw_state->cfgcr1 = intel_de_read(i915, regs[id].cfgcr1); in skl_ddi_pll_get_hw_state()
1394 hw_state->cfgcr2 = intel_de_read(i915, regs[id].cfgcr2); in skl_ddi_pll_get_hw_state()
1399 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in skl_ddi_pll_get_hw_state()
1404 static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915, in skl_ddi_dpll0_get_hw_state() argument
1414 wakeref = intel_display_power_get_if_enabled(i915, in skl_ddi_dpll0_get_hw_state()
1422 val = intel_de_read(i915, regs[id].ctl); in skl_ddi_dpll0_get_hw_state()
1423 if (drm_WARN_ON(&i915->drm, !(val & LCPLL_PLL_ENABLE))) in skl_ddi_dpll0_get_hw_state()
1426 val = intel_de_read(i915, DPLL_CTRL1); in skl_ddi_dpll0_get_hw_state()
1432 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in skl_ddi_dpll0_get_hw_state()
1676 static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915, in skl_ddi_wrpll_get_freq() argument
1680 int ref_clock = i915->display.dpll.ref_clks.nssc; in skl_ddi_wrpll_get_freq()
1707 drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n"); in skl_ddi_wrpll_get_freq()
1741 if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0)) in skl_ddi_wrpll_get_freq()
1749 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in skl_ddi_hdmi_pll_dividers() local
1763 i915->display.dpll.ref_clks.nssc, &wrpll_params); in skl_ddi_hdmi_pll_dividers()
1781 crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL, in skl_ddi_hdmi_pll_dividers()
1824 static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915, in skl_ddi_lcpll_get_freq() argument
1851 drm_WARN(&i915->drm, 1, "Unsupported link rate\n"); in skl_ddi_lcpll_get_freq()
1902 static int skl_ddi_pll_get_freq(struct drm_i915_private *i915, in skl_ddi_pll_get_freq() argument
1911 return skl_ddi_wrpll_get_freq(i915, pll, pll_state); in skl_ddi_pll_get_freq()
1913 return skl_ddi_lcpll_get_freq(i915, pll, pll_state); in skl_ddi_pll_get_freq()
1916 static void skl_update_dpll_ref_clks(struct drm_i915_private *i915) in skl_update_dpll_ref_clks() argument
1919 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()
1922 static void skl_dump_hw_state(struct drm_i915_private *i915, in skl_dump_hw_state() argument
1925 drm_dbg_kms(&i915->drm, "dpll_hw_state: " in skl_dump_hw_state()
1964 static void bxt_ddi_pll_enable(struct drm_i915_private *i915, in bxt_ddi_pll_enable() argument
1972 bxt_port_to_phy_channel(i915, port, &phy, &ch); in bxt_ddi_pll_enable()
1975 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL); in bxt_ddi_pll_enable()
1977 if (IS_GEMINILAKE(i915)) { in bxt_ddi_pll_enable()
1978 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), in bxt_ddi_pll_enable()
1981 if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & in bxt_ddi_pll_enable()
1983 drm_err(&i915->drm, in bxt_ddi_pll_enable()
1988 intel_de_rmw(i915, BXT_PORT_PLL_EBB_4(phy, ch), in bxt_ddi_pll_enable()
1992 intel_de_rmw(i915, BXT_PORT_PLL_EBB_0(phy, ch), in bxt_ddi_pll_enable()
1996 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 0), in bxt_ddi_pll_enable()
2000 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 1), in bxt_ddi_pll_enable()
2004 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 2), in bxt_ddi_pll_enable()
2008 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 3), in bxt_ddi_pll_enable()
2012 temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6)); in bxt_ddi_pll_enable()
2017 intel_de_write(i915, BXT_PORT_PLL(phy, ch, 6), temp); in bxt_ddi_pll_enable()
2020 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 8), in bxt_ddi_pll_enable()
2023 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 9), in bxt_ddi_pll_enable()
2026 temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10)); in bxt_ddi_pll_enable()
2030 intel_de_write(i915, BXT_PORT_PLL(phy, ch, 10), temp); in bxt_ddi_pll_enable()
2033 temp = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch)); in bxt_ddi_pll_enable()
2035 intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp); in bxt_ddi_pll_enable()
2038 intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp); in bxt_ddi_pll_enable()
2041 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE); in bxt_ddi_pll_enable()
2042 intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port)); in bxt_ddi_pll_enable()
2044 if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), in bxt_ddi_pll_enable()
2046 drm_err(&i915->drm, "PLL %d not locked\n", port); in bxt_ddi_pll_enable()
2048 if (IS_GEMINILAKE(i915)) { in bxt_ddi_pll_enable()
2049 temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN0(phy, ch)); in bxt_ddi_pll_enable()
2051 intel_de_write(i915, BXT_PORT_TX_DW5_GRP(phy, ch), temp); in bxt_ddi_pll_enable()
2058 temp = intel_de_read(i915, BXT_PORT_PCS_DW12_LN01(phy, ch)); in bxt_ddi_pll_enable()
2062 intel_de_write(i915, BXT_PORT_PCS_DW12_GRP(phy, ch), temp); in bxt_ddi_pll_enable()
2065 static void bxt_ddi_pll_disable(struct drm_i915_private *i915, in bxt_ddi_pll_disable() argument
2070 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0); in bxt_ddi_pll_disable()
2071 intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port)); in bxt_ddi_pll_disable()
2073 if (IS_GEMINILAKE(i915)) { in bxt_ddi_pll_disable()
2074 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), in bxt_ddi_pll_disable()
2077 if (wait_for_us(!(intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & in bxt_ddi_pll_disable()
2079 drm_err(&i915->drm, in bxt_ddi_pll_disable()
2084 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915, in bxt_ddi_pll_get_hw_state() argument
2095 bxt_port_to_phy_channel(i915, port, &phy, &ch); in bxt_ddi_pll_get_hw_state()
2097 wakeref = intel_display_power_get_if_enabled(i915, in bxt_ddi_pll_get_hw_state()
2104 val = intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)); in bxt_ddi_pll_get_hw_state()
2108 hw_state->ebb0 = intel_de_read(i915, BXT_PORT_PLL_EBB_0(phy, ch)); in bxt_ddi_pll_get_hw_state()
2111 hw_state->ebb4 = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch)); in bxt_ddi_pll_get_hw_state()
2114 hw_state->pll0 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 0)); in bxt_ddi_pll_get_hw_state()
2117 hw_state->pll1 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 1)); in bxt_ddi_pll_get_hw_state()
2120 hw_state->pll2 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 2)); in bxt_ddi_pll_get_hw_state()
2123 hw_state->pll3 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 3)); in bxt_ddi_pll_get_hw_state()
2126 hw_state->pll6 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6)); in bxt_ddi_pll_get_hw_state()
2131 hw_state->pll8 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 8)); in bxt_ddi_pll_get_hw_state()
2134 hw_state->pll9 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 9)); in bxt_ddi_pll_get_hw_state()
2137 hw_state->pll10 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10)); in bxt_ddi_pll_get_hw_state()
2146 hw_state->pcsdw12 = intel_de_read(i915, in bxt_ddi_pll_get_hw_state()
2148 if (intel_de_read(i915, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) in bxt_ddi_pll_get_hw_state()
2149 drm_dbg(&i915->drm, in bxt_ddi_pll_get_hw_state()
2152 intel_de_read(i915, in bxt_ddi_pll_get_hw_state()
2159 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in bxt_ddi_pll_get_hw_state()
2180 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_hdmi_pll_dividers() local
2190 drm_WARN_ON(&i915->drm, clk_div->m1 != 2); in bxt_ddi_hdmi_pll_dividers()
2198 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_dp_pll_dividers() local
2209 chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div); in bxt_ddi_dp_pll_dividers()
2211 drm_WARN_ON(&i915->drm, clk_div->vco == 0 || in bxt_ddi_dp_pll_dividers()
2218 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_set_dpll_hw_state() local
2242 drm_err(&i915->drm, "Invalid VCO\n"); in bxt_ddi_set_dpll_hw_state()
2283 static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915, in bxt_ddi_pll_get_freq() argument
2297 return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock); in bxt_ddi_pll_get_freq()
2313 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_hdmi_set_dpll_hw_state() local
2323 crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL, in bxt_ddi_hdmi_set_dpll_hw_state()
2350 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in bxt_get_dpll() local
2356 pll = intel_get_shared_dpll_by_id(i915, id); in bxt_get_dpll()
2358 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n", in bxt_get_dpll()
2369 static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915) in bxt_update_dpll_ref_clks() argument
2371 i915->display.dpll.ref_clks.ssc = 100000; in bxt_update_dpll_ref_clks()
2372 i915->display.dpll.ref_clks.nssc = 100000; in bxt_update_dpll_ref_clks()
2376 static void bxt_dump_hw_state(struct drm_i915_private *i915, in bxt_dump_hw_state() argument
2379 drm_dbg_kms(&i915->drm, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," in bxt_dump_hw_state()
2510 ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915) in ehl_combo_pll_div_frac_wa_needed() argument
2512 return (((IS_ELKHARTLAKE(i915) || IS_JASPERLAKE(i915)) && in ehl_combo_pll_div_frac_wa_needed()
2513 IS_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) || in ehl_combo_pll_div_frac_wa_needed()
2514 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) && in ehl_combo_pll_div_frac_wa_needed()
2515 i915->display.dpll.ref_clks.nssc == 38400; in ehl_combo_pll_div_frac_wa_needed()
2607 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_dp_combo_pll() local
2609 i915->display.dpll.ref_clks.nssc == 24000 ? in icl_calc_dp_combo_pll()
2629 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_tbt_pll() local
2631 if (DISPLAY_VER(i915) >= 12) { in icl_calc_tbt_pll()
2632 switch (i915->display.dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2634 MISSING_CASE(i915->display.dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2645 switch (i915->display.dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2647 MISSING_CASE(i915->display.dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2662 static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915, in icl_ddi_tbt_pll_get_freq() argument
2670 drm_WARN_ON(&i915->drm, 1); in icl_ddi_tbt_pll_get_freq()
2675 static int icl_wrpll_ref_clock(struct drm_i915_private *i915) in icl_wrpll_ref_clock() argument
2677 int ref_clock = i915->display.dpll.ref_clks.nssc; in icl_wrpll_ref_clock()
2693 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_wrpll() local
2694 int ref_clock = icl_wrpll_ref_clock(i915); in icl_calc_wrpll()
2733 static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915, in icl_ddi_combo_pll_get_freq() argument
2737 int ref_clock = icl_wrpll_ref_clock(i915); in icl_ddi_combo_pll_get_freq()
2783 if (ehl_combo_pll_div_frac_wa_needed(i915)) in icl_ddi_combo_pll_get_freq()
2788 if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0)) in icl_ddi_combo_pll_get_freq()
2794 static void icl_calc_dpll_state(struct drm_i915_private *i915, in icl_calc_dpll_state() argument
2800 if (ehl_combo_pll_div_frac_wa_needed(i915)) in icl_calc_dpll_state()
2811 if (DISPLAY_VER(i915) >= 12) in icl_calc_dpll_state()
2816 if (i915->display.vbt.override_afc_startup) in icl_calc_dpll_state()
2817 pll_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val); in icl_calc_dpll_state()
2903 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_mg_pll_state() local
2904 int refclk_khz = i915->display.dpll.ref_clks.nssc; in icl_calc_mg_pll_state()
2914 bool is_dkl = DISPLAY_VER(i915) >= 12; in icl_calc_mg_pll_state()
3012 if (i915->display.vbt.override_afc_startup) { in icl_calc_mg_pll_state()
3013 u8 val = i915->display.vbt.override_afc_startup_val; in icl_calc_mg_pll_state()
3103 static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915, in icl_ddi_mg_pll_get_freq() argument
3110 ref_clock = i915->display.dpll.ref_clks.nssc; in icl_ddi_mg_pll_get_freq()
3112 if (DISPLAY_VER(i915) >= 12) { in icl_ddi_mg_pll_get_freq()
3217 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in icl_compute_combo_phy_dpll() local
3234 icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state); in icl_compute_combo_phy_dpll()
3239 crtc_state->port_clock = icl_ddi_combo_pll_get_freq(i915, NULL, in icl_compute_combo_phy_dpll()
3249 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in icl_get_combo_phy_dpll() local
3257 if (IS_ALDERLAKE_S(i915)) { in icl_get_combo_phy_dpll()
3263 } else if (IS_DG1(i915)) { in icl_get_combo_phy_dpll()
3273 } else if (IS_ROCKETLAKE(i915)) { in icl_get_combo_phy_dpll()
3278 } else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && in icl_get_combo_phy_dpll()
3289 dpll_mask &= ~intel_hti_dpll_mask(i915); in icl_get_combo_phy_dpll()
3308 struct drm_i915_private *i915 = to_i915(state->base.dev); in icl_compute_tc_phy_dplls() local
3321 icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state); in icl_compute_tc_phy_dplls()
3331 crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL, in icl_compute_tc_phy_dplls()
3341 struct drm_i915_private *i915 = to_i915(state->base.dev); in icl_get_tc_phy_dplls() local
3360 dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(i915, in icl_get_tc_phy_dplls()
3387 struct drm_i915_private *i915 = to_i915(state->base.dev); in icl_compute_dplls() local
3388 enum phy phy = intel_port_to_phy(i915, encoder->port); in icl_compute_dplls()
3390 if (intel_phy_is_combo(i915, phy)) in icl_compute_dplls()
3392 else if (intel_phy_is_tc(i915, phy)) in icl_compute_dplls()
3404 struct drm_i915_private *i915 = to_i915(state->base.dev); in icl_get_dplls() local
3405 enum phy phy = intel_port_to_phy(i915, encoder->port); in icl_get_dplls()
3407 if (intel_phy_is_combo(i915, phy)) in icl_get_dplls()
3409 else if (intel_phy_is_tc(i915, phy)) in icl_get_dplls()
3443 static bool mg_pll_get_hw_state(struct drm_i915_private *i915, in mg_pll_get_hw_state() argument
3453 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); in mg_pll_get_hw_state()
3455 wakeref = intel_display_power_get_if_enabled(i915, in mg_pll_get_hw_state()
3460 val = intel_de_read(i915, enable_reg); in mg_pll_get_hw_state()
3464 hw_state->mg_refclkin_ctl = intel_de_read(i915, in mg_pll_get_hw_state()
3469 intel_de_read(i915, MG_CLKTOP2_CORECLKCTL1(tc_port)); in mg_pll_get_hw_state()
3474 intel_de_read(i915, MG_CLKTOP2_HSCLKCTL(tc_port)); in mg_pll_get_hw_state()
3481 hw_state->mg_pll_div0 = intel_de_read(i915, MG_PLL_DIV0(tc_port)); in mg_pll_get_hw_state()
3482 hw_state->mg_pll_div1 = intel_de_read(i915, MG_PLL_DIV1(tc_port)); in mg_pll_get_hw_state()
3483 hw_state->mg_pll_lf = intel_de_read(i915, MG_PLL_LF(tc_port)); in mg_pll_get_hw_state()
3484 hw_state->mg_pll_frac_lock = intel_de_read(i915, in mg_pll_get_hw_state()
3486 hw_state->mg_pll_ssc = intel_de_read(i915, MG_PLL_SSC(tc_port)); in mg_pll_get_hw_state()
3488 hw_state->mg_pll_bias = intel_de_read(i915, MG_PLL_BIAS(tc_port)); in mg_pll_get_hw_state()
3490 intel_de_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port)); in mg_pll_get_hw_state()
3492 if (i915->display.dpll.ref_clks.nssc == 38400) { in mg_pll_get_hw_state()
3505 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in mg_pll_get_hw_state()
3509 static bool dkl_pll_get_hw_state(struct drm_i915_private *i915, in dkl_pll_get_hw_state() argument
3519 wakeref = intel_display_power_get_if_enabled(i915, in dkl_pll_get_hw_state()
3524 val = intel_de_read(i915, intel_tc_pll_enable_reg(i915, pll)); in dkl_pll_get_hw_state()
3532 hw_state->mg_refclkin_ctl = intel_dkl_phy_read(i915, in dkl_pll_get_hw_state()
3537 intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port)); in dkl_pll_get_hw_state()
3545 intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port)); in dkl_pll_get_hw_state()
3549 hw_state->mg_pll_div0 = intel_dkl_phy_read(i915, DKL_PLL_DIV0(tc_port)); in dkl_pll_get_hw_state()
3551 if (i915->display.vbt.override_afc_startup) in dkl_pll_get_hw_state()
3555 hw_state->mg_pll_div1 = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port)); in dkl_pll_get_hw_state()
3559 hw_state->mg_pll_ssc = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port)); in dkl_pll_get_hw_state()
3565 hw_state->mg_pll_bias = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port)); in dkl_pll_get_hw_state()
3570 intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); in dkl_pll_get_hw_state()
3576 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in dkl_pll_get_hw_state()
3580 static bool icl_pll_get_hw_state(struct drm_i915_private *i915, in icl_pll_get_hw_state() argument
3590 wakeref = intel_display_power_get_if_enabled(i915, in icl_pll_get_hw_state()
3595 val = intel_de_read(i915, enable_reg); in icl_pll_get_hw_state()
3599 if (IS_ALDERLAKE_S(i915)) { in icl_pll_get_hw_state()
3600 hw_state->cfgcr0 = intel_de_read(i915, ADLS_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3601 hw_state->cfgcr1 = intel_de_read(i915, ADLS_DPLL_CFGCR1(id)); in icl_pll_get_hw_state()
3602 } else if (IS_DG1(i915)) { in icl_pll_get_hw_state()
3603 hw_state->cfgcr0 = intel_de_read(i915, DG1_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3604 hw_state->cfgcr1 = intel_de_read(i915, DG1_DPLL_CFGCR1(id)); in icl_pll_get_hw_state()
3605 } else if (IS_ROCKETLAKE(i915)) { in icl_pll_get_hw_state()
3606 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3608 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3610 } else if (DISPLAY_VER(i915) >= 12) { in icl_pll_get_hw_state()
3611 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3613 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3615 if (i915->display.vbt.override_afc_startup) { in icl_pll_get_hw_state()
3616 hw_state->div0 = intel_de_read(i915, TGL_DPLL0_DIV0(id)); in icl_pll_get_hw_state()
3620 if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && in icl_pll_get_hw_state()
3622 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3624 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3627 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3629 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3636 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in icl_pll_get_hw_state()
3640 static bool combo_pll_get_hw_state(struct drm_i915_private *i915, in combo_pll_get_hw_state() argument
3644 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); in combo_pll_get_hw_state()
3646 return icl_pll_get_hw_state(i915, pll, hw_state, enable_reg); in combo_pll_get_hw_state()
3649 static bool tbt_pll_get_hw_state(struct drm_i915_private *i915, in tbt_pll_get_hw_state() argument
3653 return icl_pll_get_hw_state(i915, pll, hw_state, TBT_PLL_ENABLE); in tbt_pll_get_hw_state()
3656 static void icl_dpll_write(struct drm_i915_private *i915, in icl_dpll_write() argument
3663 if (IS_ALDERLAKE_S(i915)) { in icl_dpll_write()
3666 } else if (IS_DG1(i915)) { in icl_dpll_write()
3669 } else if (IS_ROCKETLAKE(i915)) { in icl_dpll_write()
3672 } else if (DISPLAY_VER(i915) >= 12) { in icl_dpll_write()
3677 if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && in icl_dpll_write()
3687 intel_de_write(i915, cfgcr0_reg, hw_state->cfgcr0); in icl_dpll_write()
3688 intel_de_write(i915, cfgcr1_reg, hw_state->cfgcr1); in icl_dpll_write()
3689 drm_WARN_ON_ONCE(&i915->drm, i915->display.vbt.override_afc_startup && in icl_dpll_write()
3691 if (i915->display.vbt.override_afc_startup && in icl_dpll_write()
3693 intel_de_rmw(i915, div0_reg, in icl_dpll_write()
3695 intel_de_posting_read(i915, cfgcr1_reg); in icl_dpll_write()
3698 static void icl_mg_pll_write(struct drm_i915_private *i915, in icl_mg_pll_write() argument
3710 intel_de_rmw(i915, MG_REFCLKIN_CTL(tc_port), in icl_mg_pll_write()
3713 intel_de_rmw(i915, MG_CLKTOP2_CORECLKCTL1(tc_port), in icl_mg_pll_write()
3717 intel_de_rmw(i915, MG_CLKTOP2_HSCLKCTL(tc_port), in icl_mg_pll_write()
3724 intel_de_write(i915, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); in icl_mg_pll_write()
3725 intel_de_write(i915, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); in icl_mg_pll_write()
3726 intel_de_write(i915, MG_PLL_LF(tc_port), hw_state->mg_pll_lf); in icl_mg_pll_write()
3727 intel_de_write(i915, MG_PLL_FRAC_LOCK(tc_port), in icl_mg_pll_write()
3729 intel_de_write(i915, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); in icl_mg_pll_write()
3731 intel_de_rmw(i915, MG_PLL_BIAS(tc_port), in icl_mg_pll_write()
3734 intel_de_rmw(i915, MG_PLL_TDC_COLDST_BIAS(tc_port), in icl_mg_pll_write()
3738 intel_de_posting_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port)); in icl_mg_pll_write()
3741 static void dkl_pll_write(struct drm_i915_private *i915, in dkl_pll_write() argument
3753 val = intel_dkl_phy_read(i915, DKL_REFCLKIN_CTL(tc_port)); in dkl_pll_write()
3756 intel_dkl_phy_write(i915, DKL_REFCLKIN_CTL(tc_port), val); in dkl_pll_write()
3758 val = intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port)); in dkl_pll_write()
3761 intel_dkl_phy_write(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port), val); in dkl_pll_write()
3763 val = intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port)); in dkl_pll_write()
3769 intel_dkl_phy_write(i915, DKL_CLKTOP2_HSCLKCTL(tc_port), val); in dkl_pll_write()
3772 if (i915->display.vbt.override_afc_startup) in dkl_pll_write()
3774 intel_dkl_phy_rmw(i915, DKL_PLL_DIV0(tc_port), val, in dkl_pll_write()
3777 val = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port)); in dkl_pll_write()
3781 intel_dkl_phy_write(i915, DKL_PLL_DIV1(tc_port), val); in dkl_pll_write()
3783 val = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port)); in dkl_pll_write()
3789 intel_dkl_phy_write(i915, DKL_PLL_SSC(tc_port), val); in dkl_pll_write()
3791 val = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port)); in dkl_pll_write()
3795 intel_dkl_phy_write(i915, DKL_PLL_BIAS(tc_port), val); in dkl_pll_write()
3797 val = intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); in dkl_pll_write()
3801 intel_dkl_phy_write(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port), val); in dkl_pll_write()
3803 intel_dkl_phy_posting_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); in dkl_pll_write()
3806 static void icl_pll_power_enable(struct drm_i915_private *i915, in icl_pll_power_enable() argument
3810 intel_de_rmw(i915, enable_reg, 0, PLL_POWER_ENABLE); in icl_pll_power_enable()
3816 if (intel_de_wait_for_set(i915, enable_reg, PLL_POWER_STATE, 1)) in icl_pll_power_enable()
3817 drm_err(&i915->drm, "PLL %d Power not enabled\n", in icl_pll_power_enable()
3821 static void icl_pll_enable(struct drm_i915_private *i915, in icl_pll_enable() argument
3825 intel_de_rmw(i915, enable_reg, 0, PLL_ENABLE); in icl_pll_enable()
3828 if (intel_de_wait_for_set(i915, enable_reg, PLL_LOCK, 1)) in icl_pll_enable()
3829 drm_err(&i915->drm, "PLL %d not locked\n", pll->info->id); in icl_pll_enable()
3832 static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll) in adlp_cmtg_clock_gating_wa() argument
3836 if (!(IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) || in adlp_cmtg_clock_gating_wa()
3850 val = intel_de_read(i915, TRANS_CMTG_CHICKEN); in adlp_cmtg_clock_gating_wa()
3851 val = intel_de_rmw(i915, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING); in adlp_cmtg_clock_gating_wa()
3852 if (drm_WARN_ON(&i915->drm, val & ~DISABLE_DPT_CLK_GATING)) in adlp_cmtg_clock_gating_wa()
3853 drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val); in adlp_cmtg_clock_gating_wa()
3856 static void combo_pll_enable(struct drm_i915_private *i915, in combo_pll_enable() argument
3859 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); in combo_pll_enable()
3861 icl_pll_power_enable(i915, pll, enable_reg); in combo_pll_enable()
3863 icl_dpll_write(i915, pll); in combo_pll_enable()
3871 icl_pll_enable(i915, pll, enable_reg); in combo_pll_enable()
3873 adlp_cmtg_clock_gating_wa(i915, pll); in combo_pll_enable()
3878 static void tbt_pll_enable(struct drm_i915_private *i915, in tbt_pll_enable() argument
3881 icl_pll_power_enable(i915, pll, TBT_PLL_ENABLE); in tbt_pll_enable()
3883 icl_dpll_write(i915, pll); in tbt_pll_enable()
3891 icl_pll_enable(i915, pll, TBT_PLL_ENABLE); in tbt_pll_enable()
3896 static void mg_pll_enable(struct drm_i915_private *i915, in mg_pll_enable() argument
3899 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); in mg_pll_enable()
3901 icl_pll_power_enable(i915, pll, enable_reg); in mg_pll_enable()
3903 if (DISPLAY_VER(i915) >= 12) in mg_pll_enable()
3904 dkl_pll_write(i915, pll); in mg_pll_enable()
3906 icl_mg_pll_write(i915, pll); in mg_pll_enable()
3914 icl_pll_enable(i915, pll, enable_reg); in mg_pll_enable()
3919 static void icl_pll_disable(struct drm_i915_private *i915, in icl_pll_disable() argument
3931 intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0); in icl_pll_disable()
3934 if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 1)) in icl_pll_disable()
3935 drm_err(&i915->drm, "PLL %d locked\n", pll->info->id); in icl_pll_disable()
3939 intel_de_rmw(i915, enable_reg, PLL_POWER_ENABLE, 0); in icl_pll_disable()
3945 if (intel_de_wait_for_clear(i915, enable_reg, PLL_POWER_STATE, 1)) in icl_pll_disable()
3946 drm_err(&i915->drm, "PLL %d Power not disabled\n", in icl_pll_disable()
3950 static void combo_pll_disable(struct drm_i915_private *i915, in combo_pll_disable() argument
3953 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); in combo_pll_disable()
3955 icl_pll_disable(i915, pll, enable_reg); in combo_pll_disable()
3958 static void tbt_pll_disable(struct drm_i915_private *i915, in tbt_pll_disable() argument
3961 icl_pll_disable(i915, pll, TBT_PLL_ENABLE); in tbt_pll_disable()
3964 static void mg_pll_disable(struct drm_i915_private *i915, in mg_pll_disable() argument
3967 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); in mg_pll_disable()
3969 icl_pll_disable(i915, pll, enable_reg); in mg_pll_disable()
3972 static void icl_update_dpll_ref_clks(struct drm_i915_private *i915) in icl_update_dpll_ref_clks() argument
3975 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in icl_update_dpll_ref_clks()
3978 static void icl_dump_hw_state(struct drm_i915_private *i915, in icl_dump_hw_state() argument
3981 drm_dbg_kms(&i915->drm, in icl_dump_hw_state()
4164 * @i915: i915 device
4166 * Initialize shared DPLLs for @i915.
4168 void intel_shared_dpll_init(struct drm_i915_private *i915) in intel_shared_dpll_init() argument
4174 mutex_init(&i915->display.dpll.lock); in intel_shared_dpll_init()
4176 if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915)) in intel_shared_dpll_init()
4179 else if (IS_ALDERLAKE_P(i915)) in intel_shared_dpll_init()
4181 else if (IS_ALDERLAKE_S(i915)) in intel_shared_dpll_init()
4183 else if (IS_DG1(i915)) in intel_shared_dpll_init()
4185 else if (IS_ROCKETLAKE(i915)) in intel_shared_dpll_init()
4187 else if (DISPLAY_VER(i915) >= 12) in intel_shared_dpll_init()
4189 else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) in intel_shared_dpll_init()
4191 else if (DISPLAY_VER(i915) >= 11) in intel_shared_dpll_init()
4193 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) in intel_shared_dpll_init()
4195 else if (DISPLAY_VER(i915) == 9) in intel_shared_dpll_init()
4197 else if (HAS_DDI(i915)) in intel_shared_dpll_init()
4199 else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915)) in intel_shared_dpll_init()
4208 if (drm_WARN_ON(&i915->drm, in intel_shared_dpll_init()
4209 i >= ARRAY_SIZE(i915->display.dpll.shared_dplls))) in intel_shared_dpll_init()
4213 if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32)) in intel_shared_dpll_init()
4216 i915->display.dpll.shared_dplls[i].info = &dpll_info[i]; in intel_shared_dpll_init()
4217 i915->display.dpll.shared_dplls[i].index = i; in intel_shared_dpll_init()
4220 i915->display.dpll.mgr = dpll_mgr; in intel_shared_dpll_init()
4221 i915->display.dpll.num_shared_dpll = i; in intel_shared_dpll_init()
4242 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_compute_shared_dplls() local
4243 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_compute_shared_dplls()
4245 if (drm_WARN_ON(&i915->drm, !dpll_mgr)) in intel_compute_shared_dplls()
4275 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_reserve_shared_dplls() local
4276 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_reserve_shared_dplls()
4278 if (drm_WARN_ON(&i915->drm, !dpll_mgr)) in intel_reserve_shared_dplls()
4298 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_release_shared_dplls() local
4299 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_release_shared_dplls()
4327 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_update_active_dpll() local
4328 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_update_active_dpll()
4330 if (drm_WARN_ON(&i915->drm, !dpll_mgr)) in intel_update_active_dpll()
4338 * @i915: i915 device
4344 int intel_dpll_get_freq(struct drm_i915_private *i915, in intel_dpll_get_freq() argument
4348 if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq)) in intel_dpll_get_freq()
4351 return pll->info->funcs->get_freq(i915, pll, pll_state); in intel_dpll_get_freq()
4356 * @i915: i915 device
4362 bool intel_dpll_get_hw_state(struct drm_i915_private *i915, in intel_dpll_get_hw_state() argument
4366 return pll->info->funcs->get_hw_state(i915, pll, hw_state); in intel_dpll_get_hw_state()
4369 static void readout_dpll_hw_state(struct drm_i915_private *i915, in readout_dpll_hw_state() argument
4374 pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state); in readout_dpll_hw_state()
4377 pll->wakeref = intel_display_power_get(i915, pll->info->power_domain); in readout_dpll_hw_state()
4380 for_each_intel_crtc(&i915->drm, crtc) { in readout_dpll_hw_state()
4389 drm_dbg_kms(&i915->drm, in readout_dpll_hw_state()
4394 void intel_dpll_update_ref_clks(struct drm_i915_private *i915) in intel_dpll_update_ref_clks() argument
4396 if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks) in intel_dpll_update_ref_clks()
4397 i915->display.dpll.mgr->update_ref_clks(i915); in intel_dpll_update_ref_clks()
4400 void intel_dpll_readout_hw_state(struct drm_i915_private *i915) in intel_dpll_readout_hw_state() argument
4405 for_each_shared_dpll(i915, pll, i) in intel_dpll_readout_hw_state()
4406 readout_dpll_hw_state(i915, pll); in intel_dpll_readout_hw_state()
4409 static void sanitize_dpll_state(struct drm_i915_private *i915, in sanitize_dpll_state() argument
4415 adlp_cmtg_clock_gating_wa(i915, pll); in sanitize_dpll_state()
4420 drm_dbg_kms(&i915->drm, in sanitize_dpll_state()
4424 _intel_disable_shared_dpll(i915, pll); in sanitize_dpll_state()
4427 void intel_dpll_sanitize_state(struct drm_i915_private *i915) in intel_dpll_sanitize_state() argument
4432 for_each_shared_dpll(i915, pll, i) in intel_dpll_sanitize_state()
4433 sanitize_dpll_state(i915, pll); in intel_dpll_sanitize_state()
4438 * @i915: i915 drm device
4443 void intel_dpll_dump_hw_state(struct drm_i915_private *i915, in intel_dpll_dump_hw_state() argument
4446 if (i915->display.dpll.mgr) { in intel_dpll_dump_hw_state()
4447 i915->display.dpll.mgr->dump_hw_state(i915, hw_state); in intel_dpll_dump_hw_state()
4452 drm_dbg_kms(&i915->drm, in intel_dpll_dump_hw_state()
4463 verify_single_dpll_state(struct drm_i915_private *i915, in verify_single_dpll_state() argument
4474 drm_dbg_kms(&i915->drm, "%s\n", pll->info->name); in verify_single_dpll_state()
4476 active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state); in verify_single_dpll_state()
4479 I915_STATE_WARN(i915, !pll->on && pll->active_mask, in verify_single_dpll_state()
4481 I915_STATE_WARN(i915, pll->on && !pll->active_mask, in verify_single_dpll_state()
4483 I915_STATE_WARN(i915, pll->on != active, in verify_single_dpll_state()
4489 I915_STATE_WARN(i915, in verify_single_dpll_state()
4500 I915_STATE_WARN(i915, !(pll->active_mask & pipe_mask), in verify_single_dpll_state()
4504 I915_STATE_WARN(i915, pll->active_mask & pipe_mask, in verify_single_dpll_state()
4508 I915_STATE_WARN(i915, !(pll->state.pipe_mask & pipe_mask), in verify_single_dpll_state()
4512 I915_STATE_WARN(i915, in verify_single_dpll_state()
4521 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_shared_dpll_state_verify() local
4528 verify_single_dpll_state(i915, new_crtc_state->shared_dpll, in intel_shared_dpll_state_verify()
4536 I915_STATE_WARN(i915, pll->active_mask & pipe_mask, in intel_shared_dpll_state_verify()
4539 I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask, in intel_shared_dpll_state_verify()
4547 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_shared_dpll_verify_disabled() local
4551 for_each_shared_dpll(i915, pll, i) in intel_shared_dpll_verify_disabled()
4552 verify_single_dpll_state(i915, pll, NULL, NULL); in intel_shared_dpll_verify_disabled()