236 /* LVDS 100mhz refclk limits. */
315 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)  in pnv_calc_dpll_params()  argument
321 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);  in pnv_calc_dpll_params()
333 int i9xx_calc_dpll_params(int refclk, struct dpll *clock)  in i9xx_calc_dpll_params()  argument
339 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);  in i9xx_calc_dpll_params()
346 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)  in vlv_calc_dpll_params()  argument
352 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);  in vlv_calc_dpll_params()
359 int chv_calc_dpll_params(int refclk, struct dpll *clock)  in chv_calc_dpll_params()  argument
365 		DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22);  in chv_calc_dpll_params()
398 	int refclk = i9xx_pll_refclk(dev, pipe_config);  in i9xx_crtc_clock_get()  local
439 			port_clock = pnv_calc_dpll_params(refclk, &clock);  in i9xx_crtc_clock_get()
441 			port_clock = i9xx_calc_dpll_params(refclk, &clock);  in i9xx_crtc_clock_get()
470 		port_clock = i9xx_calc_dpll_params(refclk, &clock);  in i9xx_crtc_clock_get()
489 	int refclk = 100000;  in vlv_crtc_clock_get()  local
505 	pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);  in vlv_crtc_clock_get()
517 	int refclk = 100000;  in chv_crtc_clock_get()  local
539 	pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);  in chv_crtc_clock_get()
543  * Returns whether the given set of divisors are valid for a given refclk with
608  * refclk, or FALSE.
618 		    int target, int refclk,  in i9xx_find_best_dpll()  argument
642 					i9xx_calc_dpll_params(refclk, &clock);  in i9xx_find_best_dpll()
666  * refclk, or FALSE.
676 		   int target, int refclk,  in pnv_find_best_dpll()  argument
698 					pnv_calc_dpll_params(refclk, &clock);  in pnv_find_best_dpll()
722  * refclk, or FALSE.
732 		   int target, int refclk,  in g4x_find_best_dpll()  argument
759 					i9xx_calc_dpll_params(refclk, &clock);  in g4x_find_best_dpll()
821  * refclk, or FALSE.
826 		   int target, int refclk,  in vlv_find_best_dpll()  argument
835 	int max_n = min(limit->n.max, refclk / 19200);  in vlv_find_best_dpll()
851 								     refclk * clock.m1);  in vlv_find_best_dpll()
853 					vlv_calc_dpll_params(refclk, &clock);  in vlv_find_best_dpll()
879  * refclk, or FALSE.
884 		   int target, int refclk,  in chv_find_best_dpll()  argument
900 	 * set to 2.  If requires to support 200Mhz refclk, we need to  in chv_find_best_dpll()
915 						   refclk * clock.m1);  in chv_find_best_dpll()
922 			chv_calc_dpll_params(refclk, &clock);  in chv_find_best_dpll()
944 	int refclk = 100000;  in bxt_find_best_dpll()  local
947 				  crtc_state->port_clock, refclk,  in bxt_find_best_dpll()
1317 	int refclk = 120000;  in ilk_crtc_compute_clock()  local
1329 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in ilk_crtc_compute_clock()
1333 			if (refclk == 100000)  in ilk_crtc_compute_clock()
1338 			if (refclk == 100000)  in ilk_crtc_compute_clock()
1349 				refclk, NULL, &crtc_state->dpll))  in ilk_crtc_compute_clock()
1352 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);  in ilk_crtc_compute_clock()
1421 	int refclk = 100000;  in chv_crtc_compute_clock()  local
1425 				refclk, NULL, &crtc_state->dpll))  in chv_crtc_compute_clock()
1428 	chv_calc_dpll_params(refclk, &crtc_state->dpll);  in chv_crtc_compute_clock()
1448 	int refclk = 100000;  in vlv_crtc_compute_clock()  local
1452 				refclk, NULL, &crtc_state->dpll))  in vlv_crtc_compute_clock()
1455 	vlv_calc_dpll_params(refclk, &crtc_state->dpll);  in vlv_crtc_compute_clock()
1476 	int refclk = 96000;  in g4x_crtc_compute_clock()  local
1480 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in g4x_crtc_compute_clock()
1483 				    refclk);  in g4x_crtc_compute_clock()
1502 				refclk, NULL, &crtc_state->dpll))  in g4x_crtc_compute_clock()
1505 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);  in g4x_crtc_compute_clock()
1525 	int refclk = 96000;  in pnv_crtc_compute_clock()  local
1529 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in pnv_crtc_compute_clock()
1532 				    refclk);  in pnv_crtc_compute_clock()
1542 				refclk, NULL, &crtc_state->dpll))  in pnv_crtc_compute_clock()
1545 	pnv_calc_dpll_params(refclk, &crtc_state->dpll);  in pnv_crtc_compute_clock()
1563 	int refclk = 96000;  in i9xx_crtc_compute_clock()  local
1567 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in i9xx_crtc_compute_clock()
1570 				    refclk);  in i9xx_crtc_compute_clock()
1580 				 refclk, NULL, &crtc_state->dpll))  in i9xx_crtc_compute_clock()
1583 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);  in i9xx_crtc_compute_clock()
1603 	int refclk = 48000;  in i8xx_crtc_compute_clock()  local
1607 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in i8xx_crtc_compute_clock()
1610 				    refclk);  in i8xx_crtc_compute_clock()
1622 				 refclk, NULL, &crtc_state->dpll))  in i8xx_crtc_compute_clock()
1625 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);  in i8xx_crtc_compute_clock()
1958 	/* Enable Refclk */  in vlv_enable_pll()
2005 	/* Feedback refclk divider - n and m1 */  in chv_prepare_pll()
2110 	/* Enable Refclk and SSC */  in chv_enable_pll()