1 // SPDX-License-Identifier: MIT
195  * the range value for them is (actual_value - 2).
265 	  * These are based on the data rate limits (measured in fast clocks)
281 	 * These are based on the data rate limits (measured in fast clocks)
307  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
308  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
312  * divided-down version of it.
317 	clock->m = clock->m2 + 2;  in pnv_calc_dpll_params()
318 	clock->p = clock->p1 * clock->p2;  in pnv_calc_dpll_params()
320 	clock->vco = clock->n == 0 ? 0 :  in pnv_calc_dpll_params()
321 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);  in pnv_calc_dpll_params()
322 	clock->dot = clock->p == 0 ? 0 :  in pnv_calc_dpll_params()
323 		DIV_ROUND_CLOSEST(clock->vco, clock->p);  in pnv_calc_dpll_params()
325 	return clock->dot;  in pnv_calc_dpll_params()
330 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);  in i9xx_dpll_compute_m()
335 	clock->m = i9xx_dpll_compute_m(clock);  in i9xx_calc_dpll_params()
336 	clock->p = clock->p1 * clock->p2;  in i9xx_calc_dpll_params()
338 	clock->vco = clock->n + 2 == 0 ? 0 :  in i9xx_calc_dpll_params()
339 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);  in i9xx_calc_dpll_params()
340 	clock->dot = clock->p == 0 ? 0 :  in i9xx_calc_dpll_params()
341 		DIV_ROUND_CLOSEST(clock->vco, clock->p);  in i9xx_calc_dpll_params()
343 	return clock->dot;  in i9xx_calc_dpll_params()
348 	clock->m = clock->m1 * clock->m2;  in vlv_calc_dpll_params()
349 	clock->p = clock->p1 * clock->p2 * 5;  in vlv_calc_dpll_params()
351 	clock->vco = clock->n == 0 ? 0 :  in vlv_calc_dpll_params()
352 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);  in vlv_calc_dpll_params()
353 	clock->dot = clock->p == 0 ? 0 :  in vlv_calc_dpll_params()
354 		DIV_ROUND_CLOSEST(clock->vco, clock->p);  in vlv_calc_dpll_params()
356 	return clock->dot;  in vlv_calc_dpll_params()
361 	clock->m = clock->m1 * clock->m2;  in chv_calc_dpll_params()
362 	clock->p = clock->p1 * clock->p2 * 5;  in chv_calc_dpll_params()
364 	clock->vco = clock->n == 0 ? 0 :  in chv_calc_dpll_params()
365 		DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22);  in chv_calc_dpll_params()
366 	clock->dot = clock->p == 0 ? 0 :  in chv_calc_dpll_params()
367 		DIV_ROUND_CLOSEST(clock->vco, clock->p);  in chv_calc_dpll_params()
369 	return clock->dot;  in chv_calc_dpll_params()
376 	u32 dpll = pipe_config->dpll_hw_state.dpll;  in i9xx_pll_refclk()
379 		return dev_priv->display.vbt.lvds_ssc_freq;  in i9xx_pll_refclk()
392 	struct drm_device *dev = crtc->base.dev;  in i9xx_crtc_clock_get()
394 	u32 dpll = pipe_config->dpll_hw_state.dpll;  in i9xx_crtc_clock_get()
401 		fp = pipe_config->dpll_hw_state.fp0;  in i9xx_crtc_clock_get()
403 		fp = pipe_config->dpll_hw_state.fp1;  in i9xx_crtc_clock_get()
407 		clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;  in i9xx_crtc_clock_get()
432 			drm_dbg_kms(&dev_priv->drm,  in i9xx_crtc_clock_get()
447 		    lvds_pipe == crtc->pipe) {  in i9xx_crtc_clock_get()
478 	pipe_config->port_clock = port_clock;  in i9xx_crtc_clock_get()
484 	struct drm_device *dev = crtc->base.dev;  in vlv_crtc_clock_get()
486 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);  in vlv_crtc_clock_get()
492 	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)  in vlv_crtc_clock_get()
496 	mdiv = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));  in vlv_crtc_clock_get()
505 	pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);  in vlv_crtc_clock_get()
511 	struct drm_device *dev = crtc->base.dev;  in chv_crtc_clock_get()
513 	enum dpio_channel port = vlv_pipe_to_channel(crtc->pipe);  in chv_crtc_clock_get()
514 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);  in chv_crtc_clock_get()
520 	if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)  in chv_crtc_clock_get()
539 	pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);  in chv_crtc_clock_get()
550 	if (clock->n < limit->n.min || limit->n.max < clock->n)  in intel_pll_is_valid()
552 	if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)  in intel_pll_is_valid()
554 	if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)  in intel_pll_is_valid()
556 	if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)  in intel_pll_is_valid()
560 		if (clock->m1 <= clock->m2)  in intel_pll_is_valid()
564 		if (clock->p < limit->p.min || limit->p.max < clock->p)  in intel_pll_is_valid()
566 		if (clock->m < limit->m.min || limit->m.max < clock->m)  in intel_pll_is_valid()
570 	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)  in intel_pll_is_valid()
575 	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)  in intel_pll_is_valid()
586 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in i9xx_select_p2_div()
590 		 * For LVDS just rely on its current settings for dual-channel.  in i9xx_select_p2_div()
595 			return limit->p2.p2_fast;  in i9xx_select_p2_div()
597 			return limit->p2.p2_slow;  in i9xx_select_p2_div()
599 		if (target < limit->p2.dot_limit)  in i9xx_select_p2_div()
600 			return limit->p2.p2_slow;  in i9xx_select_p2_div()
602 			return limit->p2.p2_fast;  in i9xx_select_p2_div()
610  * Target and reference clocks are specified in kHz.
622 	struct drm_device *dev = crtc_state->uapi.crtc->dev;  in i9xx_find_best_dpll()
630 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;  in i9xx_find_best_dpll()
632 		for (clock.m2 = limit->m2.min;  in i9xx_find_best_dpll()
633 		     clock.m2 <= limit->m2.max; clock.m2++) {  in i9xx_find_best_dpll()
636 			for (clock.n = limit->n.min;  in i9xx_find_best_dpll()
637 			     clock.n <= limit->n.max; clock.n++) {  in i9xx_find_best_dpll()
638 				for (clock.p1 = limit->p1.min;  in i9xx_find_best_dpll()
639 					clock.p1 <= limit->p1.max; clock.p1++) {  in i9xx_find_best_dpll()
648 					    clock.p != match_clock->p)  in i9xx_find_best_dpll()
651 					this_err = abs(clock.dot - target);  in i9xx_find_best_dpll()
668  * Target and reference clocks are specified in kHz.
680 	struct drm_device *dev = crtc_state->uapi.crtc->dev;  in pnv_find_best_dpll()
688 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;  in pnv_find_best_dpll()
690 		for (clock.m2 = limit->m2.min;  in pnv_find_best_dpll()
691 		     clock.m2 <= limit->m2.max; clock.m2++) {  in pnv_find_best_dpll()
692 			for (clock.n = limit->n.min;  in pnv_find_best_dpll()
693 			     clock.n <= limit->n.max; clock.n++) {  in pnv_find_best_dpll()
694 				for (clock.p1 = limit->p1.min;  in pnv_find_best_dpll()
695 					clock.p1 <= limit->p1.max; clock.p1++) {  in pnv_find_best_dpll()
704 					    clock.p != match_clock->p)  in pnv_find_best_dpll()
707 					this_err = abs(clock.dot - target);  in pnv_find_best_dpll()
724  * Target and reference clocks are specified in kHz.
736 	struct drm_device *dev = crtc_state->uapi.crtc->dev;  in g4x_find_best_dpll()
747 	max_n = limit->n.max;  in g4x_find_best_dpll()
749 	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {  in g4x_find_best_dpll()
751 		for (clock.m1 = limit->m1.max;  in g4x_find_best_dpll()
752 		     clock.m1 >= limit->m1.min; clock.m1--) {  in g4x_find_best_dpll()
753 			for (clock.m2 = limit->m2.max;  in g4x_find_best_dpll()
754 			     clock.m2 >= limit->m2.min; clock.m2--) {  in g4x_find_best_dpll()
755 				for (clock.p1 = limit->p1.max;  in g4x_find_best_dpll()
756 				     clock.p1 >= limit->p1.min; clock.p1--) {  in g4x_find_best_dpll()
765 					this_err = abs(clock.dot - target);  in g4x_find_best_dpll()
796 		return calculated_clock->p > best_clock->p;  in vlv_PLL_is_optimal()
803 				abs(target_freq - calculated_clock->dot),  in vlv_PLL_is_optimal()
810 	if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {  in vlv_PLL_is_optimal()
830 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in vlv_find_best_dpll()
831 	struct drm_device *dev = crtc->base.dev;  in vlv_find_best_dpll()
835 	int max_n = min(limit->n.max, refclk / 19200);  in vlv_find_best_dpll()
841 	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {  in vlv_find_best_dpll()
842 		for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {  in vlv_find_best_dpll()
843 			for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;  in vlv_find_best_dpll()
844 			     clock.p2 -= clock.p2 > 10 ? 2 : 1) {  in vlv_find_best_dpll()
847 				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {  in vlv_find_best_dpll()
888 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in chv_find_best_dpll()
889 	struct drm_device *dev = crtc->base.dev;  in chv_find_best_dpll()
906 	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {  in chv_find_best_dpll()
907 		for (clock.p2 = limit->p2.p2_fast;  in chv_find_best_dpll()
908 				clock.p2 >= limit->p2.p2_slow;  in chv_find_best_dpll()
909 				clock.p2 -= clock.p2 > 10 ? 2 : 1) {  in chv_find_best_dpll()
947 				  crtc_state->port_clock, refclk,  in bxt_find_best_dpll()
953 	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;  in i9xx_dpll_compute_fp()
958 	return (1 << dpll->n) << 16 | dpll->m2;  in pnv_dpll_compute_fp()
965 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_update_pll_dividers()
966 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_update_pll_dividers()
977 	crtc_state->dpll_hw_state.fp0 = fp;  in i9xx_update_pll_dividers()
978 	crtc_state->dpll_hw_state.fp1 = fp2;  in i9xx_update_pll_dividers()
985 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_compute_dpll()
986 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_compute_dpll()
1000 		dpll |= (crtc_state->pixel_multiplier - 1)  in i9xx_compute_dpll()
1013 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;  in i9xx_compute_dpll()
1014 		dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;  in i9xx_compute_dpll()
1016 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;  in i9xx_compute_dpll()
1017 		WARN_ON(reduced_clock->p1 != clock->p1);  in i9xx_compute_dpll()
1019 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;  in i9xx_compute_dpll()
1020 		WARN_ON(reduced_clock->p1 != clock->p1);  in i9xx_compute_dpll()
1023 	switch (clock->p2) {  in i9xx_compute_dpll()
1037 	WARN_ON(reduced_clock->p2 != clock->p2);  in i9xx_compute_dpll()
1042 	if (crtc_state->sdvo_tv_clock)  in i9xx_compute_dpll()
1051 	crtc_state->dpll_hw_state.dpll = dpll;  in i9xx_compute_dpll()
1054 		u32 dpll_md = (crtc_state->pixel_multiplier - 1)  in i9xx_compute_dpll()
1056 		crtc_state->dpll_hw_state.dpll_md = dpll_md;  in i9xx_compute_dpll()
1064 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i8xx_compute_dpll()
1065 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i8xx_compute_dpll()
1073 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;  in i8xx_compute_dpll()
1075 		if (clock->p1 == 2)  in i8xx_compute_dpll()
1078 			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;  in i8xx_compute_dpll()
1079 		if (clock->p2 == 4)  in i8xx_compute_dpll()
1082 	WARN_ON(reduced_clock->p1 != clock->p1);  in i8xx_compute_dpll()
1083 	WARN_ON(reduced_clock->p2 != clock->p2);  in i8xx_compute_dpll()
1091 	 *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."  in i8xx_compute_dpll()
1108 	crtc_state->dpll_hw_state.dpll = dpll;  in i8xx_compute_dpll()
1114 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in hsw_crtc_compute_clock()
1134 	if (!crtc_state->has_pch_encoder)  in hsw_crtc_compute_clock()
1135 		crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);  in hsw_crtc_compute_clock()
1143 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in hsw_crtc_get_shared_dpll()
1169 	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);  in dg2_crtc_compute_clock()
1188 	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->cx0pll_state);  in mtl_crtc_compute_clock()
1190 	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);  in mtl_crtc_compute_clock()
1197 	return dpll->m < factor * dpll->n;  in ilk_needs_fb_cb_tune()
1204 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_update_pll_dividers()
1205 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_update_pll_dividers()
1213 		     dev_priv->display.vbt.lvds_ssc_freq == 100000) ||  in ilk_update_pll_dividers()
1217 	} else if (crtc_state->sdvo_tv_clock) {  in ilk_update_pll_dividers()
1229 	crtc_state->dpll_hw_state.fp0 = fp;  in ilk_update_pll_dividers()
1230 	crtc_state->dpll_hw_state.fp1 = fp2;  in ilk_update_pll_dividers()
1237 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_compute_dpll()
1238 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_compute_dpll()
1250 	dpll |= (crtc_state->pixel_multiplier - 1)  in ilk_compute_dpll()
1272 	 * this on ILK at all since it has a fixed DPLL<->pipe mapping.  in ilk_compute_dpll()
1279 	dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;  in ilk_compute_dpll()
1281 	dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;  in ilk_compute_dpll()
1283 	switch (clock->p2) {  in ilk_compute_dpll()
1297 	WARN_ON(reduced_clock->p2 != clock->p2);  in ilk_compute_dpll()
1307 	crtc_state->dpll_hw_state.dpll = dpll;  in ilk_compute_dpll()
1313 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in ilk_crtc_compute_clock()
1321 	if (!crtc_state->has_pch_encoder)  in ilk_crtc_compute_clock()
1326 			drm_dbg_kms(&dev_priv->drm,  in ilk_crtc_compute_clock()
1328 				    dev_priv->display.vbt.lvds_ssc_freq);  in ilk_crtc_compute_clock()
1329 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in ilk_crtc_compute_clock()
1347 	if (!crtc_state->clock_set &&  in ilk_crtc_compute_clock()
1348 	    !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,  in ilk_crtc_compute_clock()
1349 				refclk, NULL, &crtc_state->dpll))  in ilk_crtc_compute_clock()
1350 		return -EINVAL;  in ilk_crtc_compute_clock()
1352 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);  in ilk_crtc_compute_clock()
1354 	ilk_compute_dpll(crtc_state, &crtc_state->dpll,  in ilk_crtc_compute_clock()
1355 			 &crtc_state->dpll);  in ilk_crtc_compute_clock()
1361 	crtc_state->port_clock = crtc_state->dpll.dot;  in ilk_crtc_compute_clock()
1362 	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);  in ilk_crtc_compute_clock()
1374 	if (!crtc_state->has_pch_encoder)  in ilk_crtc_get_shared_dpll()
1382 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in vlv_compute_dpll()
1384 	crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |  in vlv_compute_dpll()
1386 	if (crtc->pipe != PIPE_A)  in vlv_compute_dpll()
1387 		crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;  in vlv_compute_dpll()
1391 		crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |  in vlv_compute_dpll()
1394 	crtc_state->dpll_hw_state.dpll_md =  in vlv_compute_dpll()
1395 		(crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;  in vlv_compute_dpll()
1400 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in chv_compute_dpll()
1402 	crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |  in chv_compute_dpll()
1404 	if (crtc->pipe != PIPE_A)  in chv_compute_dpll()
1405 		crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;  in chv_compute_dpll()
1409 		crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;  in chv_compute_dpll()
1411 	crtc_state->dpll_hw_state.dpll_md =  in chv_compute_dpll()
1412 		(crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;  in chv_compute_dpll()
1423 	if (!crtc_state->clock_set &&  in chv_crtc_compute_clock()
1424 	    !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,  in chv_crtc_compute_clock()
1425 				refclk, NULL, &crtc_state->dpll))  in chv_crtc_compute_clock()
1426 		return -EINVAL;  in chv_crtc_compute_clock()
1428 	chv_calc_dpll_params(refclk, &crtc_state->dpll);  in chv_crtc_compute_clock()
1436 	crtc_state->port_clock = crtc_state->dpll.dot;  in chv_crtc_compute_clock()
1437 	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);  in chv_crtc_compute_clock()
1450 	if (!crtc_state->clock_set &&  in vlv_crtc_compute_clock()
1451 	    !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,  in vlv_crtc_compute_clock()
1452 				refclk, NULL, &crtc_state->dpll))  in vlv_crtc_compute_clock()
1453 		return -EINVAL;  in vlv_crtc_compute_clock()
1455 	vlv_calc_dpll_params(refclk, &crtc_state->dpll);  in vlv_crtc_compute_clock()
1463 	crtc_state->port_clock = crtc_state->dpll.dot;  in vlv_crtc_compute_clock()
1464 	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);  in vlv_crtc_compute_clock()
1472 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in g4x_crtc_compute_clock()
1480 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in g4x_crtc_compute_clock()
1481 			drm_dbg_kms(&dev_priv->drm,  in g4x_crtc_compute_clock()
1500 	if (!crtc_state->clock_set &&  in g4x_crtc_compute_clock()
1501 	    !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,  in g4x_crtc_compute_clock()
1502 				refclk, NULL, &crtc_state->dpll))  in g4x_crtc_compute_clock()
1503 		return -EINVAL;  in g4x_crtc_compute_clock()
1505 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);  in g4x_crtc_compute_clock()
1507 	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,  in g4x_crtc_compute_clock()
1508 			  &crtc_state->dpll);  in g4x_crtc_compute_clock()
1510 	crtc_state->port_clock = crtc_state->dpll.dot;  in g4x_crtc_compute_clock()
1513 		crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);  in g4x_crtc_compute_clock()
1521 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in pnv_crtc_compute_clock()
1529 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in pnv_crtc_compute_clock()
1530 			drm_dbg_kms(&dev_priv->drm,  in pnv_crtc_compute_clock()
1540 	if (!crtc_state->clock_set &&  in pnv_crtc_compute_clock()
1541 	    !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,  in pnv_crtc_compute_clock()
1542 				refclk, NULL, &crtc_state->dpll))  in pnv_crtc_compute_clock()
1543 		return -EINVAL;  in pnv_crtc_compute_clock()
1545 	pnv_calc_dpll_params(refclk, &crtc_state->dpll);  in pnv_crtc_compute_clock()
1547 	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,  in pnv_crtc_compute_clock()
1548 			  &crtc_state->dpll);  in pnv_crtc_compute_clock()
1550 	crtc_state->port_clock = crtc_state->dpll.dot;  in pnv_crtc_compute_clock()
1551 	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);  in pnv_crtc_compute_clock()
1559 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in i9xx_crtc_compute_clock()
1567 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in i9xx_crtc_compute_clock()
1568 			drm_dbg_kms(&dev_priv->drm,  in i9xx_crtc_compute_clock()
1578 	if (!crtc_state->clock_set &&  in i9xx_crtc_compute_clock()
1579 	    !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,  in i9xx_crtc_compute_clock()
1580 				 refclk, NULL, &crtc_state->dpll))  in i9xx_crtc_compute_clock()
1581 		return -EINVAL;  in i9xx_crtc_compute_clock()
1583 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);  in i9xx_crtc_compute_clock()
1585 	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,  in i9xx_crtc_compute_clock()
1586 			  &crtc_state->dpll);  in i9xx_crtc_compute_clock()
1588 	crtc_state->port_clock = crtc_state->dpll.dot;  in i9xx_crtc_compute_clock()
1591 		crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);  in i9xx_crtc_compute_clock()
1599 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in i8xx_crtc_compute_clock()
1607 			refclk = dev_priv->display.vbt.lvds_ssc_freq;  in i8xx_crtc_compute_clock()
1608 			drm_dbg_kms(&dev_priv->drm,  in i8xx_crtc_compute_clock()
1620 	if (!crtc_state->clock_set &&  in i8xx_crtc_compute_clock()
1621 	    !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,  in i8xx_crtc_compute_clock()
1622 				 refclk, NULL, &crtc_state->dpll))  in i8xx_crtc_compute_clock()
1623 		return -EINVAL;  in i8xx_crtc_compute_clock()
1625 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);  in i8xx_crtc_compute_clock()
1627 	i8xx_compute_dpll(crtc_state, &crtc_state->dpll,  in i8xx_crtc_compute_clock()
1628 			  &crtc_state->dpll);  in i8xx_crtc_compute_clock()
1630 	crtc_state->port_clock = crtc_state->dpll.dot;  in i8xx_crtc_compute_clock()
1631 	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);  in i8xx_crtc_compute_clock()
1681 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_dpll_crtc_compute_clock()
1686 	drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));  in intel_dpll_crtc_compute_clock()
1688 	memset(&crtc_state->dpll_hw_state, 0,  in intel_dpll_crtc_compute_clock()
1689 	       sizeof(crtc_state->dpll_hw_state));  in intel_dpll_crtc_compute_clock()
1691 	if (!crtc_state->hw.enable)  in intel_dpll_crtc_compute_clock()
1694 	ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc);  in intel_dpll_crtc_compute_clock()
1696 		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",  in intel_dpll_crtc_compute_clock()
1697 			    crtc->base.base.id, crtc->base.name);  in intel_dpll_crtc_compute_clock()
1707 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_dpll_crtc_get_shared_dpll()
1712 	drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));  in intel_dpll_crtc_get_shared_dpll()
1713 	drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll);  in intel_dpll_crtc_get_shared_dpll()
1715 	if (!crtc_state->hw.enable || crtc_state->shared_dpll)  in intel_dpll_crtc_get_shared_dpll()
1718 	if (!i915->display.funcs.dpll->crtc_get_shared_dpll)  in intel_dpll_crtc_get_shared_dpll()
1721 	ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc);  in intel_dpll_crtc_get_shared_dpll()
1723 		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",  in intel_dpll_crtc_get_shared_dpll()
1724 			    crtc->base.base.id, crtc->base.name);  in intel_dpll_crtc_get_shared_dpll()
1735 		dev_priv->display.funcs.dpll = &mtl_dpll_funcs;  in intel_dpll_init_clock_hook()
1737 		dev_priv->display.funcs.dpll = &dg2_dpll_funcs;  in intel_dpll_init_clock_hook()
1739 		dev_priv->display.funcs.dpll = &hsw_dpll_funcs;  in intel_dpll_init_clock_hook()
1741 		dev_priv->display.funcs.dpll = &ilk_dpll_funcs;  in intel_dpll_init_clock_hook()
1743 		dev_priv->display.funcs.dpll = &chv_dpll_funcs;  in intel_dpll_init_clock_hook()
1745 		dev_priv->display.funcs.dpll = &vlv_dpll_funcs;  in intel_dpll_init_clock_hook()
1747 		dev_priv->display.funcs.dpll = &g4x_dpll_funcs;  in intel_dpll_init_clock_hook()
1749 		dev_priv->display.funcs.dpll = &pnv_dpll_funcs;  in intel_dpll_init_clock_hook()
1751 		dev_priv->display.funcs.dpll = &i9xx_dpll_funcs;  in intel_dpll_init_clock_hook()
1753 		dev_priv->display.funcs.dpll = &i8xx_dpll_funcs;  in intel_dpll_init_clock_hook()
1766 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_enable_pll()
1767 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_enable_pll()
1768 	u32 dpll = crtc_state->dpll_hw_state.dpll;  in i9xx_enable_pll()
1769 	enum pipe pipe = crtc->pipe;  in i9xx_enable_pll()
1772 	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);  in i9xx_enable_pll()
1774 	/* PLL is protected by panel, make sure we can write it */  in i9xx_enable_pll()
1778 	intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0);  in i9xx_enable_pll()
1779 	intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1);  in i9xx_enable_pll()
1789 	/* Wait for the clocks to stabilize. */  in i9xx_enable_pll()
1795 			       crtc_state->dpll_hw_state.dpll_md);  in i9xx_enable_pll()
1798 		 * DPLL is enabled and the clocks are stable.  in i9xx_enable_pll()
1844 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in vlv_prepare_pll()
1845 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in vlv_prepare_pll()
1846 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);  in vlv_prepare_pll()
1847 	enum pipe pipe = crtc->pipe;  in vlv_prepare_pll()
1854 	bestn = crtc_state->dpll.n;  in vlv_prepare_pll()
1855 	bestm1 = crtc_state->dpll.m1;  in vlv_prepare_pll()
1856 	bestm2 = crtc_state->dpll.m2;  in vlv_prepare_pll()
1857 	bestp1 = crtc_state->dpll.p1;  in vlv_prepare_pll()
1858 	bestp2 = crtc_state->dpll.p2;  in vlv_prepare_pll()
1895 	if (crtc_state->port_clock == 162000 ||  in vlv_prepare_pll()
1935 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in _vlv_enable_pll()
1936 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in _vlv_enable_pll()
1937 	enum pipe pipe = crtc->pipe;  in _vlv_enable_pll()
1939 	intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll);  in _vlv_enable_pll()
1944 		drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);  in _vlv_enable_pll()
1949 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in vlv_enable_pll()
1950 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in vlv_enable_pll()
1951 	enum pipe pipe = crtc->pipe;  in vlv_enable_pll()
1953 	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);  in vlv_enable_pll()
1955 	/* PLL is protected by panel, make sure we can write it */  in vlv_enable_pll()
1960 		       crtc_state->dpll_hw_state.dpll &  in vlv_enable_pll()
1963 	if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) {  in vlv_enable_pll()
1969 		       crtc_state->dpll_hw_state.dpll_md);  in vlv_enable_pll()
1975 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in chv_prepare_pll()
1976 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in chv_prepare_pll()
1977 	enum pipe pipe = crtc->pipe;  in chv_prepare_pll()
1979 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);  in chv_prepare_pll()
1985 	bestm2_frac = crtc_state->dpll.m2 & 0x3fffff;  in chv_prepare_pll()
1986 	bestm2 = crtc_state->dpll.m2 >> 22;  in chv_prepare_pll()
1987 	bestp1 = crtc_state->dpll.p1;  in chv_prepare_pll()
1988 	bestp2 = crtc_state->dpll.p2;  in chv_prepare_pll()
1989 	vco = crtc_state->dpll.vco;  in chv_prepare_pll()
2002 	/* Feedback post-divider - m2 */  in chv_prepare_pll()
2005 	/* Feedback refclk divider - n and m1 */  in chv_prepare_pll()
2070 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in _chv_enable_pll()
2071 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in _chv_enable_pll()
2072 	enum pipe pipe = crtc->pipe;  in _chv_enable_pll()
2074 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);  in _chv_enable_pll()
2092 	intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll);  in _chv_enable_pll()
2096 		drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);  in _chv_enable_pll()
2101 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in chv_enable_pll()
2102 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in chv_enable_pll()
2103 	enum pipe pipe = crtc->pipe;  in chv_enable_pll()
2105 	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);  in chv_enable_pll()
2107 	/* PLL is protected by panel, make sure we can write it */  in chv_enable_pll()
2112 		       crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);  in chv_enable_pll()
2114 	if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) {  in chv_enable_pll()
2128 			       crtc_state->dpll_hw_state.dpll_md);  in chv_enable_pll()
2130 		dev_priv->display.state.chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md;  in chv_enable_pll()
2136 		drm_WARN_ON(&dev_priv->drm,  in chv_enable_pll()
2141 			       crtc_state->dpll_hw_state.dpll_md);  in chv_enable_pll()
2147  * vlv_force_pll_on - forcibly enable just the PLL
2164 		return -ENOMEM;  in vlv_force_pll_on()
2166 	crtc_state->cpu_transcoder = (enum transcoder)pipe;  in vlv_force_pll_on()
2167 	crtc_state->pixel_multiplier = 1;  in vlv_force_pll_on()
2168 	crtc_state->dpll = *dpll;  in vlv_force_pll_on()
2169 	crtc_state->output_types = BIT(INTEL_OUTPUT_EDP);  in vlv_force_pll_on()
2179 	intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);  in vlv_force_pll_on()
2229 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_disable_pll()
2230 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_disable_pll()
2231 	enum pipe pipe = crtc->pipe;  in i9xx_disable_pll()
2238 	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);  in i9xx_disable_pll()
2246  * vlv_force_pll_off - forcibly disable just the PLL
2261 /* Only for pre-ILK configs */