35 	} dot, vco, n, m, m1, m2, p, p1;  member
47 	.m1 = { .min = 18, .max = 26 },
60 	.m1 = { .min = 18, .max = 26 },
73 	.m1 = { .min = 18, .max = 26 },
86 	.m1 = { .min = 8, .max = 18 },
99 	.m1 = { .min = 8, .max = 18 },
113 	.m1 = { .min = 17, .max = 23 },
128 	.m1 = { .min = 16, .max = 23 },
141 	.m1 = { .min = 17, .max = 23 },
155 	.m1 = { .min = 17, .max = 23 },
171 	.m1 = { .min = 0, .max = 0 },
184 	.m1 = { .min = 0, .max = 0 },
194  * We calculate clock using (register_value + 2) for N/M1/M2, so here
202 	.m1 = { .min = 12, .max = 22 },
215 	.m1 = { .min = 12, .max = 22 },
228 	.m1 = { .min = 12, .max = 22 },
242 	.m1 = { .min = 12, .max = 22 },
255 	.m1 = { .min = 12, .max = 22 },
273 	.m1 = { .min = 2, .max = 3 },
289 	.m1 = { .min = 2, .max = 2 },
299 	.m1 = { .min = 2, .max = 2 },
314 /* m1 is reserved as 0 in Pineview, n is a ring counter */
330 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);  in i9xx_dpll_compute_m()
348 	clock->m = clock->m1 * clock->m2;  in vlv_calc_dpll_params()
361 	clock->m = clock->m1 * clock->m2;  in chv_calc_dpll_params()
405 	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;  in i9xx_crtc_clock_get()
499 	clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;  in vlv_crtc_clock_get()
531 	clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;  in chv_crtc_clock_get()
556 	if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)  in intel_pll_is_valid()
560 		if (clock->m1 <= clock->m2)  in intel_pll_is_valid()
630 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;  in i9xx_find_best_dpll()
631 	     clock.m1++) {  in i9xx_find_best_dpll()
634 			if (clock.m2 >= clock.m1)  in i9xx_find_best_dpll()
688 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;  in pnv_find_best_dpll()
689 	     clock.m1++) {  in pnv_find_best_dpll()
750 		/* based on hardware requirement, prefere larger m1,m2 */  in g4x_find_best_dpll()
751 		for (clock.m1 = limit->m1.max;  in g4x_find_best_dpll()
752 		     clock.m1 >= limit->m1.min; clock.m1--) {  in g4x_find_best_dpll()
846 				/* based on hardware requirement, prefer bigger m1,m2 values */  in vlv_find_best_dpll()
847 				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {  in vlv_find_best_dpll()
851 								     refclk * clock.m1);  in vlv_find_best_dpll()
899 	 * Based on hardware doc, the n always set to 1, and m1 always  in chv_find_best_dpll()
904 	clock.m1 = 2;  in chv_find_best_dpll()
915 						   refclk * clock.m1);  in chv_find_best_dpll()
917 			if (m2 > INT_MAX/clock.m1)  in chv_find_best_dpll()
953 	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;  in i9xx_dpll_compute_fp()
1855 	bestm1 = crtc_state->dpll.m1;  in vlv_prepare_pll()
2005 	/* Feedback refclk divider - n and m1 */  in chv_prepare_pll()