Lines Matching full:dpll
315 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
328 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) in i9xx_dpll_compute_m() argument
330 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
333 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
346 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
359 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
376 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk() local
378 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) in i9xx_pll_refclk()
394 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_crtc_clock_get() local
396 struct dpll clock; in i9xx_crtc_clock_get()
400 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in i9xx_crtc_clock_get()
416 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> in i9xx_crtc_clock_get()
419 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> in i9xx_crtc_clock_get()
422 switch (dpll & DPLL_MODE_MASK) { in i9xx_crtc_clock_get()
424 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? in i9xx_crtc_clock_get()
428 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? in i9xx_crtc_clock_get()
433 "Unknown DPLL mode %08x in programmed " in i9xx_crtc_clock_get()
434 "mode\n", (int)(dpll & DPLL_MODE_MASK)); in i9xx_crtc_clock_get()
450 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in i9xx_crtc_clock_get()
458 if (dpll & PLL_P1_DIVIDE_BY_TWO) in i9xx_crtc_clock_get()
461 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> in i9xx_crtc_clock_get()
464 if (dpll & PLL_P2_DIVIDE_BY_4) in i9xx_crtc_clock_get()
487 struct dpll clock; in vlv_crtc_clock_get()
491 /* In case of DSI, DPLL will not be used */ in vlv_crtc_clock_get()
492 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
515 struct dpll clock; in chv_crtc_clock_get()
519 /* In case of DSI, DPLL will not be used */ in chv_crtc_clock_get()
520 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
548 const struct dpll *clock) in intel_pll_is_valid()
619 const struct dpll *match_clock, in i9xx_find_best_dpll()
620 struct dpll *best_clock) in i9xx_find_best_dpll()
623 struct dpll clock; in i9xx_find_best_dpll()
677 const struct dpll *match_clock, in pnv_find_best_dpll()
678 struct dpll *best_clock) in pnv_find_best_dpll()
681 struct dpll clock; in pnv_find_best_dpll()
733 const struct dpll *match_clock, in g4x_find_best_dpll()
734 struct dpll *best_clock) in g4x_find_best_dpll()
737 struct dpll clock; in g4x_find_best_dpll()
784 const struct dpll *calculated_clock, in vlv_PLL_is_optimal()
785 const struct dpll *best_clock, in vlv_PLL_is_optimal()
827 const struct dpll *match_clock, in vlv_find_best_dpll()
828 struct dpll *best_clock) in vlv_find_best_dpll()
832 struct dpll clock; in vlv_find_best_dpll()
885 const struct dpll *match_clock, in chv_find_best_dpll()
886 struct dpll *best_clock) in chv_find_best_dpll()
891 struct dpll clock; in chv_find_best_dpll()
941 struct dpll *best_clock) in bxt_find_best_dpll()
951 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) in i9xx_dpll_compute_fp() argument
953 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
956 static u32 pnv_dpll_compute_fp(const struct dpll *dpll) in pnv_dpll_compute_fp() argument
958 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
962 const struct dpll *clock, in i9xx_update_pll_dividers()
963 const struct dpll *reduced_clock) in i9xx_update_pll_dividers()
982 const struct dpll *clock, in i9xx_compute_dpll()
983 const struct dpll *reduced_clock) in i9xx_compute_dpll()
987 u32 dpll; in i9xx_compute_dpll() local
991 dpll = DPLL_VGA_MODE_DIS; in i9xx_compute_dpll()
994 dpll |= DPLLB_MODE_LVDS; in i9xx_compute_dpll()
996 dpll |= DPLLB_MODE_DAC_SERIAL; in i9xx_compute_dpll()
1000 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
1006 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
1009 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
1013 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
1014 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
1016 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_compute_dpll()
1019 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
1025 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in i9xx_compute_dpll()
1028 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in i9xx_compute_dpll()
1031 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in i9xx_compute_dpll()
1034 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in i9xx_compute_dpll()
1040 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); in i9xx_compute_dpll()
1043 dpll |= PLL_REF_INPUT_TVCLKINBC; in i9xx_compute_dpll()
1046 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i9xx_compute_dpll()
1048 dpll |= PLL_REF_INPUT_DREFCLK; in i9xx_compute_dpll()
1050 dpll |= DPLL_VCO_ENABLE; in i9xx_compute_dpll()
1051 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
1061 const struct dpll *clock, in i8xx_compute_dpll()
1062 const struct dpll *reduced_clock) in i8xx_compute_dpll()
1066 u32 dpll; in i8xx_compute_dpll() local
1070 dpll = DPLL_VGA_MODE_DIS; in i8xx_compute_dpll()
1073 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
1076 dpll |= PLL_P1_DIVIDE_BY_TWO; in i8xx_compute_dpll()
1078 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
1080 dpll |= PLL_P2_DIVIDE_BY_4; in i8xx_compute_dpll()
1089 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock in i8xx_compute_dpll()
1090 * Enable) must be set to “1” in both the DPLL A Control Register in i8xx_compute_dpll()
1091 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." in i8xx_compute_dpll()
1099 dpll |= DPLL_DVO_2X_MODE; in i8xx_compute_dpll()
1103 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i8xx_compute_dpll()
1105 dpll |= PLL_REF_INPUT_DREFCLK; in i8xx_compute_dpll()
1107 dpll |= DPLL_VCO_ENABLE; in i8xx_compute_dpll()
1108 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
1195 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) in ilk_needs_fb_cb_tune() argument
1197 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune()
1201 const struct dpll *clock, in ilk_update_pll_dividers()
1202 const struct dpll *reduced_clock) in ilk_update_pll_dividers()
1234 const struct dpll *clock, in ilk_compute_dpll()
1235 const struct dpll *reduced_clock) in ilk_compute_dpll()
1239 u32 dpll; in ilk_compute_dpll() local
1243 dpll = 0; in ilk_compute_dpll()
1246 dpll |= DPLLB_MODE_LVDS; in ilk_compute_dpll()
1248 dpll |= DPLLB_MODE_DAC_SERIAL; in ilk_compute_dpll()
1250 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_compute_dpll()
1255 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1258 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1263 * possible to share the DPLL between CRT and HDMI. Enabling in ilk_compute_dpll()
1268 * DPLLs and so DPLL sharing is the only way to get three pipes in ilk_compute_dpll()
1270 * and potentially avoid enabling the second DPLL, but it's not in ilk_compute_dpll()
1272 * this on ILK at all since it has a fixed DPLL<->pipe mapping. in ilk_compute_dpll()
1276 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1279 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1281 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1285 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in ilk_compute_dpll()
1288 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in ilk_compute_dpll()
1291 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in ilk_compute_dpll()
1294 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in ilk_compute_dpll()
1301 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in ilk_compute_dpll()
1303 dpll |= PLL_REF_INPUT_DREFCLK; in ilk_compute_dpll()
1305 dpll |= DPLL_VCO_ENABLE; in ilk_compute_dpll()
1307 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll()
1349 refclk, NULL, &crtc_state->dpll)) in ilk_crtc_compute_clock()
1352 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in ilk_crtc_compute_clock()
1354 ilk_compute_dpll(crtc_state, &crtc_state->dpll, in ilk_crtc_compute_clock()
1355 &crtc_state->dpll); in ilk_crtc_compute_clock()
1361 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1384 crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
1387 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
1389 /* DPLL not used with DSI, but still need the rest set up */ in vlv_compute_dpll()
1391 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
1402 crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
1405 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
1407 /* DPLL not used with DSI, but still need the rest set up */ in chv_compute_dpll()
1409 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
1425 refclk, NULL, &crtc_state->dpll)) in chv_crtc_compute_clock()
1428 chv_calc_dpll_params(refclk, &crtc_state->dpll); in chv_crtc_compute_clock()
1436 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1452 refclk, NULL, &crtc_state->dpll)) in vlv_crtc_compute_clock()
1455 vlv_calc_dpll_params(refclk, &crtc_state->dpll); in vlv_crtc_compute_clock()
1463 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1502 refclk, NULL, &crtc_state->dpll)) in g4x_crtc_compute_clock()
1505 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in g4x_crtc_compute_clock()
1507 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in g4x_crtc_compute_clock()
1508 &crtc_state->dpll); in g4x_crtc_compute_clock()
1510 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1542 refclk, NULL, &crtc_state->dpll)) in pnv_crtc_compute_clock()
1545 pnv_calc_dpll_params(refclk, &crtc_state->dpll); in pnv_crtc_compute_clock()
1547 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in pnv_crtc_compute_clock()
1548 &crtc_state->dpll); in pnv_crtc_compute_clock()
1550 crtc_state->port_clock = crtc_state->dpll.dot; in pnv_crtc_compute_clock()
1580 refclk, NULL, &crtc_state->dpll)) in i9xx_crtc_compute_clock()
1583 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in i9xx_crtc_compute_clock()
1585 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in i9xx_crtc_compute_clock()
1586 &crtc_state->dpll); in i9xx_crtc_compute_clock()
1588 crtc_state->port_clock = crtc_state->dpll.dot; in i9xx_crtc_compute_clock()
1622 refclk, NULL, &crtc_state->dpll)) in i8xx_crtc_compute_clock()
1625 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in i8xx_crtc_compute_clock()
1627 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, in i8xx_crtc_compute_clock()
1628 &crtc_state->dpll); in i8xx_crtc_compute_clock()
1630 crtc_state->port_clock = crtc_state->dpll.dot; in i8xx_crtc_compute_clock()
1694 ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc); in intel_dpll_crtc_compute_clock()
1696 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n", in intel_dpll_crtc_compute_clock()
1718 if (!i915->display.funcs.dpll->crtc_get_shared_dpll) in intel_dpll_crtc_get_shared_dpll()
1721 ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc); in intel_dpll_crtc_get_shared_dpll()
1723 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", in intel_dpll_crtc_get_shared_dpll()
1735 dev_priv->display.funcs.dpll = &mtl_dpll_funcs; in intel_dpll_init_clock_hook()
1737 dev_priv->display.funcs.dpll = &dg2_dpll_funcs; in intel_dpll_init_clock_hook()
1739 dev_priv->display.funcs.dpll = &hsw_dpll_funcs; in intel_dpll_init_clock_hook()
1741 dev_priv->display.funcs.dpll = &ilk_dpll_funcs; in intel_dpll_init_clock_hook()
1743 dev_priv->display.funcs.dpll = &chv_dpll_funcs; in intel_dpll_init_clock_hook()
1745 dev_priv->display.funcs.dpll = &vlv_dpll_funcs; in intel_dpll_init_clock_hook()
1747 dev_priv->display.funcs.dpll = &g4x_dpll_funcs; in intel_dpll_init_clock_hook()
1749 dev_priv->display.funcs.dpll = &pnv_dpll_funcs; in intel_dpll_init_clock_hook()
1751 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs; in intel_dpll_init_clock_hook()
1753 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs; in intel_dpll_init_clock_hook()
1768 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll() local
1783 * the P1/P2 dividers. Otherwise the DPLL will keep using the old in i9xx_enable_pll()
1786 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1787 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1790 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_enable_pll()
1798 * DPLL is enabled and the clocks are stable. in i9xx_enable_pll()
1802 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1807 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1808 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_enable_pll()
1854 bestn = crtc_state->dpll.n; in vlv_prepare_pll()
1855 bestm1 = crtc_state->dpll.m1; in vlv_prepare_pll()
1856 bestm2 = crtc_state->dpll.m2; in vlv_prepare_pll()
1857 bestp1 = crtc_state->dpll.p1; in vlv_prepare_pll()
1858 bestp2 = crtc_state->dpll.p2; in vlv_prepare_pll()
1939 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _vlv_enable_pll()
1940 intel_de_posting_read(dev_priv, DPLL(pipe)); in _vlv_enable_pll()
1943 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _vlv_enable_pll()
1944 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); in _vlv_enable_pll()
1959 intel_de_write(dev_priv, DPLL(pipe), in vlv_enable_pll()
1960 crtc_state->dpll_hw_state.dpll & in vlv_enable_pll()
1963 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { in vlv_enable_pll()
1985 bestm2_frac = crtc_state->dpll.m2 & 0x3fffff; in chv_prepare_pll()
1986 bestm2 = crtc_state->dpll.m2 >> 22; in chv_prepare_pll()
1987 bestp1 = crtc_state->dpll.p1; in chv_prepare_pll()
1988 bestp2 = crtc_state->dpll.p2; in chv_prepare_pll()
1989 vco = crtc_state->dpll.vco; in chv_prepare_pll()
2092 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _chv_enable_pll()
2095 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _chv_enable_pll()
2111 intel_de_write(dev_priv, DPLL(pipe), in chv_enable_pll()
2112 crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_enable_pll()
2114 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { in chv_enable_pll()
2137 (intel_de_read(dev_priv, DPLL(PIPE_B)) & in chv_enable_pll()
2150 * @dpll: PLL configuration
2152 * Enable the PLL for @pipe using the supplied @dpll config. To be used
2157 const struct dpll *dpll) in vlv_force_pll_on() argument
2168 crtc_state->dpll = *dpll; in vlv_force_pll_on()
2196 intel_de_write(dev_priv, DPLL(pipe), val); in vlv_disable_pll()
2197 intel_de_posting_read(dev_priv, DPLL(pipe)); in vlv_disable_pll()
2214 intel_de_write(dev_priv, DPLL(pipe), val); in chv_disable_pll()
2215 intel_de_posting_read(dev_priv, DPLL(pipe)); in chv_disable_pll()
2240 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()
2241 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_disable_pll()
2267 cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; in assert_pll()