Lines Matching +full:two +full:- +full:lane
2 * Copyright © 2014-2016 Intel Corporation
43 * IOSF-SB port.
45 * Each display PHY is made up of one or two channels. Each channel
46 * houses a common lane part which contains the PLL and other common
47 * logic. CH0 common lane also contains the IOSF-SB logic for the
56 * Eeach channel also has two splines (also called data lanes), and
57 * each spline is made up of one Physical Access Coding Sub-Layer
58 * (PCS) block and two TX lanes. So each channel has two PCS blocks
62 * Additionally the PHY also contains an AUX lane with AUX blocks
68 * Generally on VLV/CHV the common lane corresponds to the pipe and
101 * ---------------------------------
104 * |---------------|---------------| Display PHY
106 * |-------|-------|-------|-------|
108 * ---------------------------------
110 * ---------------------------------
113 * -----------------
116 * |---------------| Display PHY
118 * |-------|-------|
120 * -----------------
122 * -----------------
126 * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
135 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
177 .rcomp_phy = -1,
199 .rcomp_phy = -1,
252 if (port == phy_info->channel[DPIO_CH0].port) { in bxt_port_to_phy_channel()
258 if (phy_info->dual_channel && in bxt_port_to_phy_channel()
259 port == phy_info->channel[DPIO_CH1].port) { in bxt_port_to_phy_channel()
266 drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c", in bxt_port_to_phy_channel()
275 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_ddi_phy_set_signal_levels()
283 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in bxt_ddi_phy_set_signal_levels()
284 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in bxt_ddi_phy_set_signal_levels()
287 bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch); in bxt_ddi_phy_set_signal_levels()
291 * can read only lane registers and we pick lanes 0/1 for that. in bxt_ddi_phy_set_signal_levels()
299 val |= trans->entries[level].bxt.margin << MARGIN_000_SHIFT | in bxt_ddi_phy_set_signal_levels()
300 trans->entries[level].bxt.scale << UNIQ_TRANS_SCALE_SHIFT; in bxt_ddi_phy_set_signal_levels()
305 if (trans->entries[level].bxt.enable) in bxt_ddi_phy_set_signal_levels()
309 drm_err(&dev_priv->drm, in bxt_ddi_phy_set_signal_levels()
316 val |= trans->entries[level].bxt.deemphasis << DEEMPH_SHIFT; in bxt_ddi_phy_set_signal_levels()
331 if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) in bxt_ddi_phy_is_enabled()
336 drm_dbg(&dev_priv->drm, in bxt_ddi_phy_is_enabled()
343 drm_dbg(&dev_priv->drm, in bxt_ddi_phy_is_enabled()
364 drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n", in bxt_phy_wait_grc_done()
378 if (phy_info->rcomp_phy != -1) in _bxt_ddi_phy_init()
379 dev_priv->display.state.bxt_phy_grc = bxt_get_grc(dev_priv, phy); in _bxt_ddi_phy_init()
382 drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, " in _bxt_ddi_phy_init()
387 drm_dbg(&dev_priv->drm, in _bxt_ddi_phy_init()
392 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask); in _bxt_ddi_phy_init()
402 if (intel_wait_for_register_fw(&dev_priv->uncore, in _bxt_ddi_phy_init()
407 drm_err(&dev_priv->drm, "timeout during PHY%d power on\n", in _bxt_ddi_phy_init()
421 if (phy_info->dual_channel) in _bxt_ddi_phy_init()
425 if (phy_info->rcomp_phy != -1) { in _bxt_ddi_phy_init()
428 bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy); in _bxt_ddi_phy_init()
435 val = bxt_get_grc(dev_priv, phy_info->rcomp_phy); in _bxt_ddi_phy_init()
436 dev_priv->display.state.bxt_phy_grc = val; in _bxt_ddi_phy_init()
446 if (phy_info->reset_delay) in _bxt_ddi_phy_init()
447 udelay(phy_info->reset_delay); in _bxt_ddi_phy_init()
460 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0); in bxt_ddi_phy_uninit()
467 enum dpio_phy rcomp_phy = phy_info->rcomp_phy; in bxt_ddi_phy_init()
470 lockdep_assert_held(&dev_priv->display.power.domains.lock); in bxt_ddi_phy_init()
473 if (rcomp_phy != -1) in bxt_ddi_phy_init()
506 drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: " in __phy_reg_verify_state()
547 if (phy_info->dual_channel) in bxt_ddi_phy_verify_state()
552 if (phy_info->rcomp_phy != -1) { in bxt_ddi_phy_verify_state()
553 u32 grc_code = dev_priv->display.state.bxt_phy_grc; in bxt_ddi_phy_verify_state()
592 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_ddi_phy_set_lane_optim_mask()
593 enum port port = encoder->port; in bxt_ddi_phy_set_lane_optim_mask()
596 int lane; in bxt_ddi_phy_set_lane_optim_mask() local
600 for (lane = 0; lane < 4; lane++) { in bxt_ddi_phy_set_lane_optim_mask()
602 BXT_PORT_TX_DW14_LN(phy, ch, lane)); in bxt_ddi_phy_set_lane_optim_mask()
609 if (lane_lat_optim_mask & BIT(lane)) in bxt_ddi_phy_set_lane_optim_mask()
612 intel_de_write(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane), in bxt_ddi_phy_set_lane_optim_mask()
620 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_ddi_phy_get_lane_lat_optim_mask()
621 enum port port = encoder->port; in bxt_ddi_phy_get_lane_lat_optim_mask()
624 int lane; in bxt_ddi_phy_get_lane_lat_optim_mask() local
630 for (lane = 0; lane < 4; lane++) { in bxt_ddi_phy_get_lane_lat_optim_mask()
632 BXT_PORT_TX_DW14_LN(phy, ch, lane)); in bxt_ddi_phy_get_lane_lat_optim_mask()
635 mask |= BIT(lane); in bxt_ddi_phy_get_lane_lat_optim_mask()
643 switch (dig_port->base.port) { in vlv_dig_port_to_channel()
645 MISSING_CASE(dig_port->base.port); in vlv_dig_port_to_channel()
657 switch (dig_port->base.port) { in vlv_dig_port_to_phy()
659 MISSING_CASE(dig_port->base.port); in vlv_dig_port_to_phy()
702 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_set_phy_signal_level()
704 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_set_phy_signal_level()
706 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in chv_set_phy_signal_level()
719 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
732 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
740 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
748 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
771 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
785 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
798 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_data_lane_soft_reset()
799 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_data_lane_soft_reset()
801 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in chv_data_lane_soft_reset()
811 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
828 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
843 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_pre_pll_enable()
844 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_phy_pre_pll_enable()
846 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in chv_phy_pre_pll_enable()
847 enum pipe pipe = crtc->pipe; in chv_phy_pre_pll_enable()
849 intel_dp_unused_lane_mask(crtc_state->lane_count); in chv_phy_pre_pll_enable()
853 * Must trick the second common lane into life. in chv_phy_pre_pll_enable()
857 dig_port->release_cl2_override = in chv_phy_pre_pll_enable()
864 /* Assert data lane reset */ in chv_phy_pre_pll_enable()
895 if (crtc_state->lane_count > 2) { in chv_phy_pre_pll_enable()
925 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_pre_encoder_enable()
926 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_phy_pre_encoder_enable()
928 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in chv_phy_pre_encoder_enable()
939 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable()
945 /* Program Tx lane latency optimal setting*/ in chv_phy_pre_encoder_enable()
946 for (i = 0; i < crtc_state->lane_count; i++) { in chv_phy_pre_encoder_enable()
948 if (crtc_state->lane_count == 1) in chv_phy_pre_encoder_enable()
956 /* Data lane stagger programming */ in chv_phy_pre_encoder_enable()
957 if (crtc_state->port_clock > 270000) in chv_phy_pre_encoder_enable()
959 else if (crtc_state->port_clock > 135000) in chv_phy_pre_encoder_enable()
961 else if (crtc_state->port_clock > 67500) in chv_phy_pre_encoder_enable()
963 else if (crtc_state->port_clock > 33750) in chv_phy_pre_encoder_enable()
972 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable()
985 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable()
994 /* Deassert data lane reset */ in chv_phy_pre_encoder_enable()
1003 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_release_cl2_override()
1005 if (dig_port->release_cl2_override) { in chv_phy_release_cl2_override()
1007 dig_port->release_cl2_override = false; in chv_phy_release_cl2_override()
1014 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_post_pll_disable()
1015 enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe; in chv_phy_post_pll_disable()
1036 * lane so that chv_powergate_phy_ch() will power in chv_phy_post_pll_disable()
1051 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_set_phy_signal_level()
1053 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_set_phy_signal_level()
1055 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in vlv_set_phy_signal_level()
1079 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_phy_pre_pll_enable()
1080 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_phy_pre_pll_enable()
1082 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in vlv_phy_pre_pll_enable()
1084 /* Program Tx lane resets to default */ in vlv_phy_pre_pll_enable()
1096 /* Fix up inter-pair skew failure */ in vlv_phy_pre_pll_enable()
1109 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_phy_pre_encoder_enable()
1110 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_phy_pre_encoder_enable()
1112 enum pipe pipe = crtc->pipe; in vlv_phy_pre_encoder_enable()
1128 /* Program lane clock */ in vlv_phy_pre_encoder_enable()
1139 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_phy_reset_lanes()
1140 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in vlv_phy_reset_lanes()
1142 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in vlv_phy_reset_lanes()