Lines Matching +full:dp +full:- +full:connector
83 /* DP DSC throughput values used for slice count calculations KPixels/s */
88 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
98 /* Constants for DP DSC configurations */
107 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
108 * @intel_dp: DP struct
110 * If a CPU or PCH DP output is attached to an eDP panel, this function
119 return dig_port->base.type == INTEL_OUTPUT_EDP; in intel_dp_is_edp()
127 return drm_dp_is_uhbr_rate(crtc_state->port_clock); in intel_dp_is_uhbr()
131 * intel_dp_link_symbol_size - get the link symbol size for a given link rate
135 * rate -> channel coding.
143 * intel_dp_link_symbol_clock - convert link rate to link symbol clock
156 intel_dp->sink_rates[0] = 162000; in intel_dp_set_default_sink_rates()
157 intel_dp->num_sink_rates = 1; in intel_dp_set_default_sink_rates()
169 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { in intel_dp_set_dpcd_sink_rates()
173 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); in intel_dp_set_dpcd_sink_rates()
174 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); in intel_dp_set_dpcd_sink_rates()
182 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); in intel_dp_set_dpcd_sink_rates()
183 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps); in intel_dp_set_dpcd_sink_rates()
190 intel_dp->sink_rates[i] = dp_rates[i]; in intel_dp_set_dpcd_sink_rates()
197 if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) { in intel_dp_set_dpcd_sink_rates()
200 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3); in intel_dp_set_dpcd_sink_rates()
202 drm_dp_dpcd_readb(&intel_dp->aux, in intel_dp_set_dpcd_sink_rates()
205 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) { in intel_dp_set_dpcd_sink_rates()
207 if (intel_dp->lttpr_common_caps[0] >= 0x20 && in intel_dp_set_dpcd_sink_rates()
208 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER - in intel_dp_set_dpcd_sink_rates()
212 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES - in intel_dp_set_dpcd_sink_rates()
221 intel_dp->sink_rates[i++] = 1000000; in intel_dp_set_dpcd_sink_rates()
223 intel_dp->sink_rates[i++] = 1350000; in intel_dp_set_dpcd_sink_rates()
225 intel_dp->sink_rates[i++] = 2000000; in intel_dp_set_dpcd_sink_rates()
228 intel_dp->num_sink_rates = i; in intel_dp_set_dpcd_sink_rates()
233 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_set_sink_rates() local
235 struct intel_encoder *encoder = &intel_dig_port->base; in intel_dp_set_sink_rates()
239 if (intel_dp->num_sink_rates) in intel_dp_set_sink_rates()
242 drm_err(&dp_to_i915(intel_dp)->drm, in intel_dp_set_sink_rates()
243 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n", in intel_dp_set_sink_rates()
244 connector->base.base.id, connector->base.name, in intel_dp_set_sink_rates()
245 encoder->base.base.id, encoder->base.name); in intel_dp_set_sink_rates()
252 intel_dp->max_sink_lane_count = 1; in intel_dp_set_default_max_sink_lane_count()
257 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_set_max_sink_lane_count() local
259 struct intel_encoder *encoder = &intel_dig_port->base; in intel_dp_set_max_sink_lane_count()
261 intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); in intel_dp_set_max_sink_lane_count()
263 switch (intel_dp->max_sink_lane_count) { in intel_dp_set_max_sink_lane_count()
270 drm_err(&dp_to_i915(intel_dp)->drm, in intel_dp_set_max_sink_lane_count()
271 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n", in intel_dp_set_max_sink_lane_count()
272 connector->base.base.id, connector->base.name, in intel_dp_set_max_sink_lane_count()
273 encoder->base.base.id, encoder->base.name, in intel_dp_set_max_sink_lane_count()
274 intel_dp->max_sink_lane_count); in intel_dp_set_max_sink_lane_count()
286 if (rates[len - i - 1] <= max_rate) in intel_dp_rate_limit_len()
287 return len - i; in intel_dp_rate_limit_len()
297 return intel_dp_rate_limit_len(intel_dp->common_rates, in intel_dp_common_len_rate_limit()
298 intel_dp->num_common_rates, max_rate); in intel_dp_common_len_rate_limit()
303 if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm, in intel_dp_common_rate()
304 index < 0 || index >= intel_dp->num_common_rates)) in intel_dp_common_rate()
307 return intel_dp->common_rates[index]; in intel_dp_common_rate()
313 return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1); in intel_dp_max_common_rate()
318 int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata); in intel_dp_max_source_lane_count()
319 int max_lanes = dig_port->max_lanes; in intel_dp_max_source_lane_count()
332 int sink_max = intel_dp->max_sink_lane_count; in intel_dp_max_common_lane_count()
334 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps); in intel_dp_max_common_lane_count()
344 switch (intel_dp->max_link_lane_count) { in intel_dp_max_lane_count()
348 return intel_dp->max_link_lane_count; in intel_dp_max_lane_count()
350 MISSING_CASE(intel_dp->max_link_lane_count); in intel_dp_max_lane_count()
370 * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
391 * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
393 * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
400 * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
419 * 80% data bandwidth efficiency for SST non-FEC. However, this turns in intel_dp_max_data_rate()
434 struct intel_encoder *encoder = &intel_dig_port->base; in intel_dp_can_bigjoiner()
435 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dp_can_bigjoiner()
439 encoder->port != PORT_A); in intel_dp_can_bigjoiner()
450 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in icl_max_source_rate()
451 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); in icl_max_source_rate()
470 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in mtl_max_source_rate()
471 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); in mtl_max_source_rate()
481 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in vbt_max_link_rate()
484 max_rate = intel_bios_dp_max_link_rate(encoder->devdata); in vbt_max_link_rate()
487 struct intel_connector *connector = intel_dp->attached_connector; in vbt_max_link_rate() local
488 int edp_max_rate = connector->panel.vbt.edp.max_link_rate; in vbt_max_link_rate()
524 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in intel_dp_set_source_rates()
529 drm_WARN_ON(&dev_priv->drm, in intel_dp_set_source_rates()
530 intel_dp->source_rates || intel_dp->num_source_rates); in intel_dp_set_source_rates()
572 intel_dp->source_rates = source_rates; in intel_dp_set_source_rates()
573 intel_dp->num_source_rates = size; in intel_dp_set_source_rates()
599 /* return index of rate in rates array, or -1 if not found */
608 return -1; in intel_dp_rate_index()
615 drm_WARN_ON(&i915->drm, in intel_dp_set_common_rates()
616 !intel_dp->num_source_rates || !intel_dp->num_sink_rates); in intel_dp_set_common_rates()
618 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, in intel_dp_set_common_rates()
619 intel_dp->num_source_rates, in intel_dp_set_common_rates()
620 intel_dp->sink_rates, in intel_dp_set_common_rates()
621 intel_dp->num_sink_rates, in intel_dp_set_common_rates()
622 intel_dp->common_rates); in intel_dp_set_common_rates()
625 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) { in intel_dp_set_common_rates()
626 intel_dp->common_rates[0] = 162000; in intel_dp_set_common_rates()
627 intel_dp->num_common_rates = 1; in intel_dp_set_common_rates()
637 * boot-up. in intel_dp_link_params_valid()
640 link_rate > intel_dp->max_link_rate) in intel_dp_link_params_valid()
656 intel_panel_preferred_fixed_mode(intel_dp->attached_connector); in intel_dp_can_link_train_fallback_for_edp()
659 mode_rate = intel_dp_link_required(fixed_mode->clock, 18); in intel_dp_can_link_train_fallback_for_edp()
677 if (intel_dp->is_mst) { in intel_dp_get_link_train_fallback_values()
678 drm_err(&i915->drm, "Link Training Unsuccessful\n"); in intel_dp_get_link_train_fallback_values()
679 return -1; in intel_dp_get_link_train_fallback_values()
682 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { in intel_dp_get_link_train_fallback_values()
683 drm_dbg_kms(&i915->drm, in intel_dp_get_link_train_fallback_values()
685 intel_dp->use_max_params = true; in intel_dp_get_link_train_fallback_values()
689 index = intel_dp_rate_index(intel_dp->common_rates, in intel_dp_get_link_train_fallback_values()
690 intel_dp->num_common_rates, in intel_dp_get_link_train_fallback_values()
695 intel_dp_common_rate(intel_dp, index - 1), in intel_dp_get_link_train_fallback_values()
697 drm_dbg_kms(&i915->drm, in intel_dp_get_link_train_fallback_values()
701 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1); in intel_dp_get_link_train_fallback_values()
702 intel_dp->max_link_lane_count = lane_count; in intel_dp_get_link_train_fallback_values()
708 drm_dbg_kms(&i915->drm, in intel_dp_get_link_train_fallback_values()
712 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); in intel_dp_get_link_train_fallback_values()
713 intel_dp->max_link_lane_count = lane_count >> 1; in intel_dp_get_link_train_fallback_values()
715 drm_err(&i915->drm, "Link Training Unsuccessful\n"); in intel_dp_get_link_train_fallback_values()
716 return -1; in intel_dp_get_link_train_fallback_values()
732 * The hard-coded 1/0.972261=2.853% overhead factor in intel_dp_bw_fec_overhead()
733 * corresponds (for instance) to the 8b/10b DP FEC 2.4% + in intel_dp_bw_fec_overhead()
737 * lane DP link, with 2 DSC slices and 8 bpp color depth). in intel_dp_bw_fec_overhead()
760 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n", in intel_dp_dsc_nearest_valid_bpp()
765 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */ in intel_dp_dsc_nearest_valid_bpp()
767 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); in intel_dp_dsc_nearest_valid_bpp()
778 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n", in intel_dp_dsc_nearest_valid_bpp()
785 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { in intel_dp_dsc_nearest_valid_bpp()
789 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n", in intel_dp_dsc_nearest_valid_bpp()
813 i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits / in get_max_compressed_bpp_with_joiner()
837 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available) in intel_dp_dsc_get_max_compressed_bpp()
838 * for MST -> TimeSlots has to be calculated, based on mode requirements in intel_dp_dsc_get_max_compressed_bpp()
866 drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots " in intel_dp_dsc_get_max_compressed_bpp()
881 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, in intel_dp_dsc_get_slice_count() argument
885 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_dp_dsc_get_slice_count()
900 if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100)) in intel_dp_dsc_get_slice_count()
903 max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd); in intel_dp_dsc_get_slice_count()
905 drm_dbg_kms(&i915->drm, in intel_dp_dsc_get_slice_count()
906 "Unsupported slice width %d by DP DSC Sink device\n", in intel_dp_dsc_get_slice_count()
920 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false)) in intel_dp_dsc_get_slice_count()
931 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n", in intel_dp_dsc_get_slice_count()
948 * Also, ILK doesn't seem capable of DP YCbCr output. in source_can_output()
967 if (!drm_dp_is_branch(intel_dp->dpcd)) in dfp_can_convert_from_rgb()
971 return intel_dp->dfp.rgb_to_ycbcr; in dfp_can_convert_from_rgb()
974 return intel_dp->dfp.rgb_to_ycbcr && in dfp_can_convert_from_rgb()
975 intel_dp->dfp.ycbcr_444_to_420; in dfp_can_convert_from_rgb()
984 if (!drm_dp_is_branch(intel_dp->dpcd)) in dfp_can_convert_from_ycbcr444()
988 return intel_dp->dfp.ycbcr_444_to_420; in dfp_can_convert_from_ycbcr444()
1012 intel_dp_output_format(struct intel_connector *connector, in intel_dp_output_format() argument
1015 struct intel_dp *intel_dp = intel_attached_dp(connector); in intel_dp_output_format()
1018 intel_dp->force_dsc_output_format; in intel_dp_output_format()
1022 (!drm_dp_is_branch(intel_dp->dpcd) || in intel_dp_output_format()
1027 drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n"); in intel_dp_output_format()
1041 drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format)); in intel_dp_output_format()
1068 intel_dp_sink_format(struct intel_connector *connector, in intel_dp_sink_format() argument
1071 const struct drm_display_info *info = &connector->base.display_info; in intel_dp_sink_format()
1080 intel_dp_mode_min_output_bpp(struct intel_connector *connector, in intel_dp_mode_min_output_bpp() argument
1085 sink_format = intel_dp_sink_format(connector, mode); in intel_dp_mode_min_output_bpp()
1087 output_format = intel_dp_output_format(connector, sink_format); in intel_dp_mode_min_output_bpp()
1096 * Older platforms don't like hdisplay==4096 with DP. in intel_dp_hdisplay_bad()
1113 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_max_tmds_clock() local
1114 const struct drm_display_info *info = &connector->base.display_info; in intel_dp_max_tmds_clock()
1115 int max_tmds_clock = intel_dp->dfp.max_tmds_clock; in intel_dp_max_tmds_clock()
1118 if (max_tmds_clock && info->max_tmds_clock) in intel_dp_max_tmds_clock()
1119 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); in intel_dp_max_tmds_clock()
1137 min_tmds_clock = intel_dp->dfp.min_tmds_clock; in intel_dp_tmds_clock_valid()
1150 intel_dp_mode_valid_downstream(struct intel_connector *connector, in intel_dp_mode_valid_downstream() argument
1154 struct intel_dp *intel_dp = intel_attached_dp(connector); in intel_dp_mode_valid_downstream()
1155 const struct drm_display_info *info = &connector->base.display_info; in intel_dp_mode_valid_downstream()
1160 if (intel_dp->dfp.pcon_max_frl_bw) { in intel_dp_mode_valid_downstream()
1163 int bpp = intel_dp_mode_min_output_bpp(connector, mode); in intel_dp_mode_valid_downstream()
1167 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; in intel_dp_mode_valid_downstream()
1178 if (intel_dp->dfp.max_dotclock && in intel_dp_mode_valid_downstream()
1179 target_clock > intel_dp->dfp.max_dotclock) in intel_dp_mode_valid_downstream()
1182 sink_format = intel_dp_sink_format(connector, mode); in intel_dp_mode_valid_downstream()
1184 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ in intel_dp_mode_valid_downstream()
1190 !connector->base.ycbcr_420_allowed || in intel_dp_mode_valid_downstream()
1211 return clock > i915->max_dotclk_freq || hdisplay > 5120; in intel_dp_need_bigjoiner()
1218 struct intel_connector *connector = to_intel_connector(_connector); in intel_dp_mode_valid() local
1219 struct intel_dp *intel_dp = intel_attached_dp(connector); in intel_dp_mode_valid()
1220 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); in intel_dp_mode_valid()
1222 int target_clock = mode->clock; in intel_dp_mode_valid()
1224 int max_dotclk = dev_priv->max_dotclk_freq; in intel_dp_mode_valid()
1234 if (mode->flags & DRM_MODE_FLAG_DBLCLK) in intel_dp_mode_valid()
1237 fixed_mode = intel_panel_fixed_mode(connector, mode); in intel_dp_mode_valid()
1239 status = intel_panel_mode_valid(connector, mode); in intel_dp_mode_valid()
1243 target_clock = fixed_mode->clock; in intel_dp_mode_valid()
1246 if (mode->clock < 10000) in intel_dp_mode_valid()
1249 if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) { in intel_dp_mode_valid()
1256 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay)) in intel_dp_mode_valid()
1264 intel_dp_mode_min_output_bpp(connector, mode)); in intel_dp_mode_valid()
1267 drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) { in intel_dp_mode_valid()
1271 sink_format = intel_dp_sink_format(connector, mode); in intel_dp_mode_valid()
1272 output_format = intel_dp_output_format(connector, sink_format); in intel_dp_mode_valid()
1274 * TBD pass the connector BPC, in intel_dp_mode_valid()
1277 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); in intel_dp_mode_valid()
1285 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4; in intel_dp_mode_valid()
1287 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, in intel_dp_mode_valid()
1289 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) { in intel_dp_mode_valid()
1295 mode->hdisplay, in intel_dp_mode_valid()
1300 intel_dp_dsc_get_slice_count(connector, in intel_dp_mode_valid()
1302 mode->hdisplay, in intel_dp_mode_valid()
1319 status = intel_dp_mode_valid_downstream(connector, mode, target_clock); in intel_dp_mode_valid()
1348 len -= r; in snprintf_int_array()
1361 intel_dp->source_rates, intel_dp->num_source_rates); in intel_dp_print_rates()
1362 drm_dbg_kms(&i915->drm, "source rates: %s\n", str); in intel_dp_print_rates()
1365 intel_dp->sink_rates, intel_dp->num_sink_rates); in intel_dp_print_rates()
1366 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str); in intel_dp_print_rates()
1369 intel_dp->common_rates, intel_dp->num_common_rates); in intel_dp_print_rates()
1370 drm_dbg_kms(&i915->drm, "common rates: %s\n", str); in intel_dp_print_rates()
1378 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); in intel_dp_max_link_rate()
1380 return intel_dp_common_rate(intel_dp, len - 1); in intel_dp_max_link_rate()
1386 int i = intel_dp_rate_index(intel_dp->sink_rates, in intel_dp_rate_select()
1387 intel_dp->num_sink_rates, rate); in intel_dp_rate_select()
1389 if (drm_WARN_ON(&i915->drm, i < 0)) in intel_dp_rate_select()
1399 if (intel_dp->use_rate_select) { in intel_dp_compute_rate()
1411 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_has_hdmi_sink() local
1413 return connector->base.display_info.is_hdmi; in intel_dp_has_hdmi_sink()
1419 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_dp_source_supports_fec()
1425 if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A) in intel_dp_source_supports_fec()
1432 const struct intel_connector *connector, in intel_dp_supports_fec() argument
1436 drm_dp_sink_supports_fec(connector->dp.fec_capability); in intel_dp_supports_fec()
1439 static bool intel_dp_supports_dsc(const struct intel_connector *connector, in intel_dp_supports_dsc() argument
1442 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable) in intel_dp_supports_dsc()
1446 connector->dp.dsc_decompression_aux && in intel_dp_supports_dsc()
1447 drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd); in intel_dp_supports_dsc()
1454 int clock = crtc_state->hw.adjusted_mode.crtc_clock; in intel_dp_hdmi_compute_bpc()
1471 for (; bpc >= 8; bpc -= 2) { in intel_dp_hdmi_compute_bpc()
1474 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format, in intel_dp_hdmi_compute_bpc()
1479 return -EINVAL; in intel_dp_hdmi_compute_bpc()
1487 struct intel_connector *intel_connector = intel_dp->attached_connector; in intel_dp_max_bpp()
1490 bpc = crtc_state->pipe_bpp / 3; in intel_dp_max_bpp()
1492 if (intel_dp->dfp.max_bpc) in intel_dp_max_bpp()
1493 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); in intel_dp_max_bpp()
1495 if (intel_dp->dfp.min_tmds_clock) { in intel_dp_max_bpp()
1509 if (intel_connector->base.display_info.bpc == 0 && in intel_dp_max_bpp()
1510 intel_connector->panel.vbt.edp.bpp && in intel_dp_max_bpp()
1511 intel_connector->panel.vbt.edp.bpp < bpp) { in intel_dp_max_bpp()
1512 drm_dbg_kms(&dev_priv->drm, in intel_dp_max_bpp()
1513 "clamping bpp for eDP panel to BIOS-provided %i\n", in intel_dp_max_bpp()
1514 intel_connector->panel.vbt.edp.bpp); in intel_dp_max_bpp()
1515 bpp = intel_connector->panel.vbt.edp.bpp; in intel_dp_max_bpp()
1530 /* For DP Compliance we override the computed bpp for the pipe */ in intel_dp_adjust_compliance_config()
1531 if (intel_dp->compliance.test_data.bpc != 0) { in intel_dp_adjust_compliance_config()
1532 int bpp = 3 * intel_dp->compliance.test_data.bpc; in intel_dp_adjust_compliance_config()
1534 limits->pipe.min_bpp = limits->pipe.max_bpp = bpp; in intel_dp_adjust_compliance_config()
1535 pipe_config->dither_force_disable = bpp == 6 * 3; in intel_dp_adjust_compliance_config()
1537 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp); in intel_dp_adjust_compliance_config()
1541 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { in intel_dp_adjust_compliance_config()
1547 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, in intel_dp_adjust_compliance_config()
1548 intel_dp->compliance.test_lane_count)) { in intel_dp_adjust_compliance_config()
1549 index = intel_dp_rate_index(intel_dp->common_rates, in intel_dp_adjust_compliance_config()
1550 intel_dp->num_common_rates, in intel_dp_adjust_compliance_config()
1551 intel_dp->compliance.test_link_rate); in intel_dp_adjust_compliance_config()
1553 limits->min_rate = limits->max_rate = in intel_dp_adjust_compliance_config()
1554 intel_dp->compliance.test_link_rate; in intel_dp_adjust_compliance_config()
1555 limits->min_lane_count = limits->max_lane_count = in intel_dp_adjust_compliance_config()
1556 intel_dp->compliance.test_lane_count; in intel_dp_adjust_compliance_config()
1561 static bool has_seamless_m_n(struct intel_connector *connector) in has_seamless_m_n() argument
1563 struct drm_i915_private *i915 = to_i915(connector->base.dev); in has_seamless_m_n()
1570 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; in has_seamless_m_n()
1576 struct intel_connector *connector = to_intel_connector(conn_state->connector); in intel_dp_mode_clock() local
1577 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_dp_mode_clock()
1580 if (has_seamless_m_n(connector)) in intel_dp_mode_clock()
1581 return intel_panel_highest_mode(connector, adjusted_mode)->clock; in intel_dp_mode_clock()
1583 return adjusted_mode->crtc_clock; in intel_dp_mode_clock()
1596 for (bpp = to_bpp_int(limits->link.max_bpp_x16); in intel_dp_compute_link_config_wide()
1597 bpp >= to_bpp_int(limits->link.min_bpp_x16); in intel_dp_compute_link_config_wide()
1598 bpp -= 2 * 3) { in intel_dp_compute_link_config_wide()
1599 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); in intel_dp_compute_link_config_wide()
1603 for (i = 0; i < intel_dp->num_common_rates; i++) { in intel_dp_compute_link_config_wide()
1605 if (link_rate < limits->min_rate || in intel_dp_compute_link_config_wide()
1606 link_rate > limits->max_rate) in intel_dp_compute_link_config_wide()
1609 for (lane_count = limits->min_lane_count; in intel_dp_compute_link_config_wide()
1610 lane_count <= limits->max_lane_count; in intel_dp_compute_link_config_wide()
1616 pipe_config->lane_count = lane_count; in intel_dp_compute_link_config_wide()
1617 pipe_config->pipe_bpp = bpp; in intel_dp_compute_link_config_wide()
1618 pipe_config->port_clock = link_rate; in intel_dp_compute_link_config_wide()
1626 return -EINVAL; in intel_dp_compute_link_config_wide()
1641 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, in intel_dp_dsc_compute_max_bpp() argument
1644 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_dp_dsc_compute_max_bpp()
1656 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, in intel_dp_dsc_compute_max_bpp()
1673 return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >> in intel_dp_sink_dsc_version_minor()
1699 static int intel_dp_dsc_compute_params(const struct intel_connector *connector, in intel_dp_dsc_compute_params() argument
1702 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_dp_dsc_compute_params()
1703 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dp_dsc_compute_params()
1713 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in intel_dp_dsc_compute_params()
1714 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; in intel_dp_dsc_compute_params()
1716 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height); in intel_dp_dsc_compute_params()
1722 vdsc_cfg->dsc_version_major = in intel_dp_dsc_compute_params()
1723 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & in intel_dp_dsc_compute_params()
1725 vdsc_cfg->dsc_version_minor = in intel_dp_dsc_compute_params()
1727 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)); in intel_dp_dsc_compute_params()
1728 if (vdsc_cfg->convert_rgb) in intel_dp_dsc_compute_params()
1729 vdsc_cfg->convert_rgb = in intel_dp_dsc_compute_params()
1730 connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & in intel_dp_dsc_compute_params()
1733 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd); in intel_dp_dsc_compute_params()
1735 drm_dbg_kms(&i915->drm, in intel_dp_dsc_compute_params()
1737 return -EINVAL; in intel_dp_dsc_compute_params()
1740 if (vdsc_cfg->dsc_version_minor == 2) in intel_dp_dsc_compute_params()
1741 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? in intel_dp_dsc_compute_params()
1744 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? in intel_dp_dsc_compute_params()
1747 vdsc_cfg->block_pred_enable = in intel_dp_dsc_compute_params()
1748 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & in intel_dp_dsc_compute_params()
1754 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector, in intel_dp_dsc_supports_format() argument
1757 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_dp_dsc_supports_format()
1769 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2) in intel_dp_dsc_supports_format()
1777 return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format); in intel_dp_dsc_supports_format()
1799 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in dsc_compute_link_config()
1803 for (i = 0; i < intel_dp->num_common_rates; i++) { in dsc_compute_link_config()
1805 if (link_rate < limits->min_rate || link_rate > limits->max_rate) in dsc_compute_link_config()
1808 for (lane_count = limits->min_lane_count; in dsc_compute_link_config()
1809 lane_count <= limits->max_lane_count; in dsc_compute_link_config()
1812 lane_count, adjusted_mode->clock, in dsc_compute_link_config()
1813 pipe_config->output_format, in dsc_compute_link_config()
1817 pipe_config->lane_count = lane_count; in dsc_compute_link_config()
1818 pipe_config->port_clock = link_rate; in dsc_compute_link_config()
1824 return -EINVAL; in dsc_compute_link_config()
1828 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector, in intel_dp_dsc_max_sink_compressed_bppx16() argument
1832 u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd); in intel_dp_dsc_max_sink_compressed_bppx16()
1838 * values as given in spec Table 2-157 DP v2.0 in intel_dp_dsc_max_sink_compressed_bppx16()
1840 switch (pipe_config->output_format) { in intel_dp_dsc_max_sink_compressed_bppx16()
1847 MISSING_CASE(pipe_config->output_format); in intel_dp_dsc_max_sink_compressed_bppx16()
1856 /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */ in intel_dp_dsc_sink_min_compressed_bpp()
1857 switch (pipe_config->output_format) { in intel_dp_dsc_sink_min_compressed_bpp()
1864 MISSING_CASE(pipe_config->output_format); in intel_dp_dsc_sink_min_compressed_bpp()
1871 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, in intel_dp_dsc_sink_max_compressed_bpp() argument
1875 return intel_dp_dsc_max_sink_compressed_bppx16(connector, in intel_dp_dsc_sink_max_compressed_bpp()
1915 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); in icl_dsc_compute_link_config()
1928 pipe_config->dsc.compressed_bpp_x16 = in icl_dsc_compute_link_config()
1934 return -EINVAL; in icl_dsc_compute_link_config()
1939 * uncompressed bpp-1. So we start from max compressed bpp and see if any
1945 const struct intel_connector *connector, in xelpd_dsc_compute_link_config() argument
1953 u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); in xelpd_dsc_compute_link_config()
1965 dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step); in xelpd_dsc_compute_link_config()
1970 compressed_bppx16 -= bppx16_step) { in xelpd_dsc_compute_link_config()
1971 if (intel_dp->force_dsc_fractional_bpp_en && in xelpd_dsc_compute_link_config()
1980 pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16; in xelpd_dsc_compute_link_config()
1981 if (intel_dp->force_dsc_fractional_bpp_en && in xelpd_dsc_compute_link_config()
1983 drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n"); in xelpd_dsc_compute_link_config()
1988 return -EINVAL; in xelpd_dsc_compute_link_config()
1992 const struct intel_connector *connector, in dsc_compute_compressed_bpp() argument
1998 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in dsc_compute_compressed_bpp()
2007 dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16)); in dsc_compute_compressed_bpp()
2010 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, in dsc_compute_compressed_bpp()
2015 dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock, in dsc_compute_compressed_bpp()
2016 adjusted_mode->hdisplay, in dsc_compute_compressed_bpp()
2017 pipe_config->bigjoiner_pipes); in dsc_compute_compressed_bpp()
2019 dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16)); in dsc_compute_compressed_bpp()
2022 return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits, in dsc_compute_compressed_bpp()
2043 dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc); in is_dsc_pipe_bpp_sufficient()
2046 dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp); in is_dsc_pipe_bpp_sufficient()
2047 dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp); in is_dsc_pipe_bpp_sufficient()
2061 if (!intel_dp->force_dsc_bpc) in intel_dp_force_dsc_pipe_bpp()
2064 forced_bpp = intel_dp->force_dsc_bpc * 3; in intel_dp_force_dsc_pipe_bpp()
2067 drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc); in intel_dp_force_dsc_pipe_bpp()
2071 drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n", in intel_dp_force_dsc_pipe_bpp()
2072 intel_dp->force_dsc_bpc); in intel_dp_force_dsc_pipe_bpp()
2084 const struct intel_connector *connector = in intel_dp_dsc_compute_pipe_bpp() local
2085 to_intel_connector(conn_state->connector); in intel_dp_dsc_compute_pipe_bpp()
2086 u8 max_req_bpc = conn_state->max_requested_bpc; in intel_dp_dsc_compute_pipe_bpp()
2096 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config, in intel_dp_dsc_compute_pipe_bpp()
2099 pipe_config->pipe_bpp = forced_bpp; in intel_dp_dsc_compute_pipe_bpp()
2106 return -EINVAL; in intel_dp_dsc_compute_pipe_bpp()
2109 dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp); in intel_dp_dsc_compute_pipe_bpp()
2112 dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp); in intel_dp_dsc_compute_pipe_bpp()
2118 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc); in intel_dp_dsc_compute_pipe_bpp()
2125 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config, in intel_dp_dsc_compute_pipe_bpp()
2128 pipe_config->pipe_bpp = pipe_bpp; in intel_dp_dsc_compute_pipe_bpp()
2133 return -EINVAL; in intel_dp_dsc_compute_pipe_bpp()
2142 struct intel_connector *connector = in intel_edp_dsc_compute_pipe_bpp() local
2143 to_intel_connector(conn_state->connector); in intel_edp_dsc_compute_pipe_bpp()
2153 int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc); in intel_edp_dsc_compute_pipe_bpp()
2156 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc); in intel_edp_dsc_compute_pipe_bpp()
2158 drm_dbg_kms(&i915->drm, in intel_edp_dsc_compute_pipe_bpp()
2160 return -EINVAL; in intel_edp_dsc_compute_pipe_bpp()
2163 pipe_config->port_clock = limits->max_rate; in intel_edp_dsc_compute_pipe_bpp()
2164 pipe_config->lane_count = limits->max_lane_count; in intel_edp_dsc_compute_pipe_bpp()
2169 dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16)); in intel_edp_dsc_compute_pipe_bpp()
2172 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, in intel_edp_dsc_compute_pipe_bpp()
2176 dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16)); in intel_edp_dsc_compute_pipe_bpp()
2179 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); in intel_edp_dsc_compute_pipe_bpp()
2181 pipe_config->dsc.compressed_bpp_x16 = in intel_edp_dsc_compute_pipe_bpp()
2184 pipe_config->pipe_bpp = pipe_bpp; in intel_edp_dsc_compute_pipe_bpp()
2197 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in intel_dp_dsc_compute_config()
2198 const struct intel_connector *connector = in intel_dp_dsc_compute_config() local
2199 to_intel_connector(conn_state->connector); in intel_dp_dsc_compute_config()
2201 &pipe_config->hw.adjusted_mode; in intel_dp_dsc_compute_config()
2204 pipe_config->fec_enable = pipe_config->fec_enable || in intel_dp_dsc_compute_config()
2206 intel_dp_supports_fec(intel_dp, connector, pipe_config)); in intel_dp_dsc_compute_config()
2208 if (!intel_dp_supports_dsc(connector, pipe_config)) in intel_dp_dsc_compute_config()
2209 return -EINVAL; in intel_dp_dsc_compute_config()
2211 if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format)) in intel_dp_dsc_compute_config()
2212 return -EINVAL; in intel_dp_dsc_compute_config()
2215 * compute pipe bpp is set to false for DP MST DSC case in intel_dp_dsc_compute_config()
2228 drm_dbg_kms(&dev_priv->drm, in intel_dp_dsc_compute_config()
2236 pipe_config->dsc.slice_count = in intel_dp_dsc_compute_config()
2237 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, in intel_dp_dsc_compute_config()
2239 if (!pipe_config->dsc.slice_count) { in intel_dp_dsc_compute_config()
2240 drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n", in intel_dp_dsc_compute_config()
2241 pipe_config->dsc.slice_count); in intel_dp_dsc_compute_config()
2242 return -EINVAL; in intel_dp_dsc_compute_config()
2248 intel_dp_dsc_get_slice_count(connector, in intel_dp_dsc_compute_config()
2249 adjusted_mode->crtc_clock, in intel_dp_dsc_compute_config()
2250 adjusted_mode->crtc_hdisplay, in intel_dp_dsc_compute_config()
2251 pipe_config->bigjoiner_pipes); in intel_dp_dsc_compute_config()
2253 drm_dbg_kms(&dev_priv->drm, in intel_dp_dsc_compute_config()
2255 return -EINVAL; in intel_dp_dsc_compute_config()
2258 pipe_config->dsc.slice_count = dsc_dp_slice_count; in intel_dp_dsc_compute_config()
2265 if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1) in intel_dp_dsc_compute_config()
2266 pipe_config->dsc.dsc_split = true; in intel_dp_dsc_compute_config()
2268 ret = intel_dp_dsc_compute_params(connector, pipe_config); in intel_dp_dsc_compute_config()
2270 drm_dbg_kms(&dev_priv->drm, in intel_dp_dsc_compute_config()
2273 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
2274 BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16)); in intel_dp_dsc_compute_config()
2278 pipe_config->dsc.compression_enable = true; in intel_dp_dsc_compute_config()
2279 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d " in intel_dp_dsc_compute_config()
2281 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
2282 BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16), in intel_dp_dsc_compute_config()
2283 pipe_config->dsc.slice_count); in intel_dp_dsc_compute_config()
2289 * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
2290 * @intel_dp: intel DP
2306 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in intel_dp_compute_config_link_bpp_limits()
2308 &crtc_state->hw.adjusted_mode; in intel_dp_compute_config_link_bpp_limits()
2309 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dp_compute_config_link_bpp_limits()
2310 const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_dp_compute_config_link_bpp_limits()
2313 max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16, in intel_dp_compute_config_link_bpp_limits()
2314 to_bpp_x16(limits->pipe.max_bpp)); in intel_dp_compute_config_link_bpp_limits()
2319 if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp)) in intel_dp_compute_config_link_bpp_limits()
2322 limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp); in intel_dp_compute_config_link_bpp_limits()
2329 limits->link.min_bpp_x16 = 0; in intel_dp_compute_config_link_bpp_limits()
2332 limits->link.max_bpp_x16 = max_link_bpp_x16; in intel_dp_compute_config_link_bpp_limits()
2334 drm_dbg_kms(&i915->drm, in intel_dp_compute_config_link_bpp_limits()
2335 …"[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d ma… in intel_dp_compute_config_link_bpp_limits()
2336 encoder->base.base.id, encoder->base.name, in intel_dp_compute_config_link_bpp_limits()
2337 crtc->base.base.id, crtc->base.name, in intel_dp_compute_config_link_bpp_limits()
2338 adjusted_mode->crtc_clock, in intel_dp_compute_config_link_bpp_limits()
2340 limits->max_lane_count, in intel_dp_compute_config_link_bpp_limits()
2341 limits->max_rate, in intel_dp_compute_config_link_bpp_limits()
2342 limits->pipe.max_bpp, in intel_dp_compute_config_link_bpp_limits()
2343 BPP_X16_ARGS(limits->link.max_bpp_x16)); in intel_dp_compute_config_link_bpp_limits()
2355 limits->min_rate = intel_dp_common_rate(intel_dp, 0); in intel_dp_compute_config_limits()
2356 limits->max_rate = intel_dp_max_link_rate(intel_dp); in intel_dp_compute_config_limits()
2359 limits->max_rate = min(limits->max_rate, 810000); in intel_dp_compute_config_limits()
2361 limits->min_lane_count = 1; in intel_dp_compute_config_limits()
2362 limits->max_lane_count = intel_dp_max_lane_count(intel_dp); in intel_dp_compute_config_limits()
2364 limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format); in intel_dp_compute_config_limits()
2365 limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state, in intel_dp_compute_config_limits()
2368 if (intel_dp->use_max_params) { in intel_dp_compute_config_limits()
2377 limits->min_lane_count = limits->max_lane_count; in intel_dp_compute_config_limits()
2378 limits->min_rate = limits->max_rate; in intel_dp_compute_config_limits()
2395 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dp_compute_link_config()
2396 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dp_compute_link_config()
2397 const struct intel_connector *connector = in intel_dp_compute_link_config() local
2398 to_intel_connector(conn_state->connector); in intel_dp_compute_link_config()
2400 &pipe_config->hw.adjusted_mode; in intel_dp_compute_link_config()
2407 if (pipe_config->fec_enable && in intel_dp_compute_link_config()
2408 !intel_dp_supports_fec(intel_dp, connector, pipe_config)) in intel_dp_compute_link_config()
2409 return -EINVAL; in intel_dp_compute_link_config()
2411 if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay, in intel_dp_compute_link_config()
2412 adjusted_mode->crtc_clock)) in intel_dp_compute_link_config()
2413 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe); in intel_dp_compute_link_config()
2420 joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes; in intel_dp_compute_link_config()
2422 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en || in intel_dp_compute_link_config()
2440 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n", in intel_dp_compute_link_config()
2442 str_yes_no(intel_dp->force_dsc_en)); in intel_dp_compute_link_config()
2448 return -EINVAL; in intel_dp_compute_link_config()
2456 if (pipe_config->dsc.compression_enable) { in intel_dp_compute_link_config()
2457 drm_dbg_kms(&i915->drm, in intel_dp_compute_link_config()
2458 "DP lane count %d clock %d Input bpp %d Compressed bpp " BPP_X16_FMT "\n", in intel_dp_compute_link_config()
2459 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
2460 pipe_config->pipe_bpp, in intel_dp_compute_link_config()
2461 BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16)); in intel_dp_compute_link_config()
2463 drm_dbg_kms(&i915->drm, in intel_dp_compute_link_config()
2464 "DP link rate required %i available %i\n", in intel_dp_compute_link_config()
2465 intel_dp_link_required(adjusted_mode->crtc_clock, in intel_dp_compute_link_config()
2466 to_bpp_int_roundup(pipe_config->dsc.compressed_bpp_x16)), in intel_dp_compute_link_config()
2467 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
2468 pipe_config->lane_count)); in intel_dp_compute_link_config()
2470 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n", in intel_dp_compute_link_config()
2471 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
2472 pipe_config->pipe_bpp); in intel_dp_compute_link_config()
2474 drm_dbg_kms(&i915->drm, in intel_dp_compute_link_config()
2475 "DP link rate required %i available %i\n", in intel_dp_compute_link_config()
2476 intel_dp_link_required(adjusted_mode->crtc_clock, in intel_dp_compute_link_config()
2477 pipe_config->pipe_bpp), in intel_dp_compute_link_config()
2478 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
2479 pipe_config->lane_count)); in intel_dp_compute_link_config()
2490 &crtc_state->hw.adjusted_mode; in intel_dp_limited_color_range()
2494 * crtc_state->limited_color_range only applies to RGB, in intel_dp_limited_color_range()
2499 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) in intel_dp_limited_color_range()
2502 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { in intel_dp_limited_color_range()
2505 * CEA-861-E - 5.1 Default Encoding Parameters in intel_dp_limited_color_range()
2506 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry in intel_dp_limited_color_range()
2508 return crtc_state->pipe_bpp != 18 && in intel_dp_limited_color_range()
2512 return intel_conn_state->broadcast_rgb == in intel_dp_limited_color_range()
2532 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dp_compute_vsc_colorimetry()
2533 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dp_compute_vsc_colorimetry()
2535 if (crtc_state->has_panel_replay) { in intel_dp_compute_vsc_colorimetry()
2537 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 in intel_dp_compute_vsc_colorimetry()
2541 vsc->revision = 0x7; in intel_dp_compute_vsc_colorimetry()
2544 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 in intel_dp_compute_vsc_colorimetry()
2548 vsc->revision = 0x5; in intel_dp_compute_vsc_colorimetry()
2551 vsc->length = 0x13; in intel_dp_compute_vsc_colorimetry()
2553 /* DP 1.4a spec, Table 2-120 */ in intel_dp_compute_vsc_colorimetry()
2554 switch (crtc_state->output_format) { in intel_dp_compute_vsc_colorimetry()
2556 vsc->pixelformat = DP_PIXELFORMAT_YUV444; in intel_dp_compute_vsc_colorimetry()
2559 vsc->pixelformat = DP_PIXELFORMAT_YUV420; in intel_dp_compute_vsc_colorimetry()
2563 vsc->pixelformat = DP_PIXELFORMAT_RGB; in intel_dp_compute_vsc_colorimetry()
2566 switch (conn_state->colorspace) { in intel_dp_compute_vsc_colorimetry()
2568 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; in intel_dp_compute_vsc_colorimetry()
2571 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; in intel_dp_compute_vsc_colorimetry()
2574 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; in intel_dp_compute_vsc_colorimetry()
2577 vsc->colorimetry = DP_COLORIMETRY_SYCC_601; in intel_dp_compute_vsc_colorimetry()
2580 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601; in intel_dp_compute_vsc_colorimetry()
2583 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC; in intel_dp_compute_vsc_colorimetry()
2586 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB; in intel_dp_compute_vsc_colorimetry()
2589 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC; in intel_dp_compute_vsc_colorimetry()
2593 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB; in intel_dp_compute_vsc_colorimetry()
2597 * RGB->YCBCR color conversion uses the BT.709 in intel_dp_compute_vsc_colorimetry()
2600 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) in intel_dp_compute_vsc_colorimetry()
2601 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; in intel_dp_compute_vsc_colorimetry()
2603 vsc->colorimetry = DP_COLORIMETRY_DEFAULT; in intel_dp_compute_vsc_colorimetry()
2607 vsc->bpc = crtc_state->pipe_bpp / 3; in intel_dp_compute_vsc_colorimetry()
2610 drm_WARN_ON(&dev_priv->drm, in intel_dp_compute_vsc_colorimetry()
2611 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB); in intel_dp_compute_vsc_colorimetry()
2614 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; in intel_dp_compute_vsc_colorimetry()
2615 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; in intel_dp_compute_vsc_colorimetry()
2622 struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc; in intel_dp_compute_vsc_sdp()
2625 if (crtc_state->has_psr) in intel_dp_compute_vsc_sdp()
2631 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); in intel_dp_compute_vsc_sdp()
2632 vsc->sdp_type = DP_SDP_VSC; in intel_dp_compute_vsc_sdp()
2634 &crtc_state->infoframes.vsc); in intel_dp_compute_vsc_sdp()
2642 vsc->sdp_type = DP_SDP_VSC; in intel_dp_compute_psr_vsc_sdp()
2644 if (crtc_state->has_psr2) { in intel_dp_compute_psr_vsc_sdp()
2645 if (intel_dp->psr.colorimetry_support && in intel_dp_compute_psr_vsc_sdp()
2652 * [PSR2, -Colorimetry] in intel_dp_compute_psr_vsc_sdp()
2653 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 in intel_dp_compute_psr_vsc_sdp()
2654 * 3D stereo + PSR/PSR2 + Y-coordinate. in intel_dp_compute_psr_vsc_sdp()
2656 vsc->revision = 0x4; in intel_dp_compute_psr_vsc_sdp()
2657 vsc->length = 0xe; in intel_dp_compute_psr_vsc_sdp()
2659 } else if (crtc_state->has_panel_replay) { in intel_dp_compute_psr_vsc_sdp()
2660 if (intel_dp->psr.colorimetry_support && in intel_dp_compute_psr_vsc_sdp()
2668 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 in intel_dp_compute_psr_vsc_sdp()
2671 vsc->revision = 0x6; in intel_dp_compute_psr_vsc_sdp()
2672 vsc->length = 0x10; in intel_dp_compute_psr_vsc_sdp()
2677 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 in intel_dp_compute_psr_vsc_sdp()
2681 vsc->revision = 0x2; in intel_dp_compute_psr_vsc_sdp()
2682 vsc->length = 0x8; in intel_dp_compute_psr_vsc_sdp()
2693 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm; in intel_dp_compute_hdr_metadata_infoframe_sdp()
2695 if (!conn_state->hdr_output_metadata) in intel_dp_compute_hdr_metadata_infoframe_sdp()
2701 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n"); in intel_dp_compute_hdr_metadata_infoframe_sdp()
2705 crtc_state->infoframes.enable |= in intel_dp_compute_hdr_metadata_infoframe_sdp()
2718 static bool can_enable_drrs(struct intel_connector *connector, in can_enable_drrs() argument
2722 struct drm_i915_private *i915 = to_i915(connector->base.dev); in can_enable_drrs()
2724 if (pipe_config->vrr.enable) in can_enable_drrs()
2729 * as it allows more power-savings by complete shutting down display, in can_enable_drrs()
2733 if (pipe_config->has_psr) in can_enable_drrs()
2737 if (pipe_config->has_pch_encoder) in can_enable_drrs()
2740 if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder)) in can_enable_drrs()
2744 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; in can_enable_drrs()
2748 intel_dp_drrs_compute_config(struct intel_connector *connector, in intel_dp_drrs_compute_config() argument
2752 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_dp_drrs_compute_config()
2754 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); in intel_dp_drrs_compute_config()
2757 if (has_seamless_m_n(connector)) in intel_dp_drrs_compute_config()
2758 pipe_config->update_m_n = true; in intel_dp_drrs_compute_config()
2760 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { in intel_dp_drrs_compute_config()
2761 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) in intel_dp_drrs_compute_config()
2762 intel_zero_m_n(&pipe_config->dp_m2_n2); in intel_dp_drrs_compute_config()
2767 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay; in intel_dp_drrs_compute_config()
2769 pipe_config->has_drrs = true; in intel_dp_drrs_compute_config()
2771 pixel_clock = downclock_mode->clock; in intel_dp_drrs_compute_config()
2772 if (pipe_config->splitter.enable) in intel_dp_drrs_compute_config()
2773 pixel_clock /= pipe_config->splitter.link_count; in intel_dp_drrs_compute_config()
2775 intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock, in intel_dp_drrs_compute_config()
2776 pipe_config->port_clock, in intel_dp_drrs_compute_config()
2777 intel_dp_bw_fec_overhead(pipe_config->fec_enable), in intel_dp_drrs_compute_config()
2778 &pipe_config->dp_m2_n2); in intel_dp_drrs_compute_config()
2781 if (pipe_config->splitter.enable) in intel_dp_drrs_compute_config()
2782 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; in intel_dp_drrs_compute_config()
2789 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dp_has_audio()
2792 struct intel_connector *connector = in intel_dp_has_audio() local
2793 to_intel_connector(conn_state->connector); in intel_dp_has_audio()
2796 !intel_dp_port_has_audio(i915, encoder->port)) in intel_dp_has_audio()
2799 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) in intel_dp_has_audio()
2800 return connector->base.display_info.has_audio; in intel_dp_has_audio()
2802 return intel_conn_state->force_audio == HDMI_AUDIO_ON; in intel_dp_has_audio()
2811 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dp_compute_output_format()
2813 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_compute_output_format() local
2814 const struct drm_display_info *info = &connector->base.display_info; in intel_dp_compute_output_format()
2815 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_dp_compute_output_format()
2821 if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) { in intel_dp_compute_output_format()
2822 drm_dbg_kms(&i915->drm, in intel_dp_compute_output_format()
2824 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dp_compute_output_format()
2826 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode); in intel_dp_compute_output_format()
2829 crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format); in intel_dp_compute_output_format()
2834 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || in intel_dp_compute_output_format()
2835 !connector->base.ycbcr_420_allowed || in intel_dp_compute_output_format()
2839 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; in intel_dp_compute_output_format()
2840 crtc_state->output_format = intel_dp_output_format(connector, in intel_dp_compute_output_format()
2841 crtc_state->sink_format); in intel_dp_compute_output_format()
2854 pipe_config->has_audio = in intel_dp_audio_compute_config()
2858 pipe_config->sdp_split_enable = pipe_config->has_audio && in intel_dp_audio_compute_config()
2867 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dp_compute_config()
2868 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dp_compute_config()
2871 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_compute_config() local
2874 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A) in intel_dp_compute_config()
2875 pipe_config->has_pch_encoder = true; in intel_dp_compute_config()
2877 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode); in intel_dp_compute_config()
2879 ret = intel_panel_compute_config(connector, adjusted_mode); in intel_dp_compute_config()
2884 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_dp_compute_config()
2885 return -EINVAL; in intel_dp_compute_config()
2887 if (!connector->base.interlace_allowed && in intel_dp_compute_config()
2888 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) in intel_dp_compute_config()
2889 return -EINVAL; in intel_dp_compute_config()
2891 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) in intel_dp_compute_config()
2892 return -EINVAL; in intel_dp_compute_config()
2894 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay)) in intel_dp_compute_config()
2895 return -EINVAL; in intel_dp_compute_config()
2908 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { in intel_dp_compute_config()
2914 pipe_config->limited_color_range = in intel_dp_compute_config()
2917 pipe_config->enhanced_framing = in intel_dp_compute_config()
2918 drm_dp_enhanced_frame_cap(intel_dp->dpcd); in intel_dp_compute_config()
2920 if (pipe_config->dsc.compression_enable) in intel_dp_compute_config()
2921 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16; in intel_dp_compute_config()
2923 link_bpp_x16 = to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format, in intel_dp_compute_config()
2924 pipe_config->pipe_bpp)); in intel_dp_compute_config()
2926 if (intel_dp->mso_link_count) { in intel_dp_compute_config()
2927 int n = intel_dp->mso_link_count; in intel_dp_compute_config()
2928 int overlap = intel_dp->mso_pixel_overlap; in intel_dp_compute_config()
2930 pipe_config->splitter.enable = true; in intel_dp_compute_config()
2931 pipe_config->splitter.link_count = n; in intel_dp_compute_config()
2932 pipe_config->splitter.pixel_overlap = overlap; in intel_dp_compute_config()
2934 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n", in intel_dp_compute_config()
2937 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap; in intel_dp_compute_config()
2938 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap; in intel_dp_compute_config()
2939 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap; in intel_dp_compute_config()
2940 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap; in intel_dp_compute_config()
2941 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap; in intel_dp_compute_config()
2942 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap; in intel_dp_compute_config()
2943 adjusted_mode->crtc_clock /= n; in intel_dp_compute_config()
2949 pipe_config->lane_count, in intel_dp_compute_config()
2950 adjusted_mode->crtc_clock, in intel_dp_compute_config()
2951 pipe_config->port_clock, in intel_dp_compute_config()
2952 intel_dp_bw_fec_overhead(pipe_config->fec_enable), in intel_dp_compute_config()
2953 &pipe_config->dp_m_n); in intel_dp_compute_config()
2956 if (pipe_config->splitter.enable) in intel_dp_compute_config()
2957 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count; in intel_dp_compute_config()
2964 intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); in intel_dp_compute_config()
2974 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); in intel_dp_set_link_params()
2975 intel_dp->link_trained = false; in intel_dp_set_link_params()
2976 intel_dp->link_rate = link_rate; in intel_dp_set_link_params()
2977 intel_dp->lane_count = lane_count; in intel_dp_set_link_params()
2982 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); in intel_dp_reset_max_link_params()
2983 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); in intel_dp_reset_max_link_params()
2990 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)); in intel_edp_backlight_on()
2996 drm_dbg_kms(&i915->drm, "\n"); in intel_edp_backlight_on()
3005 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)); in intel_edp_backlight_off()
3011 drm_dbg_kms(&i915->drm, "\n"); in intel_edp_backlight_off()
3027 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && in downstream_hpd_needs_d0()
3028 drm_dp_is_branch(intel_dp->dpcd) && in downstream_hpd_needs_d0()
3029 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; in downstream_hpd_needs_d0()
3051 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector, in intel_dp_sink_set_dsc_decompression() argument
3054 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_dp_sink_set_dsc_decompression()
3056 if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux, in intel_dp_sink_set_dsc_decompression()
3058 drm_dbg_kms(&i915->drm, in intel_dp_sink_set_dsc_decompression()
3064 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector, in intel_dp_sink_set_dsc_passthrough() argument
3067 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_dp_sink_set_dsc_passthrough()
3068 struct drm_dp_aux *aux = connector->port ? in intel_dp_sink_set_dsc_passthrough()
3069 connector->port->passthrough_aux : NULL; in intel_dp_sink_set_dsc_passthrough()
3076 drm_dbg_kms(&i915->drm, in intel_dp_sink_set_dsc_passthrough()
3082 const struct intel_connector *connector, in intel_dp_dsc_aux_ref_count() argument
3085 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dp_dsc_aux_ref_count()
3093 * On SST the decompression AUX device won't be shared, each connector in intel_dp_dsc_aux_ref_count()
3096 if (!connector->mst_port) in intel_dp_dsc_aux_ref_count()
3097 return connector->dp.dsc_decompression_enabled ? 1 : 0; in intel_dp_dsc_aux_ref_count()
3099 for_each_oldnew_connector_in_state(&state->base, _connector_iter, in intel_dp_dsc_aux_ref_count()
3104 if (connector_iter->mst_port != connector->mst_port) in intel_dp_dsc_aux_ref_count()
3107 if (!connector_iter->dp.dsc_decompression_enabled) in intel_dp_dsc_aux_ref_count()
3110 drm_WARN_ON(&i915->drm, in intel_dp_dsc_aux_ref_count()
3111 (for_get_ref && !new_conn_state->crtc) || in intel_dp_dsc_aux_ref_count()
3112 (!for_get_ref && !old_conn_state->crtc)); in intel_dp_dsc_aux_ref_count()
3114 if (connector_iter->dp.dsc_decompression_aux == in intel_dp_dsc_aux_ref_count()
3115 connector->dp.dsc_decompression_aux) in intel_dp_dsc_aux_ref_count()
3123 struct intel_connector *connector) in intel_dp_dsc_aux_get_ref() argument
3125 bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0; in intel_dp_dsc_aux_get_ref()
3127 connector->dp.dsc_decompression_enabled = true; in intel_dp_dsc_aux_get_ref()
3133 struct intel_connector *connector) in intel_dp_dsc_aux_put_ref() argument
3135 connector->dp.dsc_decompression_enabled = false; in intel_dp_dsc_aux_put_ref()
3137 return intel_dp_dsc_aux_ref_count(state, connector, false) == 0; in intel_dp_dsc_aux_put_ref()
3141 * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3143 * @connector: connector to enable the decompression for
3144 * @new_crtc_state: new state for the CRTC driving @connector
3154 struct intel_connector *connector, in intel_dp_sink_enable_decompression() argument
3157 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dp_sink_enable_decompression()
3159 if (!new_crtc_state->dsc.compression_enable) in intel_dp_sink_enable_decompression()
3162 if (drm_WARN_ON(&i915->drm, in intel_dp_sink_enable_decompression()
3163 !connector->dp.dsc_decompression_aux || in intel_dp_sink_enable_decompression()
3164 connector->dp.dsc_decompression_enabled)) in intel_dp_sink_enable_decompression()
3167 if (!intel_dp_dsc_aux_get_ref(state, connector)) in intel_dp_sink_enable_decompression()
3170 intel_dp_sink_set_dsc_passthrough(connector, true); in intel_dp_sink_enable_decompression()
3171 intel_dp_sink_set_dsc_decompression(connector, true); in intel_dp_sink_enable_decompression()
3175 * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3177 * @connector: connector to disable the decompression for
3178 * @old_crtc_state: old state for the CRTC driving @connector
3185 struct intel_connector *connector, in intel_dp_sink_disable_decompression() argument
3188 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dp_sink_disable_decompression()
3190 if (!old_crtc_state->dsc.compression_enable) in intel_dp_sink_disable_decompression()
3193 if (drm_WARN_ON(&i915->drm, in intel_dp_sink_disable_decompression()
3194 !connector->dp.dsc_decompression_aux || in intel_dp_sink_disable_decompression()
3195 !connector->dp.dsc_decompression_enabled)) in intel_dp_sink_disable_decompression()
3198 if (!intel_dp_dsc_aux_put_ref(state, connector)) in intel_dp_sink_disable_decompression()
3201 intel_dp_sink_set_dsc_decompression(connector, false); in intel_dp_sink_disable_decompression()
3202 intel_dp_sink_set_dsc_passthrough(connector, false); in intel_dp_sink_disable_decompression()
3217 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) in intel_edp_init_source_oui()
3218 drm_err(&i915->drm, "Failed to read source OUI\n"); in intel_edp_init_source_oui()
3224 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) in intel_edp_init_source_oui()
3225 drm_err(&i915->drm, "Failed to write source OUI\n"); in intel_edp_init_source_oui()
3227 intel_dp->last_oui_write = jiffies; in intel_edp_init_source_oui()
3232 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_wait_source_oui() local
3235 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n", in intel_dp_wait_source_oui()
3236 connector->base.base.id, connector->base.name, in intel_dp_wait_source_oui()
3237 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); in intel_dp_wait_source_oui()
3239 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, in intel_dp_wait_source_oui()
3240 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); in intel_dp_wait_source_oui()
3246 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_dp_set_power()
3247 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dp_set_power()
3251 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_set_power()
3258 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); in intel_dp_set_power()
3273 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); in intel_dp_set_power()
3279 if (ret == 1 && lspcon->active) in intel_dp_set_power()
3284 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n", in intel_dp_set_power()
3285 encoder->base.base.id, encoder->base.name, in intel_dp_set_power()
3293 * intel_dp_sync_state - sync the encoder state during init/resume
3312 if (intel_dp->dpcd[DP_DPCD_REV] == 0) in intel_dp_sync_state()
3321 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dp_initial_fastset_check()
3326 * If BIOS has set an unsupported or non-standard link rate for some in intel_dp_initial_fastset_check()
3329 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates, in intel_dp_initial_fastset_check()
3330 crtc_state->port_clock) < 0) { in intel_dp_initial_fastset_check()
3331 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n", in intel_dp_initial_fastset_check()
3332 encoder->base.base.id, encoder->base.name); in intel_dp_initial_fastset_check()
3333 crtc_state->uapi.connectors_changed = true; in intel_dp_initial_fastset_check()
3341 * of crtc_state->dsc, we have no way to ensure reliable fastset. in intel_dp_initial_fastset_check()
3344 if (crtc_state->dsc.compression_enable) { in intel_dp_initial_fastset_check()
3345 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n", in intel_dp_initial_fastset_check()
3346 encoder->base.base.id, encoder->base.name); in intel_dp_initial_fastset_check()
3347 crtc_state->uapi.mode_changed = true; in intel_dp_initial_fastset_check()
3352 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n", in intel_dp_initial_fastset_check()
3353 encoder->base.base.id, encoder->base.name); in intel_dp_initial_fastset_check()
3354 crtc_state->uapi.mode_changed = true; in intel_dp_initial_fastset_check()
3367 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); in intel_dp_get_pcon_dsc_cap()
3369 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, in intel_dp_get_pcon_dsc_cap()
3370 intel_dp->pcon_dsc_dpcd, in intel_dp_get_pcon_dsc_cap()
3371 sizeof(intel_dp->pcon_dsc_dpcd)) < 0) in intel_dp_get_pcon_dsc_cap()
3372 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n", in intel_dp_get_pcon_dsc_cap()
3375 drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n", in intel_dp_get_pcon_dsc_cap()
3376 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd); in intel_dp_get_pcon_dsc_cap()
3384 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) { in intel_dp_pcon_get_frl_mask()
3413 struct intel_connector *intel_connector = intel_dp->attached_connector; in intel_dp_hdmi_sink_max_frl()
3414 struct drm_connector *connector = &intel_connector->base; in intel_dp_hdmi_sink_max_frl() local
3419 max_lanes = connector->display_info.hdmi.max_lanes; in intel_dp_hdmi_sink_max_frl()
3420 rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane; in intel_dp_hdmi_sink_max_frl()
3423 if (connector->display_info.hdmi.dsc_cap.v_1p2) { in intel_dp_hdmi_sink_max_frl()
3424 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes; in intel_dp_hdmi_sink_max_frl()
3425 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane; in intel_dp_hdmi_sink_max_frl()
3437 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) && in intel_dp_pcon_is_frl_trained()
3438 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL && in intel_dp_pcon_is_frl_trained()
3455 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw; in intel_dp_pcon_start_frl_training()
3456 drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw); in intel_dp_pcon_start_frl_training()
3459 drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw); in intel_dp_pcon_start_frl_training()
3464 return -EINVAL; in intel_dp_pcon_start_frl_training()
3467 drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask); in intel_dp_pcon_start_frl_training()
3472 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false); in intel_dp_pcon_start_frl_training()
3476 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS); in intel_dp_pcon_start_frl_training()
3479 return -ETIMEDOUT; in intel_dp_pcon_start_frl_training()
3481 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, in intel_dp_pcon_start_frl_training()
3485 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, in intel_dp_pcon_start_frl_training()
3489 ret = drm_dp_pcon_frl_enable(&intel_dp->aux); in intel_dp_pcon_start_frl_training()
3501 return -ETIMEDOUT; in intel_dp_pcon_start_frl_training()
3504 drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask); in intel_dp_pcon_start_frl_training()
3505 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask); in intel_dp_pcon_start_frl_training()
3506 intel_dp->frl.is_trained = true; in intel_dp_pcon_start_frl_training()
3507 drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps); in intel_dp_pcon_start_frl_training()
3514 if (drm_dp_is_branch(intel_dp->dpcd) && in intel_dp_is_hdmi_2_1_sink()
3531 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); in intel_dp_pcon_set_tmds_mode()
3537 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); in intel_dp_pcon_set_tmds_mode()
3550 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7) in intel_dp_check_frl_training()
3551 * -sink is HDMI2.1 in intel_dp_check_frl_training()
3553 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) || in intel_dp_check_frl_training()
3555 intel_dp->frl.is_trained) in intel_dp_check_frl_training()
3561 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n"); in intel_dp_check_frl_training()
3563 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL); in intel_dp_check_frl_training()
3566 drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n"); in intel_dp_check_frl_training()
3568 drm_dbg(&dev_priv->drm, "FRL training Completed\n"); in intel_dp_check_frl_training()
3575 int vactive = crtc_state->hw.adjusted_mode.vdisplay; in intel_dp_pcon_dsc_enc_slice_height()
3584 struct intel_connector *intel_connector = intel_dp->attached_connector; in intel_dp_pcon_dsc_enc_slices()
3585 struct drm_connector *connector = &intel_connector->base; in intel_dp_pcon_dsc_enc_slices() local
3586 int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice; in intel_dp_pcon_dsc_enc_slices()
3587 int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices; in intel_dp_pcon_dsc_enc_slices()
3588 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd); in intel_dp_pcon_dsc_enc_slices()
3589 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd); in intel_dp_pcon_dsc_enc_slices()
3601 struct intel_connector *intel_connector = intel_dp->attached_connector; in intel_dp_pcon_dsc_enc_bpp()
3602 struct drm_connector *connector = &intel_connector->base; in intel_dp_pcon_dsc_enc_bpp() local
3603 int output_format = crtc_state->output_format; in intel_dp_pcon_dsc_enc_bpp()
3604 bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp; in intel_dp_pcon_dsc_enc_bpp()
3605 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd); in intel_dp_pcon_dsc_enc_bpp()
3607 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024; in intel_dp_pcon_dsc_enc_bpp()
3624 struct intel_connector *intel_connector = intel_dp->attached_connector; in intel_dp_pcon_dsc_configure()
3626 struct drm_connector *connector; in intel_dp_pcon_dsc_configure() local
3634 connector = &intel_connector->base; in intel_dp_pcon_dsc_configure()
3635 hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2; in intel_dp_pcon_dsc_configure()
3637 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) || in intel_dp_pcon_dsc_configure()
3649 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, in intel_dp_pcon_dsc_configure()
3664 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param); in intel_dp_pcon_dsc_configure()
3666 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n"); in intel_dp_pcon_dsc_configure()
3677 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) in intel_dp_configure_protocol_converter()
3680 if (!drm_dp_is_branch(intel_dp->dpcd)) in intel_dp_configure_protocol_converter()
3685 if (drm_dp_dpcd_writeb(&intel_dp->aux, in intel_dp_configure_protocol_converter()
3687 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n", in intel_dp_configure_protocol_converter()
3690 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) { in intel_dp_configure_protocol_converter()
3691 switch (crtc_state->output_format) { in intel_dp_configure_protocol_converter()
3702 MISSING_CASE(crtc_state->output_format); in intel_dp_configure_protocol_converter()
3705 } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) { in intel_dp_configure_protocol_converter()
3706 switch (crtc_state->output_format) { in intel_dp_configure_protocol_converter()
3713 MISSING_CASE(crtc_state->output_format); in intel_dp_configure_protocol_converter()
3720 if (drm_dp_dpcd_writeb(&intel_dp->aux, in intel_dp_configure_protocol_converter()
3722 drm_dbg_kms(&i915->drm, in intel_dp_configure_protocol_converter()
3724 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420)); in intel_dp_configure_protocol_converter()
3728 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0) in intel_dp_configure_protocol_converter()
3729 drm_dbg_kms(&i915->drm, in intel_dp_configure_protocol_converter()
3730 "Failed to %s protocol converter RGB->YCbCr conversion mode\n", in intel_dp_configure_protocol_converter()
3738 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, in intel_dp_get_colorimetry_status()
3749 drm_err(aux->drm_dev, in intel_dp_read_dsc_dpcd()
3755 drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n", in intel_dp_read_dsc_dpcd()
3760 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector) in intel_dp_get_dsc_sink_cap() argument
3762 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_dp_get_dsc_sink_cap()
3768 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); in intel_dp_get_dsc_sink_cap()
3771 connector->dp.fec_capability = 0; in intel_dp_get_dsc_sink_cap()
3776 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, in intel_dp_get_dsc_sink_cap()
3777 connector->dp.dsc_dpcd); in intel_dp_get_dsc_sink_cap()
3779 if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY, in intel_dp_get_dsc_sink_cap()
3780 &connector->dp.fec_capability) < 0) { in intel_dp_get_dsc_sink_cap()
3781 drm_err(&i915->drm, "Failed to read FEC DPCD register\n"); in intel_dp_get_dsc_sink_cap()
3785 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", in intel_dp_get_dsc_sink_cap()
3786 connector->dp.fec_capability); in intel_dp_get_dsc_sink_cap()
3789 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector) in intel_edp_get_dsc_sink_cap() argument
3794 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd); in intel_edp_get_dsc_sink_cap()
3797 static void intel_edp_mso_mode_fixup(struct intel_connector *connector, in intel_edp_mso_mode_fixup() argument
3800 struct intel_dp *intel_dp = intel_attached_dp(connector); in intel_edp_mso_mode_fixup()
3801 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_edp_mso_mode_fixup()
3802 int n = intel_dp->mso_link_count; in intel_edp_mso_mode_fixup()
3803 int overlap = intel_dp->mso_pixel_overlap; in intel_edp_mso_mode_fixup()
3808 mode->hdisplay = (mode->hdisplay - overlap) * n; in intel_edp_mso_mode_fixup()
3809 mode->hsync_start = (mode->hsync_start - overlap) * n; in intel_edp_mso_mode_fixup()
3810 mode->hsync_end = (mode->hsync_end - overlap) * n; in intel_edp_mso_mode_fixup()
3811 mode->htotal = (mode->htotal - overlap) * n; in intel_edp_mso_mode_fixup()
3812 mode->clock *= n; in intel_edp_mso_mode_fixup()
3816 drm_dbg_kms(&i915->drm, in intel_edp_mso_mode_fixup()
3817 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n", in intel_edp_mso_mode_fixup()
3818 connector->base.base.id, connector->base.name, in intel_edp_mso_mode_fixup()
3824 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_edp_fixup_vbt_bpp()
3826 struct intel_connector *connector = intel_dp->attached_connector; in intel_edp_fixup_vbt_bpp() local
3828 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) { in intel_edp_fixup_vbt_bpp()
3842 drm_dbg_kms(&dev_priv->drm, in intel_edp_fixup_vbt_bpp()
3843 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", in intel_edp_fixup_vbt_bpp()
3844 pipe_bpp, connector->panel.vbt.edp.bpp); in intel_edp_fixup_vbt_bpp()
3845 connector->panel.vbt.edp.bpp = pipe_bpp; in intel_edp_fixup_vbt_bpp()
3852 struct intel_connector *connector = intel_dp->attached_connector; in intel_edp_mso_init() local
3853 struct drm_display_info *info = &connector->base.display_info; in intel_edp_mso_init()
3856 if (intel_dp->edp_dpcd[0] < DP_EDP_14) in intel_edp_mso_init()
3859 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) { in intel_edp_mso_init()
3860 drm_err(&i915->drm, "Failed to read MSO cap\n"); in intel_edp_mso_init()
3866 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) { in intel_edp_mso_init()
3867 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso); in intel_edp_mso_init()
3872 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n", in intel_edp_mso_init()
3873 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso, in intel_edp_mso_init()
3874 info->mso_pixel_overlap); in intel_edp_mso_init()
3876 drm_err(&i915->drm, "No source MSO support, disabling\n"); in intel_edp_mso_init()
3881 intel_dp->mso_link_count = mso; in intel_edp_mso_init()
3882 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0; in intel_edp_mso_init()
3886 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) in intel_edp_init_dpcd() argument
3889 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); in intel_edp_init_dpcd()
3892 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); in intel_edp_init_dpcd()
3894 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) in intel_edp_init_dpcd()
3897 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, in intel_edp_init_dpcd()
3898 drm_dp_is_branch(intel_dp->dpcd)); in intel_edp_init_dpcd()
3909 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, in intel_edp_init_dpcd()
3910 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == in intel_edp_init_dpcd()
3911 sizeof(intel_dp->edp_dpcd)) { in intel_edp_init_dpcd()
3912 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n", in intel_edp_init_dpcd()
3913 (int)sizeof(intel_dp->edp_dpcd), in intel_edp_init_dpcd()
3914 intel_dp->edp_dpcd); in intel_edp_init_dpcd()
3916 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14; in intel_edp_init_dpcd()
3920 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks in intel_edp_init_dpcd()
3921 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] in intel_edp_init_dpcd()
3926 intel_dp->num_sink_rates = 0; in intel_edp_init_dpcd()
3929 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { in intel_edp_init_dpcd()
3933 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, in intel_edp_init_dpcd()
3942 /* Value read multiplied by 200kHz gives the per-lane in intel_edp_init_dpcd()
3948 intel_dp->sink_rates[i] = (val * 200) / 10; in intel_edp_init_dpcd()
3950 intel_dp->num_sink_rates = i; in intel_edp_init_dpcd()
3957 if (intel_dp->num_sink_rates) in intel_edp_init_dpcd()
3958 intel_dp->use_rate_select = true; in intel_edp_init_dpcd()
3965 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], in intel_edp_init_dpcd()
3966 connector); in intel_edp_init_dpcd()
3969 * If needed, program our source OUI so we can make various Intel-specific AUX services in intel_edp_init_dpcd()
3980 if (!intel_dp->attached_connector) in intel_dp_has_sink_count()
3983 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base, in intel_dp_has_sink_count()
3984 intel_dp->dpcd, in intel_dp_has_sink_count()
3985 &intel_dp->desc); in intel_dp_has_sink_count()
3997 * Don't clobber cached eDP rates. Also skip re-reading in intel_dp_get_dpcd()
4001 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, in intel_dp_get_dpcd()
4002 drm_dp_is_branch(intel_dp->dpcd)); in intel_dp_get_dpcd()
4010 ret = drm_dp_read_sink_count(&intel_dp->aux); in intel_dp_get_dpcd()
4019 intel_dp->sink_count = ret; in intel_dp_get_dpcd()
4028 if (!intel_dp->sink_count) in intel_dp_get_dpcd()
4032 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd, in intel_dp_get_dpcd()
4033 intel_dp->downstream_ports) == 0; in intel_dp_get_dpcd()
4041 return i915->display.params.enable_dp_mst && in intel_dp_can_mst()
4043 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); in intel_dp_can_mst()
4051 &dp_to_dig_port(intel_dp)->base; in intel_dp_configure_mst()
4052 bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); in intel_dp_configure_mst()
4054 drm_dbg_kms(&i915->drm, in intel_dp_configure_mst()
4056 encoder->base.base.id, encoder->base.name, in intel_dp_configure_mst()
4059 str_yes_no(i915->display.params.enable_dp_mst)); in intel_dp_configure_mst()
4064 intel_dp->is_mst = sink_can_mst && in intel_dp_configure_mst()
4065 i915->display.params.enable_dp_mst; in intel_dp_configure_mst()
4067 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, in intel_dp_configure_mst()
4068 intel_dp->is_mst); in intel_dp_configure_mst()
4074 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4; in intel_dp_get_sink_irq_esi()
4082 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1, in intel_dp_ack_sink_irq_esi()
4095 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication in intel_dp_needs_vsc_sdp()
4097 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP. in intel_dp_needs_vsc_sdp()
4099 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) in intel_dp_needs_vsc_sdp()
4102 switch (conn_state->colorspace) { in intel_dp_needs_vsc_sdp()
4122 return -ENOSPC; in intel_dp_vsc_sdp_pack()
4127 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 in intel_dp_vsc_sdp_pack()
4130 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */ in intel_dp_vsc_sdp_pack()
4131 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */ in intel_dp_vsc_sdp_pack()
4132 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */ in intel_dp_vsc_sdp_pack()
4133 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ in intel_dp_vsc_sdp_pack()
4135 if (vsc->revision == 0x6) { in intel_dp_vsc_sdp_pack()
4136 sdp->db[0] = 1; in intel_dp_vsc_sdp_pack()
4137 sdp->db[3] = 1; in intel_dp_vsc_sdp_pack()
4142 * Format as per DP 1.4a spec and DP 2.0 respectively. in intel_dp_vsc_sdp_pack()
4144 if (!(vsc->revision == 0x5 || vsc->revision == 0x7)) in intel_dp_vsc_sdp_pack()
4149 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */ in intel_dp_vsc_sdp_pack()
4150 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */ in intel_dp_vsc_sdp_pack()
4152 switch (vsc->bpc) { in intel_dp_vsc_sdp_pack()
4157 sdp->db[17] = 0x1; /* DB17[3:0] */ in intel_dp_vsc_sdp_pack()
4160 sdp->db[17] = 0x2; in intel_dp_vsc_sdp_pack()
4163 sdp->db[17] = 0x3; in intel_dp_vsc_sdp_pack()
4166 sdp->db[17] = 0x4; in intel_dp_vsc_sdp_pack()
4169 MISSING_CASE(vsc->bpc); in intel_dp_vsc_sdp_pack()
4173 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) in intel_dp_vsc_sdp_pack()
4174 sdp->db[17] |= 0x80; /* DB17[7] */ in intel_dp_vsc_sdp_pack()
4177 sdp->db[18] = vsc->content_type & 0x7; in intel_dp_vsc_sdp_pack()
4195 return -ENOSPC; in intel_dp_hdr_metadata_infoframe_sdp_pack()
4201 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n"); in intel_dp_hdr_metadata_infoframe_sdp_pack()
4202 return -ENOSPC; in intel_dp_hdr_metadata_infoframe_sdp_pack()
4206 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n"); in intel_dp_hdr_metadata_infoframe_sdp_pack()
4207 return -ENOSPC; in intel_dp_hdr_metadata_infoframe_sdp_pack()
4212 * Prepare VSC Header for SU as per DP 1.4a spec, in intel_dp_hdr_metadata_infoframe_sdp_pack()
4213 * Table 2-100 and Table 2-101 in intel_dp_hdr_metadata_infoframe_sdp_pack()
4216 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */ in intel_dp_hdr_metadata_infoframe_sdp_pack()
4217 sdp->sdp_header.HB0 = 0; in intel_dp_hdr_metadata_infoframe_sdp_pack()
4219 * Packet Type 80h + Non-audio INFOFRAME Type value in intel_dp_hdr_metadata_infoframe_sdp_pack()
4221 * - 80h + Non-audio INFOFRAME Type value in intel_dp_hdr_metadata_infoframe_sdp_pack()
4222 * - InfoFrame Type: 0x07 in intel_dp_hdr_metadata_infoframe_sdp_pack()
4223 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame] in intel_dp_hdr_metadata_infoframe_sdp_pack()
4225 sdp->sdp_header.HB1 = drm_infoframe->type; in intel_dp_hdr_metadata_infoframe_sdp_pack()
4228 * infoframe_size - 1 in intel_dp_hdr_metadata_infoframe_sdp_pack()
4230 sdp->sdp_header.HB2 = 0x1D; in intel_dp_hdr_metadata_infoframe_sdp_pack()
4232 sdp->sdp_header.HB3 = (0x13 << 2); in intel_dp_hdr_metadata_infoframe_sdp_pack()
4234 sdp->db[0] = drm_infoframe->version; in intel_dp_hdr_metadata_infoframe_sdp_pack()
4236 sdp->db[1] = drm_infoframe->length; in intel_dp_hdr_metadata_infoframe_sdp_pack()
4241 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2); in intel_dp_hdr_metadata_infoframe_sdp_pack()
4242 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], in intel_dp_hdr_metadata_infoframe_sdp_pack()
4246 * Size of DP infoframe sdp packet for HDR static metadata consists of in intel_dp_hdr_metadata_infoframe_sdp_pack()
4247 * - DP SDP Header(struct dp_sdp_header): 4 bytes in intel_dp_hdr_metadata_infoframe_sdp_pack()
4248 * - Two Data Blocks: 2 bytes in intel_dp_hdr_metadata_infoframe_sdp_pack()
4251 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes in intel_dp_hdr_metadata_infoframe_sdp_pack()
4253 * Prior to GEN11's GMP register size is identical to DP HDR static metadata in intel_dp_hdr_metadata_infoframe_sdp_pack()
4265 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_write_dp_sdp()
4269 if ((crtc_state->infoframes.enable & in intel_write_dp_sdp()
4275 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp, in intel_write_dp_sdp()
4280 &crtc_state->infoframes.drm.drm, in intel_write_dp_sdp()
4288 if (drm_WARN_ON(&dev_priv->drm, len < 0)) in intel_write_dp_sdp()
4291 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); in intel_write_dp_sdp()
4299 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_write_dp_vsc_sdp()
4305 if (drm_WARN_ON(&dev_priv->drm, len < 0)) in intel_write_dp_vsc_sdp()
4308 dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC, in intel_write_dp_vsc_sdp()
4317 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dp_set_infoframes()
4318 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); in intel_dp_set_infoframes()
4329 if (!crtc_state->has_psr) in intel_dp_set_infoframes()
4339 if (!crtc_state->has_psr) in intel_dp_set_infoframes()
4351 return -EINVAL; in intel_dp_vsc_sdp_unpack()
4355 if (sdp->sdp_header.HB0 != 0) in intel_dp_vsc_sdp_unpack()
4356 return -EINVAL; in intel_dp_vsc_sdp_unpack()
4358 if (sdp->sdp_header.HB1 != DP_SDP_VSC) in intel_dp_vsc_sdp_unpack()
4359 return -EINVAL; in intel_dp_vsc_sdp_unpack()
4361 vsc->sdp_type = sdp->sdp_header.HB1; in intel_dp_vsc_sdp_unpack()
4362 vsc->revision = sdp->sdp_header.HB2; in intel_dp_vsc_sdp_unpack()
4363 vsc->length = sdp->sdp_header.HB3; in intel_dp_vsc_sdp_unpack()
4365 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) || in intel_dp_vsc_sdp_unpack()
4366 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) { in intel_dp_vsc_sdp_unpack()
4368 * - HB2 = 0x2, HB3 = 0x8 in intel_dp_vsc_sdp_unpack()
4370 * - HB2 = 0x4, HB3 = 0xe in intel_dp_vsc_sdp_unpack()
4371 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of in intel_dp_vsc_sdp_unpack()
4376 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) { in intel_dp_vsc_sdp_unpack()
4378 * - HB2 = 0x5, HB3 = 0x13 in intel_dp_vsc_sdp_unpack()
4382 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf; in intel_dp_vsc_sdp_unpack()
4383 vsc->colorimetry = sdp->db[16] & 0xf; in intel_dp_vsc_sdp_unpack()
4384 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1; in intel_dp_vsc_sdp_unpack()
4386 switch (sdp->db[17] & 0x7) { in intel_dp_vsc_sdp_unpack()
4388 vsc->bpc = 6; in intel_dp_vsc_sdp_unpack()
4391 vsc->bpc = 8; in intel_dp_vsc_sdp_unpack()
4394 vsc->bpc = 10; in intel_dp_vsc_sdp_unpack()
4397 vsc->bpc = 12; in intel_dp_vsc_sdp_unpack()
4400 vsc->bpc = 16; in intel_dp_vsc_sdp_unpack()
4403 MISSING_CASE(sdp->db[17] & 0x7); in intel_dp_vsc_sdp_unpack()
4404 return -EINVAL; in intel_dp_vsc_sdp_unpack()
4407 vsc->content_type = sdp->db[18] & 0x7; in intel_dp_vsc_sdp_unpack()
4409 return -EINVAL; in intel_dp_vsc_sdp_unpack()
4424 return -EINVAL; in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4426 if (sdp->sdp_header.HB0 != 0) in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4427 return -EINVAL; in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4429 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM) in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4430 return -EINVAL; in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4436 if (sdp->sdp_header.HB2 != 0x1D) in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4437 return -EINVAL; in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4440 if ((sdp->sdp_header.HB3 & 0x3) != 0) in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4441 return -EINVAL; in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4444 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13) in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4445 return -EINVAL; in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4448 if (sdp->db[0] != 1) in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4449 return -EINVAL; in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4452 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE) in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4453 return -EINVAL; in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4455 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2], in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4466 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_read_dp_vsc_sdp()
4472 if (crtc_state->has_psr) in intel_read_dp_vsc_sdp()
4475 if ((crtc_state->infoframes.enable & in intel_read_dp_vsc_sdp()
4479 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); in intel_read_dp_vsc_sdp()
4484 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n"); in intel_read_dp_vsc_sdp()
4492 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_read_dp_hdr_metadata_infoframe_sdp()
4497 if ((crtc_state->infoframes.enable & in intel_read_dp_hdr_metadata_infoframe_sdp()
4501 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, in intel_read_dp_hdr_metadata_infoframe_sdp()
4508 drm_dbg_kms(&dev_priv->drm, in intel_read_dp_hdr_metadata_infoframe_sdp()
4509 "Failed to unpack DP HDR Metadata Infoframe SDP\n"); in intel_read_dp_hdr_metadata_infoframe_sdp()
4519 &crtc_state->infoframes.vsc); in intel_read_dp_sdp()
4523 &crtc_state->infoframes.drm.drm); in intel_read_dp_sdp()
4537 /* (DP CTS 1.2) in intel_dp_autotest_link_training()
4540 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ in intel_dp_autotest_link_training()
4541 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, in intel_dp_autotest_link_training()
4545 drm_dbg_kms(&i915->drm, "Lane count read failed\n"); in intel_dp_autotest_link_training()
4550 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, in intel_dp_autotest_link_training()
4553 drm_dbg_kms(&i915->drm, "Link Rate read failed\n"); in intel_dp_autotest_link_training()
4563 intel_dp->compliance.test_lane_count = test_lane_count; in intel_dp_autotest_link_training()
4564 intel_dp->compliance.test_link_rate = test_link_rate; in intel_dp_autotest_link_training()
4577 /* Read the TEST_PATTERN (DP CTS 3.1.5) */ in intel_dp_autotest_video_pattern()
4578 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN, in intel_dp_autotest_video_pattern()
4581 drm_dbg_kms(&i915->drm, "Test pattern read failed\n"); in intel_dp_autotest_video_pattern()
4587 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, in intel_dp_autotest_video_pattern()
4590 drm_dbg_kms(&i915->drm, "H Width read failed\n"); in intel_dp_autotest_video_pattern()
4594 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, in intel_dp_autotest_video_pattern()
4597 drm_dbg_kms(&i915->drm, "V Height read failed\n"); in intel_dp_autotest_video_pattern()
4601 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0, in intel_dp_autotest_video_pattern()
4604 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n"); in intel_dp_autotest_video_pattern()
4613 intel_dp->compliance.test_data.bpc = 6; in intel_dp_autotest_video_pattern()
4616 intel_dp->compliance.test_data.bpc = 8; in intel_dp_autotest_video_pattern()
4622 intel_dp->compliance.test_data.video_pattern = test_pattern; in intel_dp_autotest_video_pattern()
4623 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); in intel_dp_autotest_video_pattern()
4624 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); in intel_dp_autotest_video_pattern()
4626 intel_dp->compliance.test_active = true; in intel_dp_autotest_video_pattern()
4635 struct intel_connector *intel_connector = intel_dp->attached_connector; in intel_dp_autotest_edid()
4636 struct drm_connector *connector = &intel_connector->base; in intel_dp_autotest_edid() local
4638 if (intel_connector->detect_edid == NULL || in intel_dp_autotest_edid()
4639 connector->edid_corrupt || in intel_dp_autotest_edid()
4640 intel_dp->aux.i2c_defer_count > 6) { in intel_dp_autotest_edid()
4642 * (DP CTS 1.2 Core r1.1) in intel_dp_autotest_edid()
4648 if (intel_dp->aux.i2c_nack_count > 0 || in intel_dp_autotest_edid()
4649 intel_dp->aux.i2c_defer_count > 0) in intel_dp_autotest_edid()
4650 drm_dbg_kms(&i915->drm, in intel_dp_autotest_edid()
4652 intel_dp->aux.i2c_nack_count, in intel_dp_autotest_edid()
4653 intel_dp->aux.i2c_defer_count); in intel_dp_autotest_edid()
4654 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; in intel_dp_autotest_edid()
4657 const struct edid *block = drm_edid_raw(intel_connector->detect_edid); in intel_dp_autotest_edid()
4660 block += block->extensions; in intel_dp_autotest_edid()
4662 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, in intel_dp_autotest_edid()
4663 block->checksum) <= 0) in intel_dp_autotest_edid()
4664 drm_dbg_kms(&i915->drm, in intel_dp_autotest_edid()
4668 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; in intel_dp_autotest_edid()
4672 intel_dp->compliance.test_active = true; in intel_dp_autotest_edid()
4681 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); in intel_dp_phy_pattern_update()
4683 &intel_dp->compliance.test_data.phytest; in intel_dp_phy_pattern_update()
4684 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dp_phy_pattern_update()
4685 enum pipe pipe = crtc->pipe; in intel_dp_phy_pattern_update()
4688 switch (data->phy_pattern) { in intel_dp_phy_pattern_update()
4690 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n"); in intel_dp_phy_pattern_update()
4694 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n"); in intel_dp_phy_pattern_update()
4699 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n"); in intel_dp_phy_pattern_update()
4705 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n"); in intel_dp_phy_pattern_update()
4712 * current firmware of DPR-100 could not set it, so hardcoding in intel_dp_phy_pattern_update()
4715 drm_dbg_kms(&dev_priv->drm, in intel_dp_phy_pattern_update()
4730 * current firmware of DPR-100 could not set it, so hardcoding in intel_dp_phy_pattern_update()
4733 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n"); in intel_dp_phy_pattern_update()
4749 &intel_dp->compliance.test_data.phytest; in intel_dp_process_phy_request()
4752 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, in intel_dp_process_phy_request()
4754 drm_dbg_kms(&i915->drm, "failed to get link status\n"); in intel_dp_process_phy_request()
4758 /* retrieve vswing & pre-emphasis setting */ in intel_dp_process_phy_request()
4766 drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, in intel_dp_process_phy_request()
4767 intel_dp->train_set, crtc_state->lane_count); in intel_dp_process_phy_request()
4769 drm_dp_set_phy_test_pattern(&intel_dp->aux, data, in intel_dp_process_phy_request()
4770 intel_dp->dpcd[DP_DPCD_REV]); in intel_dp_process_phy_request()
4777 &intel_dp->compliance.test_data.phytest; in intel_dp_autotest_phy_pattern()
4779 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) { in intel_dp_autotest_phy_pattern()
4780 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n"); in intel_dp_autotest_phy_pattern()
4785 intel_dp->compliance.test_active = true; in intel_dp_autotest_phy_pattern()
4797 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); in intel_dp_handle_test_request()
4799 drm_dbg_kms(&i915->drm, in intel_dp_handle_test_request()
4806 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n"); in intel_dp_handle_test_request()
4810 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n"); in intel_dp_handle_test_request()
4814 drm_dbg_kms(&i915->drm, "EDID test requested\n"); in intel_dp_handle_test_request()
4818 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); in intel_dp_handle_test_request()
4822 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n", in intel_dp_handle_test_request()
4828 intel_dp->compliance.test_type = request; in intel_dp_handle_test_request()
4831 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); in intel_dp_handle_test_request()
4833 drm_dbg_kms(&i915->drm, in intel_dp_handle_test_request()
4840 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_dp_link_ok()
4841 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dp_link_ok()
4842 bool uhbr = intel_dp->link_rate >= 1000000; in intel_dp_link_ok()
4847 intel_dp->lane_count); in intel_dp_link_ok()
4849 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); in intel_dp_link_ok()
4855 drm_dbg_kms(&i915->drm, in intel_dp_link_ok()
4857 encoder->base.base.id, encoder->base.name, in intel_dp_link_ok()
4868 drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled); in intel_dp_mst_hpd_irq()
4871 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); in intel_dp_mst_hpd_irq()
4878 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_dp_mst_link_status()
4879 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dp_mst_link_status()
4881 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2; in intel_dp_mst_link_status()
4883 if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status, in intel_dp_mst_link_status()
4885 drm_err(&i915->drm, in intel_dp_mst_link_status()
4887 encoder->base.base.id, encoder->base.name); in intel_dp_mst_link_status()
4895 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4896 * @intel_dp: Intel DP struct
4902 * - %true if pending interrupts were serviced (or no interrupts were
4904 * - %false if an error condition - like AUX failure or a loss of link - is
4913 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0); in intel_dp_check_mst_status()
4920 drm_dbg_kms(&i915->drm, in intel_dp_check_mst_status()
4921 "failed to get ESI - device may have failed\n"); in intel_dp_check_mst_status()
4927 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi); in intel_dp_check_mst_status()
4929 if (intel_dp->active_mst_links > 0 && link_ok && in intel_dp_check_mst_status()
4942 drm_dbg_kms(&i915->drm, "Failed to ack ESI\n"); in intel_dp_check_mst_status()
4945 drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr); in intel_dp_check_mst_status()
4957 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux); in intel_dp_handle_hdmi_link_status_change()
4958 if (intel_dp->frl.is_trained && !is_active) { in intel_dp_handle_hdmi_link_status_change()
4959 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0) in intel_dp_handle_hdmi_link_status_change()
4963 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0) in intel_dp_handle_hdmi_link_status_change()
4966 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base); in intel_dp_handle_hdmi_link_status_change()
4968 intel_dp->frl.is_trained = false; in intel_dp_handle_hdmi_link_status_change()
4980 if (!intel_dp->link_trained) in intel_dp_needs_link_retrain()
4984 * While PSR source HW is enabled, it will control main-link sending in intel_dp_needs_link_retrain()
4994 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, in intel_dp_needs_link_retrain()
4999 * Validate the cached values of intel_dp->link_rate and in intel_dp_needs_link_retrain()
5000 * intel_dp->lane_count before attempting to retrain. in intel_dp_needs_link_retrain()
5006 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, in intel_dp_needs_link_retrain()
5007 intel_dp->lane_count)) in intel_dp_needs_link_retrain()
5021 if (!conn_state->best_encoder) in intel_dp_has_connector()
5025 encoder = &dp_to_dig_port(intel_dp)->base; in intel_dp_has_connector()
5026 if (conn_state->best_encoder == &encoder->base) in intel_dp_has_connector()
5031 encoder = &intel_dp->mst_encoders[pipe]->base; in intel_dp_has_connector()
5032 if (conn_state->best_encoder == &encoder->base) in intel_dp_has_connector()
5045 struct intel_connector *connector; in intel_dp_get_active_pipes() local
5050 drm_connector_list_iter_begin(&i915->drm, &conn_iter); in intel_dp_get_active_pipes()
5051 for_each_intel_connector_iter(connector, &conn_iter) { in intel_dp_get_active_pipes()
5053 connector->base.state; in intel_dp_get_active_pipes()
5060 crtc = to_intel_crtc(conn_state->crtc); in intel_dp_get_active_pipes()
5064 ret = drm_modeset_lock(&crtc->base.mutex, ctx); in intel_dp_get_active_pipes()
5068 crtc_state = to_intel_crtc_state(crtc->base.state); in intel_dp_get_active_pipes()
5070 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); in intel_dp_get_active_pipes()
5072 if (!crtc_state->hw.active) in intel_dp_get_active_pipes()
5075 if (conn_state->commit && in intel_dp_get_active_pipes()
5076 !try_wait_for_completion(&conn_state->commit->hw_done)) in intel_dp_get_active_pipes()
5079 *pipe_mask |= BIT(crtc->pipe); in intel_dp_get_active_pipes()
5088 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_is_connected() local
5090 return connector->base.status == connector_status_connected || in intel_dp_is_connected()
5091 intel_dp->is_mst; in intel_dp_is_connected()
5097 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dp_retrain_link()
5106 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, in intel_dp_retrain_link()
5124 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n", in intel_dp_retrain_link()
5125 encoder->base.base.id, encoder->base.name); in intel_dp_retrain_link()
5127 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { in intel_dp_retrain_link()
5129 to_intel_crtc_state(crtc->base.state); in intel_dp_retrain_link()
5131 /* Suppress underruns caused by re-training */ in intel_dp_retrain_link()
5132 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); in intel_dp_retrain_link()
5133 if (crtc_state->has_pch_encoder) in intel_dp_retrain_link()
5138 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { in intel_dp_retrain_link()
5140 to_intel_crtc_state(crtc->base.state); in intel_dp_retrain_link()
5155 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { in intel_dp_retrain_link()
5157 to_intel_crtc_state(crtc->base.state); in intel_dp_retrain_link()
5162 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); in intel_dp_retrain_link()
5163 if (crtc_state->has_pch_encoder) in intel_dp_retrain_link()
5177 struct intel_connector *connector; in intel_dp_prep_phy_test() local
5182 drm_connector_list_iter_begin(&i915->drm, &conn_iter); in intel_dp_prep_phy_test()
5183 for_each_intel_connector_iter(connector, &conn_iter) { in intel_dp_prep_phy_test()
5185 connector->base.state; in intel_dp_prep_phy_test()
5192 crtc = to_intel_crtc(conn_state->crtc); in intel_dp_prep_phy_test()
5196 ret = drm_modeset_lock(&crtc->base.mutex, ctx); in intel_dp_prep_phy_test()
5200 crtc_state = to_intel_crtc_state(crtc->base.state); in intel_dp_prep_phy_test()
5202 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); in intel_dp_prep_phy_test()
5204 if (!crtc_state->hw.active) in intel_dp_prep_phy_test()
5207 if (conn_state->commit && in intel_dp_prep_phy_test()
5208 !try_wait_for_completion(&conn_state->commit->hw_done)) in intel_dp_prep_phy_test()
5211 *pipe_mask |= BIT(crtc->pipe); in intel_dp_prep_phy_test()
5221 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dp_do_phy_test()
5227 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, in intel_dp_do_phy_test()
5239 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n", in intel_dp_do_phy_test()
5240 encoder->base.base.id, encoder->base.name); in intel_dp_do_phy_test()
5242 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { in intel_dp_do_phy_test()
5244 to_intel_crtc_state(crtc->base.state); in intel_dp_do_phy_test()
5269 if (ret == -EDEADLK) { in intel_dp_phy_test()
5279 drm_WARN(encoder->base.dev, ret, in intel_dp_phy_test()
5288 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_check_device_service_irq()
5291 if (drm_dp_dpcd_readb(&intel_dp->aux, in intel_dp_check_device_service_irq()
5295 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); in intel_dp_check_device_service_irq()
5301 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); in intel_dp_check_device_service_irq()
5304 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n"); in intel_dp_check_device_service_irq()
5311 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_check_link_service_irq()
5314 if (drm_dp_dpcd_readb(&intel_dp->aux, in intel_dp_check_link_service_irq()
5318 if (drm_dp_dpcd_writeb(&intel_dp->aux, in intel_dp_check_link_service_irq()
5327 * According to DP spec
5332 * 4. Check link status on receipt of hot-plug interrupt
5334 * intel_dp_short_pulse - handles short pulse interrupts
5343 u8 old_sink_count = intel_dp->sink_count; in intel_dp_short_pulse()
5350 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); in intel_dp_short_pulse()
5360 if ((old_sink_count != intel_dp->sink_count) || !ret) { in intel_dp_short_pulse()
5369 drm_dp_cec_irq(&intel_dp->aux); in intel_dp_short_pulse()
5377 switch (intel_dp->compliance.test_type) { in intel_dp_short_pulse()
5379 drm_dbg_kms(&dev_priv->drm, in intel_dp_short_pulse()
5382 drm_kms_helper_hotplug_event(&dev_priv->drm); in intel_dp_short_pulse()
5385 drm_dbg_kms(&dev_priv->drm, in intel_dp_short_pulse()
5390 * FIXME get rid of the ad-hoc phy test modeset code in intel_dp_short_pulse()
5405 u8 *dpcd = intel_dp->dpcd; in intel_dp_detect_dpcd()
5408 if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp))) in intel_dp_detect_dpcd()
5420 /* If we're HPD-aware, SINK_COUNT changes dynamically */ in intel_dp_detect_dpcd()
5422 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { in intel_dp_detect_dpcd()
5423 return intel_dp->sink_count ? in intel_dp_detect_dpcd()
5431 if (drm_probe_ddc(&intel_dp->aux.ddc)) in intel_dp_detect_dpcd()
5435 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { in intel_dp_detect_dpcd()
5436 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; in intel_dp_detect_dpcd()
5441 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & in intel_dp_detect_dpcd()
5449 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n"); in intel_dp_detect_dpcd()
5460 * intel_digital_port_connected - is the specified port connected?
5463 * In cases where there's a connector physically connected but it can't be used
5465 * pretty much treat the port as disconnected. This is relevant for type-C
5472 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_digital_port_connected()
5478 is_connected = dig_port->connected(encoder); in intel_digital_port_connected()
5486 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_get_edid() local
5487 const struct drm_edid *fixed_edid = connector->panel.fixed_edid; in intel_dp_get_edid()
5498 return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc); in intel_dp_get_edid()
5506 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_update_dfp() local
5508 intel_dp->dfp.max_bpc = in intel_dp_update_dfp()
5509 drm_dp_downstream_max_bpc(intel_dp->dpcd, in intel_dp_update_dfp()
5510 intel_dp->downstream_ports, drm_edid); in intel_dp_update_dfp()
5512 intel_dp->dfp.max_dotclock = in intel_dp_update_dfp()
5513 drm_dp_downstream_max_dotclock(intel_dp->dpcd, in intel_dp_update_dfp()
5514 intel_dp->downstream_ports); in intel_dp_update_dfp()
5516 intel_dp->dfp.min_tmds_clock = in intel_dp_update_dfp()
5517 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd, in intel_dp_update_dfp()
5518 intel_dp->downstream_ports, in intel_dp_update_dfp()
5520 intel_dp->dfp.max_tmds_clock = in intel_dp_update_dfp()
5521 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd, in intel_dp_update_dfp()
5522 intel_dp->downstream_ports, in intel_dp_update_dfp()
5525 intel_dp->dfp.pcon_max_frl_bw = in intel_dp_update_dfp()
5526 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, in intel_dp_update_dfp()
5527 intel_dp->downstream_ports); in intel_dp_update_dfp()
5529 drm_dbg_kms(&i915->drm, in intel_dp_update_dfp()
5530 … "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n", in intel_dp_update_dfp()
5531 connector->base.base.id, connector->base.name, in intel_dp_update_dfp()
5532 intel_dp->dfp.max_bpc, in intel_dp_update_dfp()
5533 intel_dp->dfp.max_dotclock, in intel_dp_update_dfp()
5534 intel_dp->dfp.min_tmds_clock, in intel_dp_update_dfp()
5535 intel_dp->dfp.max_tmds_clock, in intel_dp_update_dfp()
5536 intel_dp->dfp.pcon_max_frl_bw); in intel_dp_update_dfp()
5545 (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough)) in intel_dp_can_ycbcr420()
5563 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_update_420() local
5565 intel_dp->dfp.ycbcr420_passthrough = in intel_dp_update_420()
5566 drm_dp_downstream_420_passthrough(intel_dp->dpcd, in intel_dp_update_420()
5567 intel_dp->downstream_ports); in intel_dp_update_420()
5568 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ in intel_dp_update_420()
5569 intel_dp->dfp.ycbcr_444_to_420 = in intel_dp_update_420()
5570 dp_to_dig_port(intel_dp)->lspcon.active || in intel_dp_update_420()
5571 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, in intel_dp_update_420()
5572 intel_dp->downstream_ports); in intel_dp_update_420()
5573 intel_dp->dfp.rgb_to_ycbcr = in intel_dp_update_420()
5574 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, in intel_dp_update_420()
5575 intel_dp->downstream_ports, in intel_dp_update_420()
5578 connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp); in intel_dp_update_420()
5580 drm_dbg_kms(&i915->drm, in intel_dp_update_420()
5581 …"[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversi… in intel_dp_update_420()
5582 connector->base.base.id, connector->base.name, in intel_dp_update_420()
5583 str_yes_no(intel_dp->dfp.rgb_to_ycbcr), in intel_dp_update_420()
5584 str_yes_no(connector->base.ycbcr_420_allowed), in intel_dp_update_420()
5585 str_yes_no(intel_dp->dfp.ycbcr_444_to_420)); in intel_dp_update_420()
5592 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_set_edid() local
5598 connector->detect_edid = drm_edid; in intel_dp_set_edid()
5601 drm_edid_connector_update(&connector->base, drm_edid); in intel_dp_set_edid()
5603 vrr_capable = intel_vrr_is_capable(connector); in intel_dp_set_edid()
5604 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n", in intel_dp_set_edid()
5605 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable)); in intel_dp_set_edid()
5606 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable); in intel_dp_set_edid()
5611 drm_dp_cec_attach(&intel_dp->aux, in intel_dp_set_edid()
5612 connector->base.display_info.source_physical_address); in intel_dp_set_edid()
5618 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_unset_edid() local
5620 drm_dp_cec_unset_edid(&intel_dp->aux); in intel_dp_unset_edid()
5621 drm_edid_free(connector->detect_edid); in intel_dp_unset_edid()
5622 connector->detect_edid = NULL; in intel_dp_unset_edid()
5624 intel_dp->dfp.max_bpc = 0; in intel_dp_unset_edid()
5625 intel_dp->dfp.max_dotclock = 0; in intel_dp_unset_edid()
5626 intel_dp->dfp.min_tmds_clock = 0; in intel_dp_unset_edid()
5627 intel_dp->dfp.max_tmds_clock = 0; in intel_dp_unset_edid()
5629 intel_dp->dfp.pcon_max_frl_bw = 0; in intel_dp_unset_edid()
5631 intel_dp->dfp.ycbcr_444_to_420 = false; in intel_dp_unset_edid()
5632 connector->base.ycbcr_420_allowed = false; in intel_dp_unset_edid()
5634 drm_connector_set_vrr_capable_property(&connector->base, in intel_dp_unset_edid()
5639 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector) in intel_dp_detect_dsc_caps() argument
5643 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ in intel_dp_detect_dsc_caps()
5648 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], in intel_dp_detect_dsc_caps()
5649 connector); in intel_dp_detect_dsc_caps()
5651 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], in intel_dp_detect_dsc_caps()
5652 connector); in intel_dp_detect_dsc_caps()
5656 intel_dp_detect(struct drm_connector *connector, in intel_dp_detect() argument
5660 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_dp_detect()
5662 to_intel_connector(connector); in intel_dp_detect()
5665 struct intel_encoder *encoder = &dig_port->base; in intel_dp_detect()
5668 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", in intel_dp_detect()
5669 connector->base.id, connector->name); in intel_dp_detect()
5670 drm_WARN_ON(&dev_priv->drm, in intel_dp_detect()
5671 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); in intel_dp_detect()
5685 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); in intel_dp_detect()
5686 memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd)); in intel_dp_detect()
5687 intel_dp->psr.sink_panel_replay_support = false; in intel_dp_detect()
5689 if (intel_dp->is_mst) { in intel_dp_detect()
5690 drm_dbg_kms(&dev_priv->drm, in intel_dp_detect()
5692 intel_dp->is_mst, in intel_dp_detect()
5693 intel_dp->mst_mgr.mst_state); in intel_dp_detect()
5694 intel_dp->is_mst = false; in intel_dp_detect()
5695 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, in intel_dp_detect()
5696 intel_dp->is_mst); in intel_dp_detect()
5713 if (intel_dp->reset_link_params || intel_dp->is_mst) { in intel_dp_detect()
5715 intel_dp->reset_link_params = false; in intel_dp_detect()
5720 if (intel_dp->is_mst) { in intel_dp_detect()
5722 * If we are in MST mode then this connector in intel_dp_detect()
5747 intel_dp->aux.i2c_nack_count = 0; in intel_dp_detect()
5748 intel_dp->aux.i2c_defer_count = 0; in intel_dp_detect()
5752 to_intel_connector(connector)->detect_edid) in intel_dp_detect()
5758 if (status != connector_status_connected && !intel_dp->is_mst) in intel_dp_detect()
5762 drm_dp_set_subconnector_property(connector, in intel_dp_detect()
5764 intel_dp->dpcd, in intel_dp_detect()
5765 intel_dp->downstream_ports); in intel_dp_detect()
5770 intel_dp_force(struct drm_connector *connector) in intel_dp_force() argument
5772 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); in intel_dp_force()
5774 struct intel_encoder *intel_encoder = &dig_port->base; in intel_dp_force()
5775 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); in intel_dp_force()
5777 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", in intel_dp_force()
5778 connector->base.id, connector->name); in intel_dp_force()
5781 if (connector->status != connector_status_connected) in intel_dp_force()
5787 static int intel_dp_get_modes(struct drm_connector *connector) in intel_dp_get_modes() argument
5789 struct intel_connector *intel_connector = to_intel_connector(connector); in intel_dp_get_modes()
5792 /* drm_edid_connector_update() done in ->detect() or ->force() */ in intel_dp_get_modes()
5793 num_modes = drm_edid_connector_add_modes(connector); in intel_dp_get_modes()
5802 if (!intel_connector->detect_edid) { in intel_dp_get_modes()
5806 mode = drm_dp_downstream_mode(connector->dev, in intel_dp_get_modes()
5807 intel_dp->dpcd, in intel_dp_get_modes()
5808 intel_dp->downstream_ports); in intel_dp_get_modes()
5810 drm_mode_probed_add(connector, mode); in intel_dp_get_modes()
5819 intel_dp_connector_register(struct drm_connector *connector) in intel_dp_connector_register() argument
5821 struct drm_i915_private *i915 = to_i915(connector->dev); in intel_dp_connector_register()
5822 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); in intel_dp_connector_register()
5824 struct intel_lspcon *lspcon = &dig_port->lspcon; in intel_dp_connector_register()
5827 ret = intel_connector_register(connector); in intel_dp_connector_register()
5831 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n", in intel_dp_connector_register()
5832 intel_dp->aux.name, connector->kdev->kobj.name); in intel_dp_connector_register()
5834 intel_dp->aux.dev = connector->kdev; in intel_dp_connector_register()
5835 ret = drm_dp_aux_register(&intel_dp->aux); in intel_dp_connector_register()
5837 drm_dp_cec_register_connector(&intel_dp->aux, connector); in intel_dp_connector_register()
5839 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata)) in intel_dp_connector_register()
5848 if (lspcon->hdr_supported) in intel_dp_connector_register()
5849 drm_connector_attach_hdr_output_metadata_property(connector); in intel_dp_connector_register()
5856 intel_dp_connector_unregister(struct drm_connector *connector) in intel_dp_connector_unregister() argument
5858 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); in intel_dp_connector_unregister()
5860 drm_dp_cec_unregister_connector(&intel_dp->aux); in intel_dp_connector_unregister()
5861 drm_dp_aux_unregister(&intel_dp->aux); in intel_dp_connector_unregister()
5862 intel_connector_unregister(connector); in intel_dp_connector_unregister()
5865 void intel_dp_connector_sync_state(struct intel_connector *connector, in intel_dp_connector_sync_state() argument
5868 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_dp_connector_sync_state()
5870 if (crtc_state && crtc_state->dsc.compression_enable) { in intel_dp_connector_sync_state()
5871 drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux); in intel_dp_connector_sync_state()
5872 connector->dp.dsc_decompression_enabled = true; in intel_dp_connector_sync_state()
5874 connector->dp.dsc_decompression_enabled = false; in intel_dp_connector_sync_state()
5881 struct intel_dp *intel_dp = &dig_port->dp; in intel_dp_encoder_flush_work()
5913 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_tile_group()
5915 struct drm_connector *connector; in intel_modeset_tile_group() local
5918 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); in intel_modeset_tile_group()
5919 drm_for_each_connector_iter(connector, &conn_iter) { in intel_modeset_tile_group()
5924 if (!connector->has_tile || in intel_modeset_tile_group()
5925 connector->tile_group->id != tile_group_id) in intel_modeset_tile_group()
5928 conn_state = drm_atomic_get_connector_state(&state->base, in intel_modeset_tile_group()
5929 connector); in intel_modeset_tile_group()
5935 crtc = to_intel_crtc(conn_state->crtc); in intel_modeset_tile_group()
5941 crtc_state->uapi.mode_changed = true; in intel_modeset_tile_group()
5943 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); in intel_modeset_tile_group()
5954 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_affected_transcoders()
5960 for_each_intel_crtc(&dev_priv->drm, crtc) { in intel_modeset_affected_transcoders()
5964 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in intel_modeset_affected_transcoders()
5968 if (!crtc_state->hw.enable) in intel_modeset_affected_transcoders()
5971 if (!(transcoders & BIT(crtc_state->cpu_transcoder))) in intel_modeset_affected_transcoders()
5974 crtc_state->uapi.mode_changed = true; in intel_modeset_affected_transcoders()
5976 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); in intel_modeset_affected_transcoders()
5980 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); in intel_modeset_affected_transcoders()
5984 transcoders &= ~BIT(crtc_state->cpu_transcoder); in intel_modeset_affected_transcoders()
5987 drm_WARN_ON(&dev_priv->drm, transcoders != 0); in intel_modeset_affected_transcoders()
5993 struct drm_connector *connector) in intel_modeset_synced_crtcs() argument
5996 drm_atomic_get_old_connector_state(&state->base, connector); in intel_modeset_synced_crtcs()
6001 crtc = to_intel_crtc(old_conn_state->crtc); in intel_modeset_synced_crtcs()
6007 if (!old_crtc_state->hw.active) in intel_modeset_synced_crtcs()
6010 transcoders = old_crtc_state->sync_mode_slaves_mask; in intel_modeset_synced_crtcs()
6011 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER) in intel_modeset_synced_crtcs()
6012 transcoders |= BIT(old_crtc_state->master_transcoder); in intel_modeset_synced_crtcs()
6021 struct drm_i915_private *dev_priv = to_i915(conn->dev); in intel_dp_connector_atomic_check()
6025 struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder); in intel_dp_connector_atomic_check()
6028 ret = intel_digital_connector_atomic_check(conn, &state->base); in intel_dp_connector_atomic_check()
6033 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr); in intel_dp_connector_atomic_check()
6048 if (conn->has_tile) { in intel_dp_connector_atomic_check()
6049 ret = intel_modeset_tile_group(state, conn->tile_group->id); in intel_dp_connector_atomic_check()
6057 static void intel_dp_oob_hotplug_event(struct drm_connector *connector, in intel_dp_oob_hotplug_event() argument
6060 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); in intel_dp_oob_hotplug_event()
6061 struct drm_i915_private *i915 = to_i915(connector->dev); in intel_dp_oob_hotplug_event()
6063 unsigned int hpd_pin = encoder->hpd_pin; in intel_dp_oob_hotplug_event()
6066 spin_lock_irq(&i915->irq_lock); in intel_dp_oob_hotplug_event()
6067 if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) { in intel_dp_oob_hotplug_event()
6068 i915->display.hotplug.event_bits |= BIT(hpd_pin); in intel_dp_oob_hotplug_event()
6070 __assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high); in intel_dp_oob_hotplug_event()
6073 spin_unlock_irq(&i915->irq_lock); in intel_dp_oob_hotplug_event()
6076 queue_delayed_work(i915->unordered_wq, &i915->display.hotplug.hotplug_work, 0); in intel_dp_oob_hotplug_event()
6102 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_dp_hpd_pulse()
6103 struct intel_dp *intel_dp = &dig_port->dp; in intel_dp_hpd_pulse()
6105 if (dig_port->base.type == INTEL_OUTPUT_EDP && in intel_dp_hpd_pulse()
6111 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..." in intel_dp_hpd_pulse()
6113 drm_dbg_kms(&i915->drm, in intel_dp_hpd_pulse()
6116 dig_port->base.base.base.id, in intel_dp_hpd_pulse()
6117 dig_port->base.base.name); in intel_dp_hpd_pulse()
6121 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", in intel_dp_hpd_pulse()
6122 dig_port->base.base.base.id, in intel_dp_hpd_pulse()
6123 dig_port->base.base.name, in intel_dp_hpd_pulse()
6127 intel_dp->reset_link_params = true; in intel_dp_hpd_pulse()
6131 if (intel_dp->is_mst) { in intel_dp_hpd_pulse()
6169 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in has_gamut_metadata_dip()
6170 enum port port = encoder->port; in has_gamut_metadata_dip()
6172 if (intel_bios_encoder_is_lspcon(encoder->devdata)) in has_gamut_metadata_dip()
6189 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) in intel_dp_add_properties() argument
6191 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_dp_add_properties()
6192 enum port port = dp_to_dig_port(intel_dp)->base.port; in intel_dp_add_properties()
6195 drm_connector_attach_dp_subconnector_property(connector); in intel_dp_add_properties()
6198 intel_attach_force_audio_property(connector); in intel_dp_add_properties()
6200 intel_attach_broadcast_rgb_property(connector); in intel_dp_add_properties()
6202 drm_connector_attach_max_bpc_property(connector, 6, 10); in intel_dp_add_properties()
6204 drm_connector_attach_max_bpc_property(connector, 6, 12); in intel_dp_add_properties()
6207 if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) { in intel_dp_add_properties()
6208 drm_connector_attach_content_type_property(connector); in intel_dp_add_properties()
6209 intel_attach_hdmi_colorspace_property(connector); in intel_dp_add_properties()
6211 intel_attach_dp_colorspace_property(connector); in intel_dp_add_properties()
6214 if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base)) in intel_dp_add_properties()
6215 drm_connector_attach_hdr_output_metadata_property(connector); in intel_dp_add_properties()
6218 drm_connector_attach_vrr_capable_property(connector); in intel_dp_add_properties()
6224 struct intel_connector *connector = intel_dp->attached_connector; in intel_edp_add_properties() local
6225 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_edp_add_properties()
6227 intel_panel_preferred_fixed_mode(connector); in intel_edp_add_properties()
6229 intel_attach_scaling_mode_property(&connector->base); in intel_edp_add_properties()
6231 drm_connector_set_panel_orientation_with_quirk(&connector->base, in intel_edp_add_properties()
6232 i915->display.vbt.orientation, in intel_edp_add_properties()
6233 fixed_mode->hdisplay, in intel_edp_add_properties()
6234 fixed_mode->vdisplay); in intel_edp_add_properties()
6238 struct intel_connector *connector) in intel_edp_backlight_setup() argument
6252 pipe = intel_dp->pps.pps_pipe; in intel_edp_backlight_setup()
6258 intel_backlight_setup(connector, pipe); in intel_edp_backlight_setup()
6265 struct drm_connector *connector = &intel_connector->base; in intel_edp_init_connector() local
6267 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_edp_init_connector()
6278 * with an already powered-on LVDS power sequencer. in intel_edp_init_connector()
6281 drm_WARN_ON(&dev_priv->drm, in intel_edp_init_connector()
6283 drm_info(&dev_priv->drm, in intel_edp_init_connector()
6289 intel_bios_init_panel_early(dev_priv, &intel_connector->panel, in intel_edp_init_connector()
6290 encoder->devdata); in intel_edp_init_connector()
6293 drm_info(&dev_priv->drm, in intel_edp_init_connector()
6295 encoder->base.base.id, encoder->base.name); in intel_edp_init_connector()
6318 drm_info(&dev_priv->drm, in intel_edp_init_connector()
6320 encoder->base.base.id, encoder->base.name); in intel_edp_init_connector()
6332 if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) { in intel_edp_init_connector()
6341 drm_info(&dev_priv->drm, in intel_edp_init_connector()
6343 encoder->base.base.id, encoder->base.name); in intel_edp_init_connector()
6349 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall in intel_edp_init_connector()
6353 if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) && in intel_edp_init_connector()
6354 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) == in intel_edp_init_connector()
6356 drm_info(&dev_priv->drm, in intel_edp_init_connector()
6358 encoder->base.base.id, encoder->base.name); in intel_edp_init_connector()
6363 mutex_lock(&dev_priv->drm.mode_config.mutex); in intel_edp_init_connector()
6364 drm_edid = drm_edid_read_ddc(connector, connector->ddc); in intel_edp_init_connector()
6369 drm_dbg_kms(&dev_priv->drm, in intel_edp_init_connector()
6370 "[CONNECTOR:%d:%s] Using OpRegion EDID\n", in intel_edp_init_connector()
6371 connector->base.id, connector->name); in intel_edp_init_connector()
6374 if (drm_edid_connector_update(connector, drm_edid) || in intel_edp_init_connector()
6375 !drm_edid_connector_add_modes(connector)) { in intel_edp_init_connector()
6376 drm_edid_connector_update(connector, NULL); in intel_edp_init_connector()
6378 drm_edid = ERR_PTR(-EINVAL); in intel_edp_init_connector()
6381 drm_edid = ERR_PTR(-ENOENT); in intel_edp_init_connector()
6384 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata, in intel_edp_init_connector()
6393 list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head) in intel_edp_init_connector()
6400 mutex_unlock(&dev_priv->drm.mode_config.mutex); in intel_edp_init_connector()
6403 drm_info(&dev_priv->drm, in intel_edp_init_connector()
6405 encoder->base.base.id, encoder->base.name); in intel_edp_init_connector()
6428 struct drm_connector *connector; in intel_dp_modeset_retry_work_fn() local
6432 connector = &intel_connector->base; in intel_dp_modeset_retry_work_fn()
6433 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id, in intel_dp_modeset_retry_work_fn()
6434 connector->name); in intel_dp_modeset_retry_work_fn()
6436 /* Grab the locks before changing connector property*/ in intel_dp_modeset_retry_work_fn()
6437 mutex_lock(&connector->dev->mode_config.mutex); in intel_dp_modeset_retry_work_fn()
6438 /* Set connector link status to BAD and send a Uevent to notify in intel_dp_modeset_retry_work_fn()
6441 drm_connector_set_link_status_property(connector, in intel_dp_modeset_retry_work_fn()
6443 mutex_unlock(&connector->dev->mode_config.mutex); in intel_dp_modeset_retry_work_fn()
6445 drm_kms_helper_connector_hotplug_event(connector); in intel_dp_modeset_retry_work_fn()
6452 struct drm_connector *connector = &intel_connector->base; in intel_dp_init_connector() local
6453 struct intel_dp *intel_dp = &dig_port->dp; in intel_dp_init_connector()
6454 struct intel_encoder *intel_encoder = &dig_port->base; in intel_dp_init_connector()
6455 struct drm_device *dev = intel_encoder->base.dev; in intel_dp_init_connector()
6457 enum port port = intel_encoder->port; in intel_dp_init_connector()
6462 INIT_WORK(&intel_connector->modeset_retry_work, in intel_dp_init_connector()
6465 if (drm_WARN(dev, dig_port->max_lanes < 1, in intel_dp_init_connector()
6466 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", in intel_dp_init_connector()
6467 dig_port->max_lanes, intel_encoder->base.base.id, in intel_dp_init_connector()
6468 intel_encoder->base.name)) in intel_dp_init_connector()
6471 intel_dp->reset_link_params = true; in intel_dp_init_connector()
6472 intel_dp->pps.pps_pipe = INVALID_PIPE; in intel_dp_init_connector()
6473 intel_dp->pps.active_pipe = INVALID_PIPE; in intel_dp_init_connector()
6476 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); in intel_dp_init_connector()
6477 intel_dp->attached_connector = intel_connector; in intel_dp_init_connector()
6479 if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) { in intel_dp_init_connector()
6486 intel_encoder->type = INTEL_OUTPUT_EDP; in intel_dp_init_connector()
6501 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp); in intel_dp_init_connector()
6504 intel_connector->dp.dsc_decompression_aux = &intel_dp->aux; in intel_dp_init_connector()
6506 drm_dbg_kms(&dev_priv->drm, in intel_dp_init_connector()
6507 "Adding %s connector on [ENCODER:%d:%s]\n", in intel_dp_init_connector()
6508 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", in intel_dp_init_connector()
6509 intel_encoder->base.base.id, intel_encoder->base.name); in intel_dp_init_connector()
6511 drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs, in intel_dp_init_connector()
6512 type, &intel_dp->aux.ddc); in intel_dp_init_connector()
6513 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); in intel_dp_init_connector()
6516 connector->interlace_allowed = true; in intel_dp_init_connector()
6518 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; in intel_dp_init_connector()
6523 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; in intel_dp_init_connector()
6525 intel_connector->get_hw_state = intel_connector_get_hw_state; in intel_dp_init_connector()
6538 intel_connector->base.base.id); in intel_dp_init_connector()
6540 intel_dp_add_properties(intel_dp, connector); in intel_dp_init_connector()
6545 drm_dbg_kms(&dev_priv->drm, in intel_dp_init_connector()
6549 intel_dp->frl.is_trained = false; in intel_dp_init_connector()
6550 intel_dp->frl.trained_rate_gbps = 0; in intel_dp_init_connector()
6558 drm_connector_cleanup(connector); in intel_dp_init_connector()
6570 for_each_intel_encoder(&dev_priv->drm, encoder) { in intel_dp_mst_suspend()
6573 if (encoder->type != INTEL_OUTPUT_DDI) in intel_dp_mst_suspend()
6581 if (intel_dp->is_mst) in intel_dp_mst_suspend()
6582 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr); in intel_dp_mst_suspend()
6593 for_each_intel_encoder(&dev_priv->drm, encoder) { in intel_dp_mst_resume()
6597 if (encoder->type != INTEL_OUTPUT_DDI) in intel_dp_mst_resume()
6605 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr, in intel_dp_mst_resume()
6608 intel_dp->is_mst = false; in intel_dp_mst_resume()
6609 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, in intel_dp_mst_resume()