38  * low-power state and comes back to normal.
71 	return i915->display.dmc.dmc;  in i915_to_dmc()
84  * unversioned file names.
146 #define PIPE_TO_DMC_ID(pipe)		 (DMC_FW_PIPEA + ((pipe) - PIPE_A))
201 	/* Sub-stepping (0, 1, ..., *). * is a wildcard */
300 	return dmc && dmc->dmc_info[dmc_id].payload;  in has_dmc_id_fw()
314 	si->stepping = step_name[0];  in intel_get_stepping_info()
315 	si->substepping = step_name[1];  in intel_get_stepping_info()
342 	/* TODO: disable the event handlers on pre-GEN12 platforms as well */  in disable_all_event_handlers()
364 	 * Wa_16015201720:adl-p,dg2  in adlp_pipedmc_clock_gating_wa()
426 			       enum intel_dmc_id dmc_id, i915_reg_t reg)  in is_dmc_evt_ctl_reg()  argument
428 	u32 offset = i915_mmio_reg_offset(reg);  in is_dmc_evt_ctl_reg()
436 			       enum intel_dmc_id dmc_id, i915_reg_t reg)  in is_dmc_evt_htp_reg()  argument
438 	u32 offset = i915_mmio_reg_offset(reg);  in is_dmc_evt_htp_reg()
447 			    i915_reg_t reg, u32 data)  in disable_dmc_evt()  argument
449 	if (!is_dmc_evt_ctl_reg(i915, dmc_id, reg))  in disable_dmc_evt()
474 			    dmc->dmc_info[dmc_id].mmioaddr[i],  in dmc_mmiodata()
475 			    dmc->dmc_info[dmc_id].mmiodata[i]))  in dmc_mmiodata()
481 		return dmc->dmc_info[dmc_id].mmiodata[i];  in dmc_mmiodata()
485  * intel_dmc_load_program() - write the firmware from memory to register.
494 	struct i915_power_domains *power_domains = &i915->display.power.domains;  in intel_dmc_load_program()
506 	assert_rpm_wakelock_held(&i915->runtime_pm);  in intel_dmc_load_program()
511 		for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) {  in intel_dmc_load_program()
513 					  DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i),  in intel_dmc_load_program()
514 					  dmc->dmc_info[dmc_id].payload[i]);  in intel_dmc_load_program()
521 		for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {  in intel_dmc_load_program()
522 			intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i],  in intel_dmc_load_program()
527 	power_domains->dc_state = 0;  in intel_dmc_load_program()
535  * intel_dmc_disable_program() - disable the firmware
555 	drm_WARN_ONCE(&i915->drm, !dmc, "DMC not initialized\n");  in assert_dmc_loaded()
556 	drm_WARN_ONCE(&i915->drm, dmc &&  in assert_dmc_loaded()
557 		      !intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),  in assert_dmc_loaded()
559 	drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE),  in assert_dmc_loaded()
561 	drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL),  in assert_dmc_loaded()
568 	if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) ||  in fw_info_matches_stepping()
569 	    (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) ||  in fw_info_matches_stepping()
575 	    (si->stepping == '*' && si->substepping == fw_info->substepping) ||  in fw_info_matches_stepping()
576 	    (fw_info->stepping == '*' && fw_info->substepping == '*'))  in fw_info_matches_stepping()
592 	struct drm_i915_private *i915 = dmc->i915;  in dmc_set_fw_offset()
600 			drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", dmc_id);  in dmc_set_fw_offset()
608 		if (dmc->dmc_info[dmc_id].present)  in dmc_set_fw_offset()
612 			dmc->dmc_info[dmc_id].present = true;  in dmc_set_fw_offset()
613 			dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset;  in dmc_set_fw_offset()
622 	struct drm_i915_private *i915 = dmc->i915;  in dmc_mmio_addr_sanity_check()
639 		drm_warn(&i915->drm, "Unknown mmio range for sanity check");  in dmc_mmio_addr_sanity_check()
655 	struct drm_i915_private *i915 = dmc->i915;  in parse_dmc_fw_header()
656 	struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];  in parse_dmc_fw_header()
662 	BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||  in parse_dmc_fw_header()
663 		     ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);  in parse_dmc_fw_header()
673 	if (dmc_header->header_ver == 3) {  in parse_dmc_fw_header()
680 		mmioaddr = v3->mmioaddr;  in parse_dmc_fw_header()
681 		mmiodata = v3->mmiodata;  in parse_dmc_fw_header()
682 		mmio_count = v3->mmio_count;  in parse_dmc_fw_header()
685 		header_len_bytes = dmc_header->header_len * 4;  in parse_dmc_fw_header()
686 		start_mmioaddr = v3->start_mmioaddr;  in parse_dmc_fw_header()
688 	} else if (dmc_header->header_ver == 1) {  in parse_dmc_fw_header()
695 		mmioaddr = v1->mmioaddr;  in parse_dmc_fw_header()
696 		mmiodata = v1->mmiodata;  in parse_dmc_fw_header()
697 		mmio_count = v1->mmio_count;  in parse_dmc_fw_header()
699 		header_len_bytes = dmc_header->header_len;  in parse_dmc_fw_header()
703 		drm_err(&i915->drm, "Unknown DMC fw header version: %u\n",  in parse_dmc_fw_header()
704 			dmc_header->header_ver);  in parse_dmc_fw_header()
709 		drm_err(&i915->drm, "DMC firmware has wrong dmc header length "  in parse_dmc_fw_header()
716 		drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);  in parse_dmc_fw_header()
721 					dmc_header->header_ver, dmc_id)) {  in parse_dmc_fw_header()
722 		drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n");  in parse_dmc_fw_header()
726 	drm_dbg_kms(&i915->drm, "DMC %d:\n", dmc_id);  in parse_dmc_fw_header()
728 		dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);  in parse_dmc_fw_header()
729 		dmc_info->mmiodata[i] = mmiodata[i];  in parse_dmc_fw_header()
731 		drm_dbg_kms(&i915->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n",  in parse_dmc_fw_header()
733 			    is_dmc_evt_ctl_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" :  in parse_dmc_fw_header()
734 			    is_dmc_evt_htp_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "",  in parse_dmc_fw_header()
735 			    disable_dmc_evt(i915, dmc_id, dmc_info->mmioaddr[i],  in parse_dmc_fw_header()
736 					    dmc_info->mmiodata[i]) ? " (disabling)" : "");  in parse_dmc_fw_header()
738 	dmc_info->mmio_count = mmio_count;  in parse_dmc_fw_header()
739 	dmc_info->start_mmioaddr = start_mmioaddr;  in parse_dmc_fw_header()
741 	rem_size -= header_len_bytes;  in parse_dmc_fw_header()
744 	payload_size = dmc_header->fw_size * 4;  in parse_dmc_fw_header()
748 	if (payload_size > dmc->max_fw_size) {  in parse_dmc_fw_header()
749 		drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size);  in parse_dmc_fw_header()
752 	dmc_info->dmc_fw_size = dmc_header->fw_size;  in parse_dmc_fw_header()
754 	dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);  in parse_dmc_fw_header()
755 	if (!dmc_info->payload)  in parse_dmc_fw_header()
759 	memcpy(dmc_info->payload, payload, payload_size);  in parse_dmc_fw_header()
764 	drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");  in parse_dmc_fw_header()
774 	struct drm_i915_private *i915 = dmc->i915;  in parse_dmc_fw_package()
782 	if (package_header->header_ver == 1) {  in parse_dmc_fw_package()
784 	} else if (package_header->header_ver == 2) {  in parse_dmc_fw_package()
787 		drm_err(&i915->drm, "DMC firmware has unknown header version %u\n",  in parse_dmc_fw_package()
788 			package_header->header_ver);  in parse_dmc_fw_package()
800 	if (package_header->header_len * 4 != package_size) {  in parse_dmc_fw_package()
801 		drm_err(&i915->drm, "DMC firmware has wrong package header length "  in parse_dmc_fw_package()
806 	num_entries = package_header->num_entries;  in parse_dmc_fw_package()
807 	if (WARN_ON(package_header->num_entries > max_entries))  in parse_dmc_fw_package()
813 			  package_header->header_ver);  in parse_dmc_fw_package()
819 	drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");  in parse_dmc_fw_package()
828 	struct drm_i915_private *i915 = dmc->i915;  in parse_dmc_fw_css()
831 		drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");  in parse_dmc_fw_css()
836 	    (css_header->header_len * 4)) {  in parse_dmc_fw_css()
837 		drm_err(&i915->drm, "DMC firmware has wrong CSS header length "  in parse_dmc_fw_css()
839 			(css_header->header_len * 4));  in parse_dmc_fw_css()
843 	dmc->version = css_header->version;  in parse_dmc_fw_css()
850 	struct drm_i915_private *i915 = dmc->i915;  in parse_dmc_fw()
864 	css_header = (struct intel_css_header *)fw->data;  in parse_dmc_fw()
865 	r = parse_dmc_fw_css(dmc, css_header, fw->size);  in parse_dmc_fw()
872 	package_header = (struct intel_package_header *)&fw->data[readcount];  in parse_dmc_fw()
873 	r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount);  in parse_dmc_fw()
880 		if (!dmc->dmc_info[dmc_id].present)  in parse_dmc_fw()
883 		offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4;  in parse_dmc_fw()
884 		if (offset > fw->size) {  in parse_dmc_fw()
885 			drm_err(&i915->drm, "Reading beyond the fw_size\n");  in parse_dmc_fw()
889 		dmc_header = (struct intel_dmc_header_base *)&fw->data[offset];  in parse_dmc_fw()
890 		parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id);  in parse_dmc_fw()
896 	drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref);  in intel_dmc_runtime_pm_get()
897 	i915->display.dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT);  in intel_dmc_runtime_pm_get()
903 		fetch_and_zero(&i915->display.dmc.wakeref);  in intel_dmc_runtime_pm_put()
919 	struct drm_i915_private *i915 = dmc->i915;  in dmc_load_work_fn()
924 	err = request_firmware(&fw, dmc->fw_path, i915->drm.dev);  in dmc_load_work_fn()
926 	if (err == -ENOENT && !i915->params.dmc_firmware_path) {  in dmc_load_work_fn()
929 			drm_dbg_kms(&i915->drm, "%s not found, falling back to %s\n",  in dmc_load_work_fn()
930 				    dmc->fw_path, fallback_path);  in dmc_load_work_fn()
931 			err = request_firmware(&fw, fallback_path, i915->drm.dev);  in dmc_load_work_fn()
933 				dmc->fw_path = fallback_path;  in dmc_load_work_fn()
943 		drm_info(&i915->drm, "Finished loading DMC firmware %s (v%u.%u)\n",  in dmc_load_work_fn()
944 			 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version),  in dmc_load_work_fn()
945 			 DMC_VERSION_MINOR(dmc->version));  in dmc_load_work_fn()
947 		drm_notice(&i915->drm,  in dmc_load_work_fn()
950 			   dmc->fw_path);  in dmc_load_work_fn()
951 		drm_notice(&i915->drm, "DMC firmware homepage: %s",  in dmc_load_work_fn()
959  * intel_dmc_init() - initialize the firmware loading.
974 	 * runtime-suspend.  in intel_dmc_init()
986 	dmc->i915 = i915;  in intel_dmc_init()
988 	INIT_WORK(&dmc->work, dmc_load_work_fn);  in intel_dmc_init()
991 		dmc->fw_path = MTL_DMC_PATH;  in intel_dmc_init()
992 		dmc->max_fw_size = XELPDP_DMC_MAX_FW_SIZE;  in intel_dmc_init()
994 		dmc->fw_path = DG2_DMC_PATH;  in intel_dmc_init()
995 		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;  in intel_dmc_init()
997 		dmc->fw_path = ADLP_DMC_PATH;  in intel_dmc_init()
998 		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;  in intel_dmc_init()
1000 		dmc->fw_path = ADLS_DMC_PATH;  in intel_dmc_init()
1001 		dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;  in intel_dmc_init()
1003 		dmc->fw_path = DG1_DMC_PATH;  in intel_dmc_init()
1004 		dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;  in intel_dmc_init()
1006 		dmc->fw_path = RKL_DMC_PATH;  in intel_dmc_init()
1007 		dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;  in intel_dmc_init()
1009 		dmc->fw_path = TGL_DMC_PATH;  in intel_dmc_init()
1010 		dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE;  in intel_dmc_init()
1012 		dmc->fw_path = ICL_DMC_PATH;  in intel_dmc_init()
1013 		dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE;  in intel_dmc_init()
1015 		dmc->fw_path = GLK_DMC_PATH;  in intel_dmc_init()
1016 		dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE;  in intel_dmc_init()
1020 		dmc->fw_path = KBL_DMC_PATH;  in intel_dmc_init()
1021 		dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE;  in intel_dmc_init()
1023 		dmc->fw_path = SKL_DMC_PATH;  in intel_dmc_init()
1024 		dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE;  in intel_dmc_init()
1026 		dmc->fw_path = BXT_DMC_PATH;  in intel_dmc_init()
1027 		dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE;  in intel_dmc_init()
1030 	if (i915->params.dmc_firmware_path) {  in intel_dmc_init()
1031 		if (strlen(i915->params.dmc_firmware_path) == 0) {  in intel_dmc_init()
1032 			drm_info(&i915->drm,  in intel_dmc_init()
1037 		dmc->fw_path = i915->params.dmc_firmware_path;  in intel_dmc_init()
1040 	if (!dmc->fw_path) {  in intel_dmc_init()
1041 		drm_dbg_kms(&i915->drm,  in intel_dmc_init()
1046 	i915->display.dmc.dmc = dmc;  in intel_dmc_init()
1048 	drm_dbg_kms(&i915->drm, "Loading %s\n", dmc->fw_path);  in intel_dmc_init()
1049 	queue_work(i915->unordered_wq, &dmc->work);  in intel_dmc_init()
1058  * intel_dmc_suspend() - prepare DMC firmware before system suspend
1073 		flush_work(&dmc->work);  in intel_dmc_suspend()
1081  * intel_dmc_resume() - init DMC firmware during system resume
1101  * intel_dmc_fini() - unload the DMC firmware.
1116 	drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref);  in intel_dmc_fini()
1120 			kfree(dmc->dmc_info[dmc_id].payload);  in intel_dmc_fini()
1123 		i915->display.dmc.dmc = NULL;  in intel_dmc_fini()
1140 				  DMC_VERSION_MAJOR(dmc->version),  in intel_dmc_print_error_state()
1141 				  DMC_VERSION_MINOR(dmc->version));  in intel_dmc_print_error_state()
1146 	struct drm_i915_private *i915 = m->private;  in intel_dmc_debugfs_status_show()
1152 		return -ENODEV;  in intel_dmc_debugfs_status_show()
1154 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);  in intel_dmc_debugfs_status_show()
1159 	seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A");  in intel_dmc_debugfs_status_show()
1173 	seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),  in intel_dmc_debugfs_status_show()
1174 		   DMC_VERSION_MINOR(dmc->version));  in intel_dmc_debugfs_status_show()
1197 	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg));  in intel_dmc_debugfs_status_show()
1199 		seq_printf(m, "DC5 -> DC6 count: %d\n",  in intel_dmc_debugfs_status_show()
1203 		   intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));  in intel_dmc_debugfs_status_show()
1210 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);  in intel_dmc_debugfs_status_show()
1219 	struct drm_minor *minor = i915->drm.primary;  in intel_dmc_debugfs_register()
1221 	debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root,  in intel_dmc_debugfs_register()